Revision 1.1
Jan. 2004

R0201-BS62LV4007

Very Low Power/Voltage CMOS SRAM
512K X 8 bit

· Vcc operation voltage : 4.5V ~ 5.5V
· Very low power consumption :

Vcc = 5.0V C-grade: 68mA (@55ns) operating current

I -grade: 70mA (@55ns) operating current

C-grade: 58mA (@70ns) operating current

I -grade: 60mA (@70ns) operating current

2.0uA (Typ.) CMOS standby current

· High speed access time :

-55 55ns
-70 70ns

· Automatic power down when chip is deselected
· Fully static operation

The BS62LV4007 is a high performance, very low power CMOS
Static Random Access Memory organized as 524,288 words by 8 bits
and operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
2.0uA at

5.0V/25

and maximum access time of 55ns at

5.0V/85

Easy memory expansion is provided by an active LOW chip enable
(CE) , and active LOW output enable (OE) and three-state output
drivers.
The BS62LV4007 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV4007 is available in the JEDEC standard 32L SOP, TSOP
, PDIP, TSOP II and STSOP package.

DESCRIPTION

FEATURES

BLOCK DIAGRAM

PRODUCT FAMILY

PIN CONFIGURATIONS

Brilliance Semiconductor, Inc

. reserves the right to modify document contents without notice.

Address

Input

Buffer

Row

Decoder

Memory Array

2048 X 2048

Column I/O

Write Driver
Sense Amp

Column Decoder

Data

Buffer

Output

Address Input Buffer

Data

Buffer

Input

Control

GND

Vdd

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

A13
A17
A15
A18
A16
A14
A12

A7
A6
A5
A4

256

2048

A11 A9 A8 A3 A2 A1 A0 A10

BS62LV4007

BSI

POWER DISSIPATION

SPEED

( ns )

STANDBY

( I

CCSB1

, Max )

Operating

( I

, Max )

PKG

TYPE

BS62LV4007TC

TSOP

BS62LV4007STC

STSOP

BS62LV4007SC

SOP

BS62LV4007EC

TSOP2

BS62LV4007PC

C to +70

4.5V ~ 5.5V

55 / 70

30uA

68mA

58mA

PDIP

BS62LV4007TI

TSOP

BS62LV4007STI

STSOP

BS62LV4007SI

SOP

BS62LV4007EI

TSOP2

BS62LV4007PI

C to +85

4.5V ~ 5.5V

55 / 70

60uA

70mA

60mA

PDIP

OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3

A11

A9
A8

A13

A17
A15

VCC

A18
A16
A14
A12

A7
A6
A5
A4

BS62LV4007TC
BS62LV4007STC
BS62LV4007TI
BS62LV4007STI

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A18
A16
A14
A12

A7
A6
A5
A4
A3
A2
A1
A0

DQ0
DQ1
DQ2

GND

VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

BS62LV4007SC
BS62LV4007SI
BS62LV4007EC
BS62LV4007EI
BS62LV4007PC
BS62LV4007PI

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

55ns :4.5~5.5V

Vcc = 5.0V Vcc =5.0V

· Data retention supply voltage as low as 1.5V
· Easy expansion with CE and OE options
· Three state outputs and TTL compatible

70ns :4.5~5.5V

55ns

70ns

Vcc =5.0V

Revision 1.1
Jan. 2004

R0201-BS62LV4007

Name

Function

A0-A18 Address Input

These 19 address inputs select one of the 524,288 x 8-bit words in the RAM

CE Chip Enable Input

CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.

WE Write Enable Input

The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

DQ0-DQ7 Data Input/Output
Ports

These 8 bi-directional ports are used to read data from or write data into the RAM.

Vcc

Power Supply

GND

Ground

TRUTH TABLE

PIN DESCRIPTIONS

BSI

MODE

I/O OPERATION

Vcc CURRENT

Not selected

High Z

CCSB

, I

CCSB1

Output Disabled

High Z

Read

OUT

Write

SYMBOL

PARAMETER

CONDITIONS

MAX.

UNIT

Input
Capacitance

=0V

6 pF

Input/Output
Capacitance

I/O

=0V

8 pF

ABSOLUTE MAXIMUM RATINGS

(1)

OPERATING RANGE

CAPACITANCE

(1)

(TA = 25

C, f = 1.0 MHz)

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.

1. This parameter is guaranteed and not 100% tested.

SYMBOL

PARAMETER

RATING

UNITS

TERM

Terminal Voltage with
Respect to GND

-0.5 to

Vcc+0.5

BIAS

Temperature Under Bias

-40 to +85

STG

Storage Temperature

-60 to +150

Power Dissipation

1.0 W

OUT

DC Output Current

BS62LV4007

RANGE

AMBIENT

TEMPERATURE

Vcc

Commercial 0

C to +70

4.5V ~ 5.5V

Industrial -40

C to +85

4.5V ~ 5.5V

Revision 1.1
Jan. 2004

R0201-BS62LV4007

1. Typical characteristics are at T

= 25

C. 2. Fmax = 1/t

3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. I

SB1_MAX.

is 30uA at Vcc=5.0V and T

=70

5. Icc_

MAX.

is 68mA(@55ns) / 58mA(@70ns) at Vcc=5.0V and T

=0~70

DATA RETENTION CHARACTERISTICS

( TA = -40 to + 85

C )

1. Vcc = 1.5V, T

= + 25

2. t

= Read Cycle Time

3. I

MAX.

is 0.8uA at T

=70

DC ELECTRICAL CHARACTERISTICS

( TA = -40 to + 85

C )

BSI

LOW V

DATA RETENTION WAVEFORM

( CE Controlled )

Data Retention Mode

Vcc

CDR

Vcc

Vcc

1.5V

CE Vcc - 0.2V

BS62LV4007

SYMBOL

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Vcc for Data Retention

CE Vcc - 0.2V
V

Vcc - 0.2V or V

0.2V

1.5 -- --

CCDR

Data Retention Current

CE Vcc - 0.2V
V

Vcc - 0.2V or V

0.2V

-- 0.3 1.3

CDR

Chip Deselect to Data
Retention Time

0 -- --

Operation Recovery Time

See Retention Waveform

(2)

-- --

PARAMETER

NAME

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Guaranteed Input Low
Voltage

(3)

-0.5

0.8

Guaranteed Input High
Voltage

(3)

2.2

Vcc+0.3

Input Leakage Current

Vcc = Max, V

= 0V to Vcc

Output Leakage Current

Vcc = Max, CE = V

, or OE = V

I/O

= 0V to Vcc

Output Low Voltage

Output High Voltage

Vcc = Min, I

= -1.0mA

Operating Power Supply

Current

CE = V

, I

= 0mA,

F=Fmax

(2)

CCSB

Standby Current-TTL

CE = V

, I

= 0mA

1.0

CCSB1

CE Vcc-0.2V,
V

Vcc - 0.2V or V

0.2V

Vcc = 5.0 V

Standby Current-CMOS

Vcc = 5.0 V

2.4

0.4

2.0

Vcc = Max, I

= 2.0mA

(5)

(4)

70ns

55ns

Revision 1.1
Jan. 2004

R0201-BS62LV4007

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

MUST BE
STEADY

MAY CHANGE
FROM H TO L

DON T CARE:
ANY CHANGE
PERMITTED

DOES NOT
APPLY

MUST BE
STEADY

WILL BE
CHANGE
FROM H TO L

CHANGE :
STATE
UNKNOWN

CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE

MAY CHANGE
FROM L TO H

WILL BE
CHANGE
FROM L TO H

BSI

BS62LV4007

AC TEST CONDITIONS

(Test Load and Input/Output Reference)

Input Pulse Levels

Vcc / 0V

Input Rise and Fall Times

1V/ns

Input and Output
Timing Reference Level

0.5Vcc

Output Load

= 30pF+1TTL

= 100pF+1TTL

AC ELECTRICAL CHARACTERISTICS

( TA = -40 to + 85

C )

READ CYCLE

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

UNIT

AVAX

Read Cycle Time

AVQV

Address Access Time

ELQV

ACS

Chip Select Access Time

GLQV

Output Enable to Output Valid

ELQX

CLZ

Chip Select to Output Low Z

GLQX

OLZ

Output Enable to Output in Low Z

EHQZ

CHZ

Chip Deselect to Output in High Z

GHQZ

OHZ

Output Disable to Output in High Z

AXOX

Data Hold from Address Change

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

(1,2,4)

OUT

ADDRESS

MIN. TYP. MAX.

(Vcc = 4.5~5.5V)

MIN. TYP. MAX.

(Vcc = 4.5~5.5V)

CYCLE TIME : 55ns

CYCLE TIME : 70ns

Revision 1.1
Jan. 2004

JEDEC

PARAMETER

NAME

DESCRIPTION

UNIT

AVAX

Write Cycle Time

E1LWH

Chip Select to End of Write

AVWL

Address Set up Time

AVWH

Address Valid to End of Write

WLWH

Write Pulse Width

WHAX

Write Recovery Time

(CE , WE)

WLOZ

WHZ

Write to Output in High Z

DVWH

Data to Write Time Overlap

WHDX

Data Hold from Write Time

GHOZ

OHZ

Output Disable to Output in High Z

WHQX

End ot Write to Output Active

R0201-BS62LV4007

AC ELECTRICAL CHARACTERISTICS

( TA = -40 to + 85

C )

WRITE CYCLE

BSI

BS62LV4007

PARAMETER

NAME

MIN. TYP. MAX.

(Vcc = 4.5~5.5V)

MIN. TYP. MAX.

(Vcc = 4.5~5.5V)

SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

(1)

(3)

(11)

(2)

OHZ

(4,10)

OUT

ADDRESS

(5)

CYCLE TIME : 55ns

CYCLE TIME : 70ns

Revision 1.1
Jan. 2004

R0201-BS62LV4007

BSI

BS62LV4007

WRITE CYCLE2

(1,6)

(11)

(2)

WHZ

(4,10)

OUT

ADDRESS

(5)

(7)

(8)

(8,9)

NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals

must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.

3. T

is measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase

to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

7. D

OUT

is the same phase of write data of this write cycle.

8. D

OUT

is the read data of next address.

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

10. The parameter is guaranteed but not 100% tested.
11. T

is measured from the later of CE going low to the end of write.

Revision 1.1
Jan. 2004

BSI

BS62LV4007

R0201-BS62LV4007

ORDERING INFORMATION

PACKAGE DIMENSIONS

BASE METAL

WITH PLATING

c c1

SECTION A-A

SOP -32

Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.

BS62LV4007 X X

Y Y

GRADE
C: +0

C ~ +70

I: -40

C ~ +85

SPEED
55: 55ns
70: 70ns

PKG MATERIAL
-: Normal
G: Green
P: Pb free

PACKAGE
S: SOP
E: TSOP 2
ST: Small TSOP
T: TSOP
P: PDIP

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: BS62LV4007TC-70