Revision 2.4
April 2002

R0201-BS62UV4000

Ultra Low Power/Voltage CMOS SRAM
512K X 8 bit

· Ultra low operation voltage : 1.8V ~ 3.6V
· Ultra low power consumption :

Vcc = 2.0V C-grade: 15mA (Max.) operating current

I -grade: 20mA (Max.) operating current

0.2uA (Typ.) CMOS standby current

Vcc = 3.0V C-grade: 20mA (Max.) operating current

I -grade: 25mA (Max.) operating current
0.25uA (Typ.) CMOS standby current

· High speed access time :

-70 70ns (Max.) at Vcc = 2.0V
-10 100ns (Max.) at Vcc = 2.0V

· Automatic power down when chip is deselected
· Three state outputs and TTL compatible
· Fully static operation
· Data retention supply voltage as low as 1.5V
· Easy expansion with CE and OE options

The BS62UV4000 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 524,288 words by 8 bits
and operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.2uA and maximum access time of 70ns in 2.0V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE), and active LOW output enable (OE) and three-state
output drivers.
The BS62UV4000 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62UV4000 is available in the JEDEC standard 32 pin SOP
, TSOP, TSOP II and STSOP

DESCRIPTION

FEATURES

BLOCK DIAGRAM

PRODUCT FAMILY

PIN CONFIGURATIONS

Brilliance Semiconductor Inc

. reserves the right to modify document contents without notice.

Address

Input

Buffer

Row

Decoder

Memory Array

2048 X 2048

Column I/O

Sense Amp

Write Driver

Column Decoder

Data

Buffer

Output

Address Input Buffer

Data

Buffer

Input

Control

GND

Vdd

DQ5

DQ4

A13
A17
A15
A18
A16
A14
A12

A7
A6
A5
A4

DQ7

DQ6

DQ3

DQ2

DQ1

DQ0

256

2048

A11 A9 A8 A3 A2 A1 A0 A10

BS62UV4000

BSI

POWER DISSIPATION

SPEED

( ns )

STANDBY

( I

CCSB1

, Max )

Operating

( I

, Max )

PKG

TYPE

BS62UV4000TC

TSOP

BS62UV4000STC

STSOP

BS62UV4000SC

SOP

BS62UV4000EC

TSOP2

BS62UV4000PC

C to +70

1.8V ~ 3.6V

70 / 100

1uA

1.5uA

15mA

20mA

PDIP

BS62UV4000TI

TSOP

BS62UV4000STI

STSOP

BS62UV4000SI

SOP

BS62UV4000EI

TSOP2

BS62UV4000PI

C to +85

1.8V ~ 3.6V

70 / 100

2uA

3uA

20mA

25mA

PDIP

OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3

A11

A9
A8

A13

A17
A15

A18
A16
A14
A12

A7
A6
A5
A4

BS62UV4000TC
BS62UV4000STC
BS62UV4000TI
BS62UV4000STI

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A18
A16
A14
A12

A7
A6
A5
A4
A3
A2
A1
A0

DQ0
DQ1
DQ2

GND

VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

BS62UV4000SC
BS62UV4000SI
BS62UV4000EC
BS62UV4000EI
BS62UV4000PC
BS62UV4000PI

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

Vcc = 2.0V

Vcc =3.0V Vcc =3.0V

Revision 2.4
April 2002

R0201-BS62UV4000

Name

Function

A0-A18 Address Input

These 19 address inputs select one of the 524,288 x 8-bit words in the RAM

CE Chip Enable Input

CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.

WE Write Enable Input

The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

DQ0-DQ7 Data Input/Output
Ports

These 8 bi-directional ports are used to read data from or write data into the RAM.

Vcc

Power Supply

GND

Ground

TRUTH TABLE

PIN DESCRIPTIONS

BSI

MODE

I/O OPERATION

Vcc CURRENT

Not selected

SB1

High Z

CCSB

, I

Output Disabled

High Z

Read

OUT

Write

SYMBOL

PARAMETER

CONDITIONS

MAX.

UNIT

Input
Capacitance

=0V

6 pF

Input/Output
Capacitance

I/O

=0V

8 pF

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.

1. This parameter is guaranteed and not tested.

ABSOLUTE MAXIMUM RATINGS

(1)

OPERATING RANGE

CAPACITANCE

(1)

(TA = 25

C, f = 1.0 MHz)

SYMBOL

PARAMETER

RATING

UNITS

TERM

Terminal Voltage with
Respect to GND

-0.5 to

Vcc+0.5

BIAS

Temperature Under Bias

-40 to +125

STG

Storage Temperature

-60 to +150

Power Dissipation

1.0

OUT

DC Output Current

BS62UV4000

RANGE

AMBIENT

TEMPERATURE

Vcc

Commercial

C to +70

1.8V ~ 3.6V

Industrial

-40

C to +85

1.8V ~ 3.6V

Revision 2.4
April 2002

R0201-BS62UV4000

1. Typical characteristics are at TA = 25

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t

DATA RETENTION CHARACTERISTICS

( TA = 0 to + 70

C )

1. Vcc = 1.5V, T

= + 25

2. t

= Read Cycle Time

DC ELECTRICAL CHARACTERISTICS

( TA = 0 to + 70

C )

BSI

LOW V

DATA RETENTION WAVEFORM

( CE Controlled )

Data Retention Mode

Vcc

CDR

Vcc

Vcc

1.5V

CE Vcc - 0.2V

BS62UV4000

SYMBOL

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Vcc for Data Retention

Vcc - 0.2V

Vcc - 0.2V or V

0.2V

1.5 -- --

CCDR

Data Retention Current

Vcc - 0.2V

Vcc - 0.2V or V

0.2V

-- 0.1 1

CDR

Chip Deselect to Data
Retention Time

0 -- --

Operation Recovery Time

See Retention Waveform

(2)

-- --

PARAMETER

NAME

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Guaranteed Input Low

(2)

Voltage

-0.5

0.6

Guaranteed Input High
Voltage

(2)

2.0

Vcc+0.2

Input Leakage Current

= 0V to Vcc

Vcc = Max, V

Output Leakage Current

Vcc = Max, CE = V

, or OE = V

I/O

= 0V to Vcc

Output Low Voltage

= 1mA

Vcc = Max, I

Output High Voltage

Vcc = Min, I

= -0.5mA

1.6

Operating Power Supply

Current

CE = V

, I

= 0mA, F = Fmax

(3)

CCSB

Standby Current-TTL

, I

= 0mA

CE = V

CCSB1

CE
V

Vcc-0.2V,
Vcc - 0.2V or V

0.2V

0.2

1.5

Vcc = 2.0 V

Vcc = 3.0 V

Vcc = 2.0 V

Standby Current-CMOS

Vcc = 3.0 V

Vcc = 2.0 V

Vcc = 3.0 V

Vcc = 2.0 V

0.8

1.4

2.4

0.4

0.6

0.25

Revision 2.4
April 2002

R0201-BS62UV4000

Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level

Vcc/0
5ns

0.5Vcc

AC ELECTRICAL CHARACTERISTICS

( TA = 0 to + 70

C , Vcc = 2.0V )

READ CYCLE

AC TEST CONDITIONS

AC TEST LOADS AND WAVEFORMS

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

MUST BE
STEADY

MAY CHANGE
FROM H TO L

DON T CAR
ANY CHANG
PERMITTED

CHANGE :

STATE

DOES NOT
APPLY

MUST BE
STEADY

WILL BE
CHANGE
FROM H TO L

UNKNOWN

CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE

MAY CHANGE
FROM L TO H

WILL BE
CHANGE
FROM L TO H

BSI

BS62UV4000

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

BS62UV4000-70

MIN. TYP. MAX.

BS62UV4000-10

MIN. TYP. MAX.

UNIT

AVAX

Read Cycle Time

100

AVQV

Address Access Time

100

ELQV

ACS

Chip Select Access Time

100

GLQV

Output Enable to Output Valid

ELQX

CLZ

Chip Select to Output Low Z

GLQX

OLZ

Output Enable to Output in Low Z

EHQZ

CHZ

Chip Deselect to Output in High Z

GHQZ

OHZ

Output Disable to Output in High Z

AXOX

Output Disable to Output Address Change

800

THEVENIN EQUIVALENT

ALL INPUT PULSES

10%

90%

Vcc

GND

5ns

90%

10%

1.2V

OUTPUT

FIGURE 2

OUTPUT

INCLUDING
JIG AND
SCOPE

1333

2000

5PF

FIGURE 1B

OUTPUT

INCLUDING
JIG AND
SCOPE

1333

100PF

FIGURE 1A

2000

Revision 2.4
April 2002

R0201-BS62UV4000

NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V

3. Address valid prior to or coincident with CE transition low.
4. OE = V

5. Transition is measured 500mV from steady state with C

= 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

BSI

BS62UV4000

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

(1,2,4)

OUT

ADDRESS

READ CYCLE3

(1,4)

READ CYCLE2

(1,3,4)

CLZ

CHZ

(5)

OUT

(5)

ACS

OUT

ADDRESS

CLZ

(5)

ACS

CHZ

(1,5)

OHZ

(5)

OLZ

Revision 2.4
April 2002

JEDEC

PARAMETER

NAME

DESCRIPTION

BS62UV4000-70

MIN. TYP. MAX.

BS62UV4000-10

MIN. TYP. MAX.

UNIT

AVAX

Write Cycle Time

100

E1LWH

Chip Select to End of Write

100

AVWL

Address Set up Time

AVWH

Address Valid to End of Write

100

WLWH

Write Pulse Width

WHAX

Write Recovery Time

(CE , WE)

WLOZ

WHZ

Write to Output in High Z

DVWH

Data to Write Time Overlap

WHDX

Data Hold from Write Time

GHOZ

OHZ

Output Disable to Output in High Z

WHQX

End ot Write to Output Active

R0201-BS62UV4000

AC ELECTRICAL CHARACTERISTICS

( TA = 0 to + 70

C , Vcc = 2.0V )

WRITE CYCLE

BSI

BS62UV4000

SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

(1)

(3)

(11)

(2)

OHZ

(4,10)

OUT

ADDRESS

(5)

PARAMETER

NAME

Revision 2.4
April 2002

R0201-BS62UV4000

BSI

BS62UV4000

WRITE CYCLE2

(1,6)

(11)

(2)

WHZ

(4,10)

OUT

ADDRESS

(5)

(7)

(8)

(8,9)

NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals

must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.

3. T

is measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase

to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

7. D

OUT

is the same phase of write data of this write cycle.

8. D

OUT

is the read data of next address.

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C

= 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

11. T

is measured from the later of CE going low to the end of write.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: BS62UV4000TC

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: BS62UV4000TC