1
2-
POWER DISSIPATION
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
(ns)
Vcc=
2.2V
Vcc=
1.5V
Vcc=
2.2V
Vcc=
1.5V
PKG TYPE
BS62XV1024SC
SOP-32
BS62XV1024TC
TSOP-32
BS62XV1024STC
+0
O
C to +70
O
C
1.2V ~ 2.4V
250
0.3uA
0.2uA
15mA
10mA
STSOP-32
BS62XV1024SI
SOP-32
BS62XV1024TI
TSOP-32
BS62XV1024STI
-40
O
C to +85
O
C
1.2V ~ 2.4V
250
1uA
0.8uA
15mA
10mA
STSOP-32
Brilliance Semiconductor Inc
.
reserves the right to modify document contents without notice.
Revision 1.0
March 2000
R0201-BS62XV1024
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A7
BSI
Extremely Low Power/Voltage CMOS SRAM
128K X 8 bit
Extremely low operation voltage : 1.2V ~ 2.4V
Extremely low power consumption :
Vcc = 1.5V 10mA (Max.) write current
0.5mA (Max.) read current
0.005uA (Typ.) CMOS standby current
Vcc = 2.2V 15mA (Max.) write current
0.8mA (Max.) read current
0.01uA (Typ.) CMOS standby current
High speed access time :
-25 250ns (Max.)
Input levels are CMOS-compatible
Automatic power down when chip is deselected
Three state outputs
Fully static operation
Data retention supply voltage as low as 1.2V
Easy expansion with CE2, CE1, and OE options
All I/O pins are 3.3V tolerant
The BS62XV1024 is a high performance, extremely low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from an extremely low range of 1.2V to 2.4V supply
voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.005uA and maximum access time of 250ns in 1.5V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62XV1024 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62XV1024 is available in the JEDEC standard 32 pin
525mil Plastic SOP, 8mmx13.4mm STSOP, and 8mmx20mm TSOP.
!
DESCRIPTION
!
FEATURES
!
BLOCK DIAGRAM
!
PRODUCT FAMILY
!
PIN CONFIGURATIONS
Address
Input
Buffer
Row
Decoder
Memory Array
1024 x 1024
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
Address Input Buffer
A3 A2 A1 A0 A10
Data
Buffer
Input
Control
Gnd
Vdd
OE
WE
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A14
A9
A11
A8
A13
A12
A6
8
8
8
8
14
128
1024
1024
20
A16
A15
A4
BS62XV1024
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
A5
CE2
BS62XV1024SC
BS62XV1024SI
BS62XV1024TC
BS62XV1024STC
BS62XV1024TI
BS62XV1024STI
2
2-
BSI
Revision 1.0
March 2000
R0201-BS62XV1024
Name
Function
A0-A16 Address Input
These 17 address input select one of the 131,072 x 8-bit words in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read
from or write to the device. If either chip enable is not active, the device is deselected
and is in a standby power mode. The DQ pins will be in the high impedance state
when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0 DQ7 Data Input/Output
Ports
These 8 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
!
TRUTH TABLE
!
PIN DESCRIPTIONS
MODE
WE
CE1
CE2
OE
I/O OPERATION
Vcc CURRENT
X
H
X
X
Not selected
(Power Down)
X
X
L
X
High Z
I
CCSB
, I
CCSB1
Output Disabled
H
L
H
H
High Z
I
CC
Read
H
L
H
L
D
OUT
I
CC
Write
L
L
H
X
D
IN
I
CC
BS62XV1024
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
C
IN
Input
Capacitance
V
IN
=0V
6
pF
C
DQ
Input/Output
Capacitance
V
I/O
=0V
8
pF
!
ABSOLUTE MAXIMUM RATINGS
(1)
!
OPERATING RANGE
!
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not tested.
SYMBOL
PARAMETER
RATING
UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to +6.0
V
T
BIAS
Temperature Under Bias
-40 to +125
O
C
T
STG
Storage Temperature
-60 to +150
O
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
20
mA
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0
O
C to +70
O
C
1.2V ~ 2.4V
Industrial
-40
O
C to +70
O
C
1.2V ~ 2.4V
3
2-
BSI
Revision 1.0
March 2000
R0201-BS62XV1024
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
IL
Guaranteed Input Low
Voltage
(2)
-0.5
--
0.3Vcc
V
V
IH
Guaranteed Input High
Voltage
(2)
0.7Vcc
--
Vcc+0.2
V
I
IL
Input Leakage Current
Vcc = Max, V
IN
= 0V to Vcc
--
--
1
uA
I
OL
Output Leakage Current
Vcc = Max, CE1= V
IH
, CE2= V
IL,
or
OE = V
IH
, V
I/O
= 0V to Vcc
--
--
1
uA
V
OL
Output Low Voltage
Vcc = Max, I
OL
= 1mA
--
--
0.3
V
V
OH
Output High Voltage
Vcc = Min, I
OH
= -0.5mA
1.2
--
--
V
Vcc=1.5V
--
--
10
I
CC
Operating Power Supply
Current
CE1 = V
IL
, or CE2 = V
IH
,
I
DQ
= 0mA, F = Fmax
(3)
Vcc=2.2V
--
--
15
mA
Vcc=1.5V
--
--
0.5
I
CCSB
Standby Power Supply
Current
CE1 = V
IH
, or CE2 = V
IL
,
I
DQ
= 0mA, F = Fmax
(3)
Vcc=2.2V
--
--
1
mA
Vcc=1.5V
--
0.005
0.2
I
CCSB1
Power Down Supply
Current
CE1
Vcc-0.2V, CE2
0.2V,
V
IN
Vcc-0.2V or V
IN
0.2V
Vcc=2.2V
--
0.01
0.3
uA
1. Typical characteristics are at TA = 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
RC
.
!
DATA RETENTION CHARACTERISTICS
( TA = 0 to + 70
o
C )
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
!
DC ELECTRICAL CHARACTERISTICS
( TA = 0 to + 70
o
C )
!
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
CE
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.2V
CE Vcc - 0.2V
BS62XV1024
!
LOW V
CC
DATA RETENTION WAVEFORM (2)
( CE2 Controlled )
CE2
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.2V
CE2 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
DR
Vcc for Data Retention
CE1
Vcc - 0.2V, CE2
0.2V,
VIN
Vcc - 0.2V or VIN
0.2V
1.2
--
--
V
I
CCDR
Data Retention Current
CE1
Vcc - 0.2V, CE2
0.2V,
VIN
Vcc - 0.2V or VIN
0.2V
--
0.005
0.1
uA
t
CDR
Chip Deselect to Data
Retention Time
0
--
--
ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
--
--
ns
4
2-
BSI
Revision 1.0
March 2000
R0201-BS62XV1024
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS62XV1024-25
MIN. TYP. MAX.
UNIT
t
AVAX
t
RC
Read Cycle Time
250
--
--
ns
t
AVQV
t
AA
Address Access Time
--
--
250
ns
t
E1LQV
t
ACS1
Chip Select Access Time
(CE1)
--
--
250
ns
t
E2HOV
t
ACS2
Chip Select Access Time
(CE2)
--
--
250
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
--
150
ns
t
E1LQX
t
CLZ1
Chip Select to Output Low Z
(CE1)
15
--
--
ns
t
E2HOX
t
CLZ2
Chip Select to Output Low Z
(CE2)
10
--
--
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
10
--
--
ns
t
E1HQZ
t
CHZ1
Chip Deselect to Output in High Z
(CE1)
0
--
40
ns
t
E2HQZ
t
CHZ1
Chip Deselect to Output in High Z
(CE2)
40
t
GHQZ
t
OHZ
Output Disable to Output in High Z
0
--
35
ns
t
AXOX
t
OH
Output Disable to Output Address Change
10
--
--
ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
!
AC ELECTRICAL CHARACTERISTICS
(over the operating range)
READ CYCLE
!
AC TEST CONDITIONS
!
AC TEST LOADS AND WAVEFORMS
!
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
1. Typical characteristics are at Vcc = 1.5V, T
A
= 25
o
C.
BS62XV1024
600
THEVENIN EQUIVALENT
ALL INPUT PULSES
10%
90%
Vcc
GND
5ns
90%
10%
0.9V
OUTPUT
FIGURE 2
1.5V
OUTPUT
INCLUDING
JIG AND
SCOPE
1000
1500
5PF
FIGURE 1B
1.5V
OUTPUT
INCLUDING
JIG AND
SCOPE
1000
100PF
FIGURE 1A
1500
5
2-
BSI
Revision 1.0
March 2000
R0201-BS62XV1024
READ CYCLE3
(1,4)
READ CYCLE2
(1,3,4)
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE1 = V
IL
and CE2= V
IH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = V
IL
.
5. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
!
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
RC
t
OH
t
AA
D
OUT
ADDRESS
t
OH
t
CLZ
t
CHZ
(5)
D
OUT
CE2
CE1
(5)
t
ACS2
t
ACS1
t
OH
t
RC
t
OE
t
CLZ2
t
CHZ
(2,5)
D
OUT
CE2
CE1
OE
ADDRESS
(5)
t
CLZ1
(5)
t
ACS1
t
ACS2
t
CHZ
(1,5)
t
OHZ
(5)
t
OLZ
t
AA
BS62XV1024
6
2-
BSI
Revision 1.0
March 2000
R0201-BS62XV1024
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS62XV1024-25
MIN. TYP. MAX.
UNIT
t
AVAX
t
WC
Write Cycle Time
250
--
--
ns
t
E1LWH
t
CW
Chip Select to End of Write
250
--
--
ns
t
AVWL
t
AS
Address Set up Time
0
--
--
ns
t
AVWH
t
AW
Address Valid to End of Write
250
--
--
ns
t
WLWH
t
WP
Write Pulse Width
150
--
--
ns
t
WHAX
t
WR1
Write Recovery Time
(CE1 , WE)
0
--
--
ns
t
E2LAX
t
WR2
Write Recovery Time
(CE2)
0
--
--
ns
t
WLOZ
t
WHZ
Write to Output in High Z
--
--
40
ns
t
DVWH
t
DW
Data to Write Time Overlap
100
--
--
ns
t
WHDX
t
DH
Data Hold from Write Time
0
--
--
ns
t
GHOZ
t
OHZ
Output Disable to Output in High Z
0
--
40
ns
t
WHQX
t
OW
End of Write to Output Active
5
--
--
ns
!
AC ELECTRICAL CHARACTERISTICS
(over the operating range)
WRITE CYCLE
!
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
(1)
1. Typical characteristics are at Vcc = 1.5V, T
A
= 25
o
C.
t
WR1
t
WC
(3)
t
CW
(11)
(11)
t
CW
(2)
t
WP
t
AW
t
OHZ
(4,10)
t
AS
t
WR2
(3)
t
DH
t
DW
D
IN
D
OUT
WE
CE2
CE1
OE
ADDRESS
(5)
(5)
BS62XV1024
7
2-
BSI
Revision 1.0
March 2000
R0201-BS62XV1024
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
IL
).
7.
D
OUT
is the same phase of write data of this write cycle.
8. D
OUT
is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. T
CW
is measured from the later of CE1 going low or CE2 going high to the end of write.
WRITE CYCLE2
(1,6)
t
WC
t
CW
(11)
(11)
t
CW
(2)
t
WP
t
AW
t
WHZ
(4,10)
t
AS
t
WR2
(3)
t
DH
t
DW
D
IN
D
OUT
WE
CE2
CE1
ADDRESS
(5)
(5)
t
DH
(7)
(8)
(8)
BS62XV1024
8
2-
Revision 1.0
March 2000
R0201-BS62XV1024
PACKAGE
S: SOP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
!
ORDERING INFORMATION
BSI
BS62XV1024
X X
--
Y
Y
GRADE
C: +0
o
C ~ +70
o
C
I: -40
o
C ~ +85
o
C
SPEED
25: 250ns
!
PACKAGE DIMENSIONS
BS62XV1024
9
2-
Revision 1.0
March 2000
R0201-BS62XV1024
!
PACKAGE DIMENSIONS (continued)
BSI
BS62XV1024
10
2-
Revision 1.0
March 2000
R0201-BS62XV1024
This page is left blank intentionally.
BSI
BS62XV1024
11
2-
POWER DISSIPATION
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
(ns)
Vcc=
3.3V
Vcc=
2.0V
Vcc=
3.3V
Vcc=
2.0V
PKG TYPE
BS62UV1024SC
SOP-32
BS62UV1024TC
TSOP-32
BS62UV1024STC
+0
O
C to +70
O
C
1.8V ~ 3.6V
150
0.5uA
0.3uA
20mA
15mA
STSOP-32
BS62UV1024SI
SOP-32
BS62UV1024TI
TSOP-32
BS62UV1024STI
-40
O
C to +85
O
C
1.8V ~ 3.6V
150
1.5uA
1uA
20mA
15mA
STSOP-32
Revision 1.0
March 2000
R0201-BS62UV1024
BSI
Ultra Low Power/Voltage CMOS SRAM
128K X 8 bit
Ultra low operation voltage : 1.8V ~ 3.6V
Ultra low power consumption :
Vcc = 2.0V 15mA (Max.) write current
0.8mA (Max.) read current
0.01uA (Typ.) CMOS standby current
Vcc = 3.3V 20mA (Max.) write current
1mA (Max.) read current
0.02uA (Typ.) CMOS standby current
High speed access time :
-15 150ns (Max.)
Input levels are CMOS-compatible
Automatic power down when chip is deselected
Three state outputs
Fully static operation
Data retention supply voltage as low as 1.5V
Easy expansion with CE2, CE1, and OE options
All I/O pins are 3.3V tolerant
The BS62UV1024 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from a ultra low range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.01uA and maximum access time of 150ns in 2V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62UV1024 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62UV1024 is available in the JEDEC standard 32 pin
525mil Plastic SOP, 8mmx13.4mm STSOP, and 8mmx20mm TSOP.
!
DESCRIPTION
!
FEATURES
!
BLOCK DIAGRAM
!
PRODUCT FAMILY
!
PIN CONFIGURATIONS
Brilliance Semiconductor Inc
.
reserves the right to modify document contents without notice.
BS62UV1024
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
BS62UV1024SC
BS62UV1024SI
BS62UV1024TC
BS62UV1024STC
BS62UV1024TI
BS62UV1024STI
A7
Address
Input
Buffer
Row
Decoder
Memory Array
1024 x 1024
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
Address Input Buffer
A3 A2 A1 A0 A10
Data
Buffer
Input
Control
Gnd
Vdd
OE
WE
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A14
A9
A11
A8
A13
A12
A6
8
8
8
8
14
128
1024
1024
20
A16
A15
A4
A5
CE2
12
2-
Name
Function
A0-A16 Address Input
These 17 address input select one of the 131,072 x 8-bit words in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read
from or write to the device. If either chip enable is not active, the device is deselected
and is in a standby power mode. The DQ pins will be in the high impedance state
when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0 DQ7 Data Input/Output
Ports
These 8 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
Revision 1.0
March 2000
R0201-BS62UV1024
BSI
BS62UV1024
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
C
IN
Input
Capacitance
V
IN
=0V
6
pF
C
DQ
Input/Output
Capacitance
V
I/O
=0V
8
pF
!
ABSOLUTE MAXIMUM RATINGS
(1)
!
OPERATING RANGE
!
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not tested.
SYMBOL
PARAMETER
RATING
UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to +6.0
V
T
BIAS
Temperature Under Bias
-40 to +125
O
C
T
STG
Storage Temperature
-60 to +150
O
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
20
mA
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0
O
C to +70
O
C
1.8V ~ 3.6V
Industrial
-40
O
C to +70
O
C
1.8V ~ 3.6V
!
TRUTH TABLE
!
PIN DESCRIPTIONS
MODE
WE
CE1
CE2
OE
I/O OPERATION
Vcc CURRENT
X
H
X
X
Not selected
(Power Down)
X
X
L
X
High Z
I
CCSB
, I
CCSB1
Output Disabled
H
L
H
H
High Z
I
CC
Read
H
L
H
L
D
OUT
I
CC
Write
L
L
H
X
D
IN
I
CC
13
2-
Revision 1.0
March 2000
R0201-BS62UV1024
BSI
BS62UV1024
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
IL
Guaranteed Input Low
Voltage
(2)
-0.5
--
0.3Vcc
V
V
IH
Guaranteed Input High
Voltage
(2)
0.7Vcc
--
Vcc+0.2
V
I
IL
Input Leakage Current
Vcc = Max, V
IN
= 0V to Vcc
--
--
1
uA
I
OL
Output Leakage Current
Vcc = Max, CE1= V
IH
, CE2= V
IL,
or
OE = V
IH
, V
I/O
= 0V to Vcc
--
--
1
uA
V
OL
Output Low Voltage
Vcc = Max, I
OL
= 1mA
--
--
0.4
V
V
OH
Output High Voltage
Vcc = Min, I
OH
= -0.5mA
1.6
--
--
V
Vcc=2.0V
--
--
15
I
CC
Operating Power Supply
Current
CE1 = V
IL
, or CE2 = V
IH
,
I
DQ
= 0mA, F = Fmax
(3)
Vcc=3.3V
--
--
20
mA
Vcc=2.0V
--
--
0.5
I
CCSB
Standby Power Supply
Current
CE1 = V
IH
, or CE2 = V
IL
,
I
DQ
= 0mA, F = Fmax
(3)
Vcc=3.3V
--
--
1
mA
Vcc=2.0V
--
0.01
0.3
I
CCSB1
Power Down Supply
Current
CE1
Vcc-0.2V, CE2
0.2V,
V
IN
Vcc-0.2V or V
IN
0.2V
Vcc=3.3V
--
0.02
0.5
uA
1. Typical characteristics are at TA = 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
RC
.
!
DATA RETENTION CHARACTERISTICS
( TA = 0 to + 70
o
C )
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
!
DC ELECTRICAL CHARACTERISTICS
( TA = 0 to + 70
o
C )
!
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
CE
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.5V
CE Vcc - 0.2V
!
LOW V
CC
DATA RETENTION WAVEFORM (2)
( CE2 Controlled )
CE2
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.5V
CE2 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
DR
Vcc for Data Retention
CE1
Vcc - 0.2V, CE2
0.2V,
VIN
Vcc - 0.2V or VIN
0.2V
1.5
--
--
V
I
CCDR
Data Retention Current
CE1
Vcc - 0.2V, CE2
0.2V,
VIN
Vcc - 0.2V or VIN
0.2V
--
0.01
0.2
uA
t
CDR
Chip Deselect to Data
Retention Time
0
--
--
ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
--
--
ns
14
2-
Revision 1.0
March 2000
R0201-BS62UV1024
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS62UV1024-15
MIN. TYP. MAX.
UNIT
t
AVAX
t
RC
Read Cycle Time
150
--
--
ns
t
AVQV
t
AA
Address Access Time
--
--
150
ns
t
E1LQV
t
ACS1
Chip Select Access Time
(CE1)
--
--
150
ns
t
E2HOV
t
ACS2
Chip Select Access Time
(CE2)
--
--
150
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
--
100
ns
t
E1LQX
t
CLZ1
Chip Select to Output Low Z
(CE1)
10
--
--
ns
t
E2HOX
t
CLZ2
Chip Select to Output Low Z
(CE2)
10
--
--
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
10
--
--
ns
t
E1HQZ
t
CHZ1
Chip Deselect to Output in High Z
(CE1)
0
--
40
ns
t
E2HQZ
t
CHZ1
Chip Deselect to Output in High Z
(CE2)
0
40
t
GHQZ
t
OHZ
Output Disable to Output in High Z
0
--
35
ns
t
AXOX
t
OH
Output Disable to Output Address Change
10
--
--
ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
!
AC ELECTRICAL CHARACTERISTICS
(over the operating range)
READ CYCLE
!
AC TEST CONDITIONS
!
AC TEST LOADS AND WAVEFORMS
!
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
1. Typical characteristics are at Vcc = 2.0V, T
A
= 25
o
C.
BSI
BS62UV1024
800
THEVENIN EQUIVALENT
ALL INPUT PULSES
10%
90%
Vcc
GND
5ns
90%
10%
1.2V
OUTPUT
2V
OUTPUT
INCLUDING
JIG AND
SCOPE
1333
2000
5PF
FIGURE 1B
2V
OUTPUT
INCLUDING
JIG AND
SCOPE
1333
100PF
FIGURE 1A
2000
15
2-
Revision 1.0
March 2000
R0201-BS62UV1024
READ CYCLE3
(1,4)
READ CYCLE2
(1,3,4)
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE1 = V
IL
and CE2= V
IH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = V
IL
.
5. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
BSI
!
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
RC
t
OH
t
AA
D
OUT
ADDRESS
t
OH
t
CLZ
t
CHZ
(5)
D
OUT
CE2
CE1
(5)
t
ACS2
t
ACS1
t
OH
t
RC
t
OE
t
CLZ2
t
CHZ
(2,5)
D
OUT
CE2
CE1
OE
ADDRESS
(5)
t
CLZ1
(5)
t
ACS1
t
ACS2
t
CHZ
(1,5)
t
OHZ
(5)
t
OLZ
t
AA
BS62UV1024
16
2-
Revision 1.0
March 2000
R0201-BS62UV1024
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS62UV1024-15
MIN. TYP. MAX.
UNIT
t
AVAX
t
WC
Write Cycle Time
150
--
--
ns
t
E1LWH
t
CW
Chip Select to End of Write
150
--
--
ns
t
AVWL
t
AS
Address Set up Time
0
--
--
ns
t
AVWH
t
AW
Address Valid to End of Write
150
--
--
ns
t
WLWH
t
WP
Write Pulse Width
80
--
--
ns
t
WHAX
t
WR1
Write Recovery Time
(CE1 , WE)
0
--
--
ns
t
E2LAX
t
WR2
Write Recovery Time
(CE2)
0
--
--
ns
t
WLOZ
t
WHZ
Write to Output in High Z
--
--
40
ns
t
DVWH
t
DW
Data to Write Time Overlap
50
--
--
ns
t
WHDX
t
DH
Data Hold from Write Time
0
--
--
ns
t
GHOZ
t
OHZ
Output Disable to Output in High Z
0
--
40
ns
t
WHQX
t
OW
End of Write to Output Active
5
--
--
ns
!
AC ELECTRICAL CHARACTERISTICS
(over the operating range)
WRITE CYCLE
!
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
(1)
1. Typical characteristics are at Vcc = 2.0V, T
A
= 25
o
C.
BSI
t
WR1
t
WC
(3)
t
CW
(11)
(11)
t
CW
(2)
t
WP
t
AW
t
OHZ
(4,10)
t
AS
t
WR2
(3)
t
DH
t
DW
D
IN
D
OUT
WE
CE2
CE1
OE
ADDRESS
(5)
(5)
BS62UV1024
17
2-
Revision 1.0
March 2000
R0201-BS62UV1024
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
IL
).
7.
D
OUT
is the same phase of write data of this write cycle.
8. D
OUT
is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. T
CW
is measured from the later of CE1 going low or CE2 going high to the end of write.
WRITE CYCLE2
(1,6)
BSI
t
WC
t
CW
(11)
(11)
t
CW
(2)
t
WP
t
AW
t
WHZ
(4,10)
t
AS
t
WR2
(3)
t
DH
t
DW
D
IN
D
OUT
WE
CE2
CE1
ADDRESS
(5)
(5)
t
DH
(7)
(8)
(8)
BS62UV1024
18
2-
Revision 1.0
March 2000
R0201-BS62UV1024
PACKAGE
S: SOP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
!
ORDERING INFORMATION
BSI
BS62UV1024
X X
--
Y
Y
GRADE
C: +0
o
C ~ +70
o
C
I: -40
o
C ~ +85
o
C
SPEED
15: 150ns
!
PACKAGE DIMENSIONS
BS62UV1024
19
2-
Revision 1.0
March 2000
R0201-BS62UV1024
!
PACKAGE DIMENSIONS (continued)
BSI
BS62UV1024
20
2-
Revision 1.0
March 2000
R0201-BS62UV1024
This page is left blank intentionally.
BSI
BS62UV1024
21
2-
POWER DISSIPATION
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
(ns)
Vcc=
5.0V
Vcc=
3.0V
Vcc=
5.0V
Vcc=
3.0V
PKG TYPE
BS62LV1024SC
SOP-32
BS62LV1024TC
TSOP-32
BS62LV1024STC
+0
O
C to +70
O
C
2.4V ~ 5.5V
70
3.0uA
0.5uA
45mA
20mA
STSOP-32
BS62LV1024SI
SOP-32
BS62LV1024TI
TSOP-32
BS62LV1024STI
-40
O
C to +85
O
C
2.4V ~ 5.5V
70
5.0uA
1.5uA
45mA
20mA
STSOP-32
Revision 1.0
March 2000
R0201-BS62LV1024
BSI
Very Low Power/Voltage CMOS SRAM
128K X 8 bit
Wide Vcc operation voltage : 2.4V ~ 5.5V
Very low power consumption :
Vcc = 3.0V 20mA (Max.) write current
1mA (Max.) read current
0.02uA (Typ.) CMOS standby current
Vcc = 5.0V 45mA (Max.) write current
2mA (Max.) read current
0.6uA (Typ.) CMOS standby current
High speed access time :
-70 70ns (Max.)
Input levels are CMOS-compatible
Automatic power down when chip is deselected
Three state outputs
Fully static operation
Data retention supply voltage as low as 1.5V
Easy expansion with CE2, CE1, and OE options
All I/O pins are 5V tolerant
The BS62LV1024 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.02uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV1024 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV1024 is available in the JEDEC standard 32 pin
525mil Plastic SOP, 8mmx13.4mm STSOP, and 8mmx20mm TSOP.
!
DESCRIPTION
!
FEATURES
!
BLOCK DIAGRAM
!
PRODUCT FAMILY
!
PIN CONFIGURATIONS
Brilliance Semiconductor Inc
.
reserves the right to modify document contents without notice.
BS62LV1024
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
BS62LV1024SC
BS62LV1024SI
BS62LV1024TC
BS62LV1024STC
BS62LV1024TI
BS62LV1024STI
A7
Address
Input
Buffer
Row
Decoder
Memory Array
1024 x 1024
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
Address Input Buffer
A3 A2 A1 A0 A10
Data
Buffer
Input
Control
Gnd
Vdd
OE
WE
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A14
A9
A11
A8
A13
A12
A6
8
8
8
8
14
128
1024
1024
20
A16
A15
A4
A5
CE2
22
2-
Revision 1.0
March 2000
R0201-BS62LV1024
BSI
BS62LV1024
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
C
IN
Input
Capacitance
V
IN
=0V
6
pF
C
DQ
Input/Output
Capacitance
V
I/O
=0V
8
pF
!
ABSOLUTE MAXIMUM RATINGS
(1)
!
OPERATING RANGE
!
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not tested.
SYMBOL
PARAMETER
RATING
UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to +6.0
V
T
BIAS
Temperature Under Bias
-40 to +125
O
C
T
STG
Storage Temperature
-60 to +150
O
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
20
mA
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0
O
C to +70
O
C
2.4V ~ 5.5V
Industrial
-40
O
C to +70
O
C
2.4V ~ 5.5V
!
TRUTH TABLE
!
PIN DESCRIPTIONS
Name
Function
A0-A16 Address Input
These 17 address input select one of the 131,072 x 8-bit words in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read
from or write to the device. If either chip enable is not active, the device is deselected
and is in a standby power mode. The DQ pins will be in the high impedance state
when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0 DQ7 Data Input/Output
Ports
These 8 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
MODE
WE
CE1
CE2
OE
I/O OPERATION
Vcc CURRENT
X
H
X
X
Not selected
(Power Down)
X
X
L
X
High Z
I
CCSB
, I
CCSB1
Output Disabled
H
L
H
H
High Z
I
CC
Read
H
L
H
L
D
OUT
I
CC
Write
L
L
H
X
D
IN
I
CC
23
2-
Revision 1.0
March 2000
R0201-BS62LV1024
BSI
BS62LV1024
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
IL
Guaranteed Input Low
Voltage
(2)
-0.5
--
0.3Vcc
V
V
IH
Guaranteed Input High
Voltage
(2)
0.7Vcc
--
Vcc+0.2
V
I
IL
Input Leakage Current
Vcc = Max, V
IN
= 0V to Vcc
--
--
1
uA
I
OL
Output Leakage Current
Vcc = Max, CE1= V
IH
, CE2= V
IL,
or
OE = V
IH
, V
I/O
= 0V to Vcc
--
--
1
uA
V
OL
Output Low Voltage
Vcc = Max, I
OL
= 2mA
--
--
0.4
V
V
OH
Output High Voltage
Vcc = Min, I
OH
= -1mA
2.4
--
--
V
Vcc=3.0V
--
--
20
I
CC
Operating Power Supply
Current
CE1 = V
IL
, or CE2 = V
IH
,
I
DQ
= 0mA, F = Fmax
(3)
Vcc=5.0V
--
--
45
mA
Vcc=3.0V
--
--
1
I
CCSB
Standby Power Supply
Current
CE1 = V
IH
, or CE2 = V
IL
,
I
DQ
= 0mA, F = Fmax
(3)
Vcc=5.0V
--
--
2
mA
Vcc=3.0V
--
0.02
0.5
I
CCSB1
Power Down Supply
Current
CE1
Vcc-0.2V, CE2
0.2V,
V
IN
Vcc-0.2V or V
IN
0.2V
Vcc=5.0V
--
0.6
3
uA
1. Typical characteristics are at TA = 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
RC
.
!
DATA RETENTION CHARACTERISTICS
( TA = 0 to + 70
o
C )
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
!
DC ELECTRICAL CHARACTERISTICS
( TA = 0 to + 70
o
C )
!
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
CE
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.5V
CE Vcc - 0.2V
!
LOW V
CC
DATA RETENTION WAVEFORM (2)
( CE2 Controlled )
CE2
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.5V
CE2 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
DR
Vcc for Data Retention
CE1
Vcc - 0.2V, CE2
0.2V,
VIN
Vcc - 0.2V or VIN
0.2V
1.5
--
--
V
I
CCDR
Data Retention Current
CE1
Vcc - 0.2V, CE2
0.2V,
VIN
Vcc - 0.2V or VIN
0.2V
--
0.02
0.3
uA
t
CDR
Chip Deselect to Data
Retention Time
0
--
--
ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
--
--
ns
24
2-
Revision 1.0
March 2000
R0201-BS62LV1024
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS62LV1024-70
MIN. TYP. MAX.
UNIT
t
AVAX
t
RC
Read Cycle Time
70
--
--
ns
t
AVQV
t
AA
Address Access Time
--
--
70
ns
t
E1LQV
t
ACS1
Chip Select Access Time
(CE1)
--
--
70
ns
t
E2HOV
t
ACS2
Chip Select Access Time
(CE2)
--
--
70
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
--
50
ns
t
E1LQX
t
CLZ1
Chip Select to Output Low Z
(CE1)
10
--
--
ns
t
E2HOX
t
CLZ2
Chip Select to Output Low Z
(CE2)
10
--
--
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
10
--
--
ns
t
E1HQZ
t
CHZ1
Chip Deselect to Output in High Z
(CE1)
0
--
40
ns
t
E2HQZ
t
CHZ1
Chip Deselect to Output in High Z
(CE2)
0
40
t
GHQZ
t
OHZ
Output Disable to Output in High Z
0
--
35
ns
t
AXOX
t
OH
Output Disable to Output Address Change
10
--
--
ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
!
AC ELECTRICAL CHARACTERISTICS
(over the operating range)
READ CYCLE
!
AC TEST CONDITIONS
!
AC TEST LOADS AND WAVEFORMS
!
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
1. Typical characteristics are at Vcc = 3.3V, T
A
= 25
o
C.
BSI
BS62LV1024
667
THEVENIN EQUIVALENT
ALL INPUT PULSES
10%
90%
Vcc
GND
5ns
90%
10%
1.73V
OUTPUT
FIGURE 2
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
1269
1404
5PF
FIGURE 1B
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
1269
100PF
FIGURE 1A
1404
25
2-
Revision 1.0
March 2000
R0201-BS62LV1024
READ CYCLE3
(1,4)
READ CYCLE2
(1,3,4)
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE1 = V
IL
and CE2= V
IH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = V
IL
.
5. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
BSI
!
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
RC
t
OH
t
AA
D
OUT
ADDRESS
t
OH
t
CLZ
t
CHZ
(5)
D
OUT
CE2
CE1
(5)
t
ACS2
t
ACS1
t
OH
t
RC
t
OE
t
CLZ2
t
CHZ
(2,5)
D
OUT
CE2
CE1
OE
ADDRESS
(5)
t
CLZ1
(5)
t
ACS1
t
ACS2
t
CHZ
(1,5)
t
OHZ
(5)
t
OLZ
t
AA
BS62LV1024
26
2-
Revision 1.0
March 2000
R0201-BS62LV1024
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS62LV1024-70
MIN. TYP. MAX.
UNIT
t
AVAX
t
WC
Write Cycle Time
70
--
--
ns
t
E1LWH
t
CW
Chip Select to End of Write
70
--
--
ns
t
AVWL
t
AS
Address Set up Time
0
--
--
ns
t
AVWH
t
AW
Address Valid to End of Write
70
--
--
ns
t
WLWH
t
WP
Write Pulse Width
50
--
--
ns
t
WHAX
t
WR1
Write Recovery Time
(CE1 , WE)
0
--
--
ns
t
E2LAX
t
WR2
Write Recovery Time
(CE2)
0
--
--
ns
t
WLOZ
t
WHZ
Write to Output in High Z
0
--
30
ns
t
DVWH
t
DW
Data to Write Time Overlap
30
--
--
ns
t
WHDX
t
DH
Data Hold from Write Time
0
--
--
ns
t
GHOZ
t
OHZ
Output Disable to Output in High Z
0
--
30
ns
t
WHQX
t
OW
End of Write to Output Active
5
--
--
ns
!
AC ELECTRICAL CHARACTERISTICS
(over the operating range)
WRITE CYCLE
!
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
(1)
1. Typical characteristics are at Vcc = 3.3V, T
A
= 25
o
C.
BSI
t
WR1
t
WC
(3)
t
CW
(11)
(11)
t
CW
(2)
t
WP
t
AW
t
OHZ
(4,10)
t
AS
t
WR2
(3)
t
DH
t
DW
D
IN
D
OUT
WE
CE2
CE1
OE
ADDRESS
(5)
(5)
BS62LV1024
27
2-
Revision 1.0
March 2000
R0201-BS62LV1024
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
IL
).
7.
D
OUT
is the same phase of write data of this write cycle.
8. D
OUT
is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. T
CW
is measured from the later of CE1 going low or CE2 going high to the end of write.
WRITE CYCLE2
(1,6)
BSI
t
WC
t
CW
(11)
(11)
t
CW
(2)
t
WP
t
AW
t
WHZ
(4,10)
t
AS
t
WR2
(3)
t
DH
t
DW
D
IN
D
OUT
WE
CE2
CE1
ADDRESS
(5)
(5)
t
DH
(7)
(8)
(8)
BS62LV1024
28
2-
Revision 1.0
March 2000
R0201-BS62LV1024
PACKAGE
S: SOP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
!
ORDERING INFORMATION
BSI
BS62LV1024
X X
--
Y
Y
GRADE
C: +0
o
C ~ +70
o
C
I: -40
o
C ~ +85
o
C
SPEED
70: 70ns
!
PACKAGE DIMENSIONS
BS62LV1024
29
2-
Revision 1.0
March 2000
R0201-BS62LV1024
BSI
BS62LV1024
!
PACKAGE DIMENSIONS (continued)
30
2-
This page is left blank intentionally.
Revision 1.0
March 2000
R0201-BS62LV1024
BSI
BS62LV1024
PDF 
ZIP