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Электронный компонент: 0100MS

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100MS
EMI SHIELD
FIGURE 1. Cross-Sectional Side View of 100MS.
FIGURE 2. Assembly Diagram.
DESCRIPTION
The 100MS is an epoxy encapsulated electromagnetic/
electrostatic interference (EMI) shield for use with
circuits where sensitivity to EMI is critical. It was
designed to attenuate EMI by converting electromag-
netic field energy into heat that is absorbed by the
shield and by shunting electrostatic fields to common.
The 100MS may be used in applications to either
confine or exclude EMI. Its cavity was designed for
28.45mm
x
28.45mm
x
7.24mm, 20-pin hybrid pack-
ages. The shields in the cover and base plate are in two
separate halves to maintain the electrical isolation
between the adjacent rows of pins of the module it
encloses. Because of the spacing between the shield
halves and epoxy flow holes, the 100MS provides a
partial, but adequate low reluctance path for electro-
magnetic flux. The 100MS is well suited for use with
isolation modules such as the Burr-Brown 3656, 722,
and 724.
ASSEMBLY INSTRUCTIONS
Assemble the base plate to the module by pushing the
pins of the module through the beveled holes in the
base plate until the base plate and bottom of the
module are in contact with each other. Place the cover
over the module so the tabs are aligned and fit into the
slots in the base plate. Bend the four wide shield
soldering tabs protruding from the cover to make
contact with the bare metal on the base plate. Solder
these four tabs to insure the integrity of their connec-
tion to the base plate.
The 100MS and the module it contains are mounted
and secured to a printed circuit board (PCB) by solder-
ing the two narrow PCB solder tabs to the appropriate
common. The PCB solder tab closest to the input side
of the module should be soldered to the input com-
mon. The other tab should be soldered to the output
common. Figure 2 illustrates the assembly of the
100MS.
Base Plate
Module
(reference only)
PCB Solder Tab
Shield Solder Tab
Cover
Shield
Solder Tab
V
ISO
Epoxy Encapsulant
Connection to
Input Common
Connection to
Output Common
V
ISO
= Isolation Voltage
Base Plate Shield
Half Cover Shield
Half Cover Shield
1979 Burr-Brown Corporation
PDS-421A
Printed in U.S.A. October, 1993
SBFS013
2
100MS
100MS
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Isolation Voltage
Rated Continuous, DC
3500
VDC
Rated Continuous, AC
2000
Vrms
Test
10 Seconds
8000
VDC
Capacitance
5
pF
Resistance
10
10
Leakage Current
120V, 60Hz
0.23
A
NOTE: Temperature changes (
T/
t) greater than 1
C per minute below 0
C and long term storage above 100
C are not recommended.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
SPECIFICATIONS
ELECTRICAL
Specifications apply between solder tabs.
APPLICATIONS INFORMATION
MULTIPLE DEVICE ORIENTATION
A typical application for the 100MS is shown in Figure 3.
Using multiple devices within 30mm of each other can
cause them to interact by forming beat frequency interfer-
ence outputs. The 100MS can reduce this interference by as
much as a factor of 200:1 depending on the distance be-
tween the devices and their relative orientation.
Minimum EMI results when the gaps of both shields are
paralleled as in Figure 3a.
PACKAGE INFORMATION
(1)
PACKAGE DRAWING
MODEL
PACKAGE
NUMBER
100MS
EMI Shield
124
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
10 0 M S
G a p i n S h i e l d
10 0 M S
G a p i n S h i e l d
( a ) O p t i m u m P C B L a y o u t .
FIGURE 3a. Optimum PCB Layout. Orientation for mini-
mum EMI.
Power
Supply
Common
G = 100
15
9
19
V
OUT1
2
6
7
3
19.6k
10
2M
20k
Thermocouple #1
20
17
16
12
C
(1)
100k
14
11
2M
+V
CC
Power
Supply
Common
3656
G = 100
15
9
19
V
OUT2
2
6
7
3
19.6k
10
2M
20k
Thermocouple #2
20
17
16
12
C
(1)
100k
14
11
2M
+V
CC
NOTE: (1) C = 0.47F.
3656
C
(1)
C
(1)
13
C
(1)
C
(1)
13
FIGURE 3b. Isolated Data Acquisition Input Circuitry. Orien-
tation for Minimum EMI.
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
0100MS
ACTIVE
PDIP
NSP
20
25
None
Call TI
Level-NA-NA-NA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check
http://www.ti.com/productcontent
for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2004
Addendum-Page 1
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