SBAS306A - NOVEMBER 2004 - REVISED DECEMBER 2004
24 Bit, Wide Bandwidth
Analog to Digital Converter
ADS1271
FEATURES
D
105kSPS Data Rate
D
AC Performance:
51kHz Bandwidth
109dB SNR (High-Resolution Mode)
-105dB THD
D
DC Accuracy:
1.8
V/
C Offset Drift
2ppm/
C Gain Drift
D
Selectable Operating Modes:
High-Speed: 105kSPS Data Rate
High-Resolution: 109dB SNR
Low-Power: 35mW Dissipation
D
Power-Down Control
D
Digital Filter:
Linear Phase Response
Passband Ripple:
0.005dB
Stop Band Attenuation: 100dB
D
Internal Offset Calibration On Command
D
Selectable SPI
t
or Frame Sync Serial Interface
D
Designed for Multichannel Systems:
Daisy-Chainable Serial Interface
Easy Synchronization
D
Simple Pin-Driven Control
D
Specified from -40
C to +105
C
D
Analog Supply: 5V
D
Digital Supply: 1.8V to 3.3V
APPLICATIONS
D
Vibration/Modal Analysis
D
Acoustics
D
Dynamic Strain Gauges
D
Pressure Sensors
D
Test and Measurement
DESCRIPTION
The ADS1271 is a 24-bit, delta-sigma analog-to-digital
converter (ADC) with a data rate up to 105kSPS. It offers
a unique combination of excellent DC accuracy and
outstanding AC performance. The high-order,
chopper-stabilized modulator achieves very low drift with
low in-band noise. The onboard decimation filter
suppresses modulator and signal out-of-band noise. The
ADS1271 provides a usable signal bandwidth up to 90%
of the Nyquist rate with less than 0.005dB of ripple.
Traditionally, industrial delta-sigma ADCs offering good
drift performance use digital filters with large passband
droop. As a result, they have limited signal bandwidth and
are mostly suited for DC measurements. High-resolution
ADCs in audio applications offer larger usable bandwidths,
but the offset and drift specification are significantly
weaker than their industrial counterparts. The ADS1271
combines these converters, allowing high-precision
industrial measurement with excellent DC and AC
specifications ensured over an extended industrial
temperature range.
Three operating modes allow for optimization of speed,
resolution, and power. A selectable SPI or a frame-sync
serial interface provides for convenient interfacing to
microcontrollers or DSPs. All operations, including internal
offset calibration, are controlled directly by pins; there are
no registers to program.
Modulator
Digital
Filter
VREFP VREFN
AVDD
DVDD
DRDY/FSYNC
SCLK
DOUT
DIN
FORMAT
AINP
AINN
Serial
Interface
Control
Logic
DGND
AGND
SYNC/PDWN
MODE
CLK
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Copyright
2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
All trademarks are the property of their respective owners.
ADS1271
SBAS306A - NOVEMBER 2004 - REVISED DECEMBER 2004
www.ti.com
2
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
ADS1271
UNIT
AVDD to AGND
-0.3 to +6.0
V
DVDD to DGND
-0.3 to +3.6
V
AGND to DGND
-0.3 to +0.3
V
Input Current
100, Momentary
mA
Input Current
10, Continuous
mA
Analog Input to AGND
-0.3 to AVDD + 0.3
V
Digital Input or Output to DGND
-0.3 to DVDD + 0.3
V
Maximum Junction Temperature
+150
C
Operating Temperature Range
-40 to +105
C
Storage Temperature Range
-60 to +150
C
Lead Temperature (soldering, 10s)
+300
C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
ORDERING INFORMATION
For the most current package and ordering information,
see the Package Option Addendum located at the end of
this data sheet, or refer to our web site at www.ti.com.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ADS1271
SBAS306A - NOVEMBER 2004 - REVISED DECEMBER 2004
www.ti.com
3
ELECTRICAL CHARACTERISTICS
All specifications at TA = -40
C to +105
C, AVDD = +5V, DVDD = +1.8V, fCLK = 27MHz, and VREF = +2.5V, unless otherwise noted.
ADS1271
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Analog Inputs
Full-scale input voltage (FSR)(1)
VIN = (AINP AINN)
VREF
V
Absolute input voltage
AINP or AINN to AGND
AGND 0.1
AVDD + 0.1
V
Common-mode input voltage
VCM = (AINP + AINN)/2
2.5
V
Differential input
High-Speed mode
16.4
k
Differential input
impedance
High-Resolution mode
16.4
k
impedance
Low-Power mode
32.8
k
DC Performance
Resolution
No missing codes
24
Bits
High-Speed mode
105,469
SPS
Data rate (fDATA)
High-Resolution mode
52,734
SPS
Data rate (fDATA)
Low-Power mode
52,734
SPS
Integral nonlinearity (INL)
Differential input, VCM = 2.5V
0.0006
0.0015
% of FSR(1)
Offset error
High-Speed mode
Without calibration
0.150
1
mV
Offset error
With calibration
On the level of the noise
Offset drift
1.8
V/
_
C
Gain error
0.1
0.5
%
Gain error drift
2
ppm/
C
High-Speed mode
Shorted input
9.0
20
V, rms
Noise
High-Resolution mode
6.5
V, rms
Noise
Low-Power mode
9.0
V, rms
Common-mode rejection
fCM = 60Hz
90
100
dB
Power-supply
AVDD
f = 60Hz
80
dB
Power-supply
rejection
DVDD
f = 60Hz
80
dB
AC Performance
Signal-to-noise ratio
High-Speed mode
99
106
dB
Signal-to-noise ratio
(SNR) (2)
(unweighted)
High-Resolution mode
109
dB
(SNR) (2)
(unweighted)
Low-Power mode
106
dB
Total harmonic distortion
(THD) (3)
VIN = 1kHz, -0.5dBFS
-105
-95
dB
Spurious free dynamic range
-108
dB
Passband ripple
0.005
dB
Passband
0.453 fDATA
Hz
-3dB Bandwidth
0.49 fDATA
Hz
Stop band attenuation
100
dB
High-Speed mode
0.547 fDATA
63.453 fDATA
Hz
Stop band
High-Resolution mode
0.547 fDATA
127.453 fDATA
Hz
Stop band
Low-Power mode
0.547 fDATA
63.453 fDATA
Hz
Group delay
High-Speed and
Low-Power modes
38/fDATA
s
Group delay
High-Resolution mode
39/fDATA
s
Settling time (latency)
High-Speed and
Low-Power modes
Complete settling
76/fDATA
s
Settling time (latency)
High-Resolution mode
Complete settling
78/fDATA
s
(1) FSR = full-scale range = 2VREF.
(2) Minimum SNR is ensured by the limit of the DC noise specification.
(3) THD includes the first nine harmonics of the input signals.
(4) MODE and FORMAT pins excluded.
(5) See the text for more details on SCLK.
ADS1271
SBAS306A - NOVEMBER 2004 - REVISED DECEMBER 2004
www.ti.com
4
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = -40
C to +105
C, AVDD = +5V, DVDD = +1.8V, fCLK = 27MHz, and VREF = +2.5V, unless otherwise noted.
UNITS
ADS1271
PARAMETER
UNITS
MAX
TYP
MIN
TEST CONDITIONS
Voltage Reference Inputs
Reference input Voltage (VREF)
VREF = VREFP VREFN
0.5
2.5
2.65
V
Negative reference input (VREFN)
AGND - 0.1
VREFP - 0.5
V
Positive reference input (VREFP)
VREFN + 0.5
AVDD + 0.1
V
Reference Input
High-Speed mode
4.2
k
Reference Input
impedance
High-Resolution mode
4.2
k
impedance
Low-Power mode
8.4
k
Digital Input/Output
VIH
0.7 DVDD
DVDD
V
VIL
DGND
0.3 DVDD
V
VOH
IOH = 5mA
0.8 DVDD
DVDD
V
VOL
IOL = 5mA
DGND
0.2 DVDD
V
Input leakage(4)
0 < VIN DIGITAL < DVDD
10
A
Master clock rate (fCLK)
1
27
MHz
SPI format
24 fDATA
fCLK
MHz
Serial clock rate
(f
)(5)
High-Speed mode
64 fDATA
64 fDATA
MHz
Serial clock rate
(fSCLK)(5)
Frame-Sync format
High-Resolution mode
128 fDATA
128 fDATA
MHz
SCLK
Frame-Sync format
Low-Power mode
64 fDATA
64 fDATA
MHz
Power Supply
AVDD
4.75
5
5.25
V
DVDD
1.65
3.6
V
High-Speed mode
17
25
mA
High-Resolution mode
17
25
mA
AVDD current
Low-Power mode
6.3
9.5
mA
AVDD current
Power-Down mode
T
105
C
1
70
A
Power-Down mode
T
85
C
1
10
A
High-Speed mode
3.5
6
mA
High-Resolution mode
2.5
5
mA
DVDD current
Low-Power mode
1.8
3.5
mA
DVDD current
Power-Down mode
T
105
C, DVDD = 3.3V
1
70
A
Power-Down mode
T
85
C, DVDD = 3.3V
1
20
A
High-Speed mode
92
136
mW
Power dissipation
High-Resolution mode
90
134
mW
Power dissipation
Low-Power mode
35
54
mW
Temperature Range
Specified
-40
+105
_
C
Operating
-40
+105
_
C
Storage
-60
+150
_
C
(1) FSR = full-scale range = 2VREF.
(2) Minimum SNR is ensured by the limit of the DC noise specification.
(3) THD includes the first nine harmonics of the input signals.
(4) MODE and FORMAT pins excluded.
(5) See the text for more details on SCLK.
ADS1271
SBAS306A - NOVEMBER 2004 - REVISED DECEMBER 2004
www.ti.com
5
PIN ASSIGNMENTS
TSSOP (PW) PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VREFP
VREFN
DGND
DVDD
CLK
SCLK
DRDY/FSYNC
DOUT
AINP
AINN
AGND
AVDD
MODE
FORMAT
SYNC/PDWN
DIN
ADS1271
Terminal Functions
PIN
NAME
NO.
FUNCTION
DESCRIPTION
AINP
1
Analog Input
Positive analog input
AINN
2
Analog Input
Negative analog input
AGND
3
Analog Input
Analog ground
AVDD
4
Analog Input
Analog supply
MODE
5
Digital Input
MODE = 0:
High-Speed mode
MODE
5
Digital Input
MODE = float: High-Resolution mode
MODE = 1:
Low-Power mode
FORMAT
6
Digital Input
FORMAT = 0: SPI
FORMAT = 1: Frame-Sync
SYNC/PDWN
7
Digital Input
Synchronize/Power-down input, active low
DIN
8
Digital Input
Data input for daisy-chain operation
DOUT
9
Digital Output
Data output
DRDY/FSYNC
10
Digital
Input/Output
If FORMAT = 0 (SPI), then pin 10 = DRDY output
If FORMAT = 1 (Frame-Sync), then pin 10 = FSYNC input
SCLK
11
Digital Input
Serial clock for data retrieval
CLK
12
Digital Input
Master clock
DVDD
13
Digital Input
Digital supply
DGND
14
Digital Input
Digital ground
VREFN
15
Analog Input
Negative reference input
VREFP
16
Analog Input
Positive reference input
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