FEATURES

WIDEBAND +12V OPERATION: 220MHz (G = +4)

UNITY-GAIN STABLE: 250MHz (G = +1)

HIGH OUTPUT CURRENT: 500mA

OUTPUT VOLTAGE SWING: 10V

HIGH SLEW RATE: 2000V/

LOW SUPPLY CURRENT: 18mA

FLEXIBLE POWER CONTROL: SO-14 Only

OUTPUT CURRENT LIMIT (

800mA)

APPLICATIONS

POWER LINE MODEM

xDSL LINE DRIVERS

CABLE MODEM DRIVERS

MATCHED I/Q CHANNEL AMPLIFIERS

BROADBAND VIDEO LINE DRIVERS

ARB LINE DRIVERS

HIGH CAP LOAD DRIVER

OPA2674 RELATED PRODUCTS

SINGLES

DUALS

TRIPLES

NOTES

OPA691

OPA2691

OPA3691

Single +12V Capable

THS6042

15V Capable

OPA2677

Single +12V Capable

DESCRIPTION

The OPA2674 provides the high output current and low
distortion required in emerging xDSL and Power Line
Modem driver applications. Operating on a single +12V
supply, the OPA2674 consumes a low 9mA/ch quiescent
current to deliver a very high 500mA output current. This
output current supports even the most demanding ADSL
CPE requirements with > 380mA minimum output current
(+25

C minimum value) with low harmonic distortion.

Differential driver applications deliver < -85dBc distortion
at the peak upstream power levels of full rate ADSL. The
high 200MHz bandwidth also supports the most
demanding VDSL line driver requirements.

Power control features are included in the SO-14 package
version to allow system power to be minimized. Two logic
control lines allow four quiescent power settings. These
include full power, power cutback for short loops, idle state
for no signal transmission but line match maintenance,
and shutdown for power off with a high impedance output.

Specified on

6V supplies (to support +12V operation), the

OPA2674 will also support a single +5V or dual

supply. Video applications will benefit from a very high
output current to drive up to 10 parallel video loads (15

)

with < 0.1%/0.1

dG/dP nonlinearity.

Single-Supply CPE Upstream Driver

82.5

17.4

100

AFE

Output

324

1 /2

O P A 26 74

1 /2

O P A 26 74

+12V

1:1.7

15V

Twisted Pair

17.7V

17.4

+6.0V

OPA2674

SBOS270 - AUGUST 2003

Dual Wideband, High Output Current

Operational Amplifier with Current Limit

www.ti.com

2003, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

OPA2674

SBOS270 - AUGUST 2003

www.ti.com

ORDERING INFORMATION

PRODUCT

PACKAGE-LEAD

PACKAGE

DESIGNATOR(1)

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

OPA2674

SO-8

-40

C to +85

OPA2674ID

Rails, 100

OPA2674IDR

Tape and Reel, 2500

OPA2674

SO-14

-40

C to +85

OPA2674I-14D

OPA2674I

14D

Rails, 58

OPA2674I-14DR

Tape and Reel, 2500

(1) For the most current specification and package information, refer to our web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

Power Supply

6.5VDC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Internal Power Dissipation

See Thermal Analysis

. . . . . . . . . . . . . .

Differential Input Voltage

1.2V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Common-Mode Voltage Range

. . . . . . . . . . . . . . . . . . . .

Storage Temperature Range: D,

14D

-40

C to +125

. . . . . . . . . . .

Lead Temperature (soldering, 10s)

+300

. . . . . . . . . . . . . . . . . . . . .

Junction Temperature (TJ)

+150

. . . . . . . . . . . . . . . . . . . . . . . . . . .

ESD Rating

Human Body Model (HBM)(2)

2000V

. . . . . . . . . . . . . . . . . . . . . .

Charge Device Model (CDM)

1000V

. . . . . . . . . . . . . . . . . . . . . .

Machine Model (MM)

100V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(1) Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.

(2) Pins 2 and 6 on SO-8 package, and pins 1 and 7 on SO-14

package > 500V HBM.

This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe

proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.

PIN CONFIGURATIONS

Top View

SO-8

Top View

SO-14

NC = No Connection

Out B

In B

+In B

OPA2674ID

Out A

In A

+In A

In A

+In A

+In B

In B

Out A

Out B

Power

Control

OPA2674I-14D

OPA2674

SBOS270 - AUGUST 2003

www.ti.com

ELECTRICAL CHARACTERISTICS: V

Boldface limits are tested at +25

At T

= +25

C, A

= A

= 1 (full power: for SO

14 only), G = +4, R

= 402

, and R

= 100

, unless otherwise noted. See Figure 1 for AC performance only.

OPA2674ID, OPA2674I-14D

TYP

MIN/MAX OVER TEMPERATURE

TEST

PARAMETER

TEST CONDITIONS

+25

C(1)

C to

+70

C(2)

-40

C to

+85

C(2)

UNITS

MIN/

MAX

TEST

LEVEL

(3)

AC Performance (see Figure 1)
Small-Signal Bandwidth (VO = 0.5VPP)

G = +1, RF = 511

250

MHz

typ

Small-Signal Bandwidth (VO = 0.5VPP)

G = +2, RF = 475

225

170

165

160

MHz

min

G = +4, RF = 402

220

170

165

160

MHz

min

G = +8, RF = 250

260

200

195

190

MHz

min

Peaking at a Gain of +1

G = +1, RF = 511

0.2

typ

Bandwidth for 0.1dB Gain Flatness

G = +4, VO = 0.5VPP

100

MHz

min

Large-Signal Bandwidth

G = +4, VO = 5VPP

220

160

155

150

MHz

typ

Slew Rate

G = +4, 5V step

2000

1500

1450

1400

min

Rise Time and Fall Time

G = +4, VO = 2V step

1.6

typ

Harmonic Distortion

G = +4, f = 5MHz, VO = 2VPP

2nd-Harmonic

RL = 100

-72

-68

-67

-66

dBc

max

500

-82

-80

-79

-78

dBc

max

3rd-Harmonic

RL = 100

-81

-79

-78

-77

dBc

max

500

-93

-91

-90

-89

dBc

max

Input Voltage Noise

f > 1MHz

2.6

2.9

3.1

nV/

max

Noninverting Input Current Noise

f > 1MHz

pA/

max

Inverting Input Current Noise

f > 1MHz

pA/

max

NTSC Differential Gain

NTSC, G = +2, RL = 150

0.03

typ

NTSC Differential Gain

NTSC, G = +2, RL = 37.5

0.05

typ

NTCS Differential Phase

NTSC, G = +2, RL = 150

0.01

deg

typ

NTCS Differential Phase

NTSC, G = +2, RL = 37.5

0.04

deg

typ

Channel

Channel Crosstalk

f = 5MHz, Input Referred

-92

typ

DC Performance(4)

Open

Loop Transimpedance Gain

VO = 0V, RL = 100

135

min

Input Offset Voltage

VCM = 0V

4.5

5.3

max

Offset Voltage Drift

VCM = 0V

max

Noninverting Input Bias Current

VCM = 0V

max

Noninverting Input Bias Current Drift

VCM = 0V

nA/

max

Inverting Input Bias Current

VCM = 0V

max

Inverting Input Bias Current Drift

VCM = 0V

100

150

nA/

max

Input(4)

Common

Mode Input Range (CMIR)(5)

4.5

4.1

4.0

min

Common

Mode Rejection Ratio (CMRR)

VCM = 0V, Input Referred

min

Noninverting Input Impedance

250

typ

Minimum Inverting Input Resistance

Open

Loop

min

Maximum Inverting Input Resistance

Open

Loop

max

Output(4)

Output Voltage Swing

No Load

5.1

4.9

4.8

4.7

min

Output Voltage Swing

RL = 100

5.0

4.8

4.7

4.5

min

RL = 25

4.8

typ

Current Output

VO = 0

500

380

350

320

min

Short

Circuit Current

VO = 0

800

typ

Closed-Loop Output Impedance

G = +4, f

100kHz

0.01

typ

Output(4) (SO-14 Only)

Current Output at Full Power

A1 = 1, A0 = 1, VO = 0

500

380

350

320

min

Current Output at Power Cutback

A1 = 1, A0 = 0, VO = 0

450

350

320

300

min

Current Output at Idle Power

A1 = 0, A0 = 1, VO = 0

100

min

(1) Junction temperature = ambient for +25

C specifications.

(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23

C at high temperature limit for over temperature

specifications.

(3) Test levels: (A) 100% tested at +25

C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and

simulation. (C) Typical value only for information.

(4) Current is considered positive out of node. VCM is the input common-mode voltage.
(5) Tested < 3dB below minimum CMRR specification at

CMIR limits.

OPA2674

SBOS270 - AUGUST 2003

www.ti.com

ELECTRICAL CHARACTERISTICS: V

6V (continued)

Boldface limits are tested at +25

At T

= +25

C, A

= A

= 1 (full power: for SO

14 only), G = +4, R

= 402

, and R

= 100

, unless otherwise noted. See Figure 1 for AC performance only.

TEST

LEVEL

(3)

OPA2674ID, OPA2674I-14D

TEST

LEVEL

(3)

MIN/MAX OVER TEMPERATURE

TYP

PARAMETER

TEST

LEVEL

(3)

MIN/

MAX

UNITS

-40

C to

+85

C(2)

C to

+70

C(2)

+25

C(1)

+25

TEST CONDITIONS

Power Supply

Specified Operating Voltage

typ

Maximum Operating Voltage

6.3

max

Maximum Quiescent Current

VS =

18.6

18.8

19.2

max

Minimum Quiescent Current

VS =

17.4

16.5

16.0

min

Power-Supply Rejection Ratio (PSRR)

f = 100kHz, Input Referred

min

Power Supply (SO-14 Only)

Maximum Logic 0

A1, A0, +VS = +6V

2.5

2.0

1.8

1.5

max

Minimum Logic 1

A1, A0, +VS = +6V

3.3

3.6

4.0

4.2

min

Logic Input Current

A1 = 0V, A0 = 0V, Each Line

100

105

max

Supply Current at Full Power

A1 = 1, A0 = 1 (logic levels)

18.0

18.6

18.8

19.2

max

Supply Current at Power Cutback

A1 = 1, A0 = 0 (logic levels)

13.3

14.2

14.4

14.8

max

Supply Current at Idle Power

A1 = 0, A0 = 1 (logic levels)

4.0

4.8

5.1

5.3

max

Supply Current at Shutdown

A1 = 0, A0 = 0 (logic levels)

1.0

1.3

1.4

1.5

max

Output Impedance in Idle Power

G = +4, f < 1MHz

0.1

typ

Output Impedance in Shutdown

100

typ

Supply Current Step Time

10% to 90% Change

200

typ

Output Switching Glitch

Inputs at GND

typ

Shutdown Isolation

G = +4, 1MHz, A1 = 0, A0 = 0

typ

Thermal Characteristics

Specification: ID, I-14D

-40 to

+85

Thermal Resistance,

ID SO

Junction

Ambient

125

C/W

typ

I-14D SO-14

100

C/W

typ

(1) Junction temperature = ambient for +25

C specifications.

(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23

C at high temperature limit for over temperature

specifications.

(3) Test levels: (A) 100% tested at +25

C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and

simulation. (C) Typical value only for information.

(4) Current is considered positive out of node. VCM is the input common-mode voltage.
(5) Tested < 3dB below minimum CMRR specification at

CMIR limits.

OPA2674

SBOS270 - AUGUST 2003

www.ti.com

ELECTRICAL CHARACTERISTICS: V

= +5V

Boldface limits are tested at +25

At T

= +25

C, A

= 1, A

= 1 (Full Power: for SO-14 only), G = +4, R

= 453

, and R

= 100

, unless otherwise noted. See Figure 3 for AC

performance only.

OPA2674ID, OPA2674I-14D

TYP

MIN/MAX OVER TEMPERATURE

TEST

PARAMETER

TEST CONDITIONS

+25

C(1)

C to

+70

C(2)

-40

C to

+85

C(2)

UNITS

MIN/

MAX

TEST

LEVEL

(3)

AC Performance (see Figure 3)

Small

Signal Bandwidth (VO = 0.5VPP)

G = +1, RF = 536

220

MHz

typ

Small

Signal Bandwidth (VO = 0.5VPP)

G = +2, RF = 511

175

140

130

120

MHz

min

G = +4, RF = 453

168

130

126

120

MHz

min

G = +8, RF = 332

175

140

130

125

MHz

min

Peaking at a Gain of +1

G = +1, RF = 511

0.6

typ

Bandwidth for 0.1dB Gain Flatness

G = +4, VO = 0.5VPP

MHz

min

Large

Signal Bandwidth

G = +4, VO = 5VPP

190

140

135

130

MHz

typ

Slew Rate

G = +4, 2V Step

900

650

625

600

min

Rise Time and Fall Time

G = +4, VO = 2V Step

typ

Harmonic Distortion

G = +4, f = 5MHz, VO = 2VPP

2nd-Harmonic

RL = 100

-65

-63

-62

-61

dBc

max

500

-72

-70

-69

-68

dBc

max

3rd-Harmonic

RL = 100

-72

-70

-69

-68

dBc

max

500

-74

-71

-70

-69

dBc

max

Input Voltage Noise

f > 1MHz

2.6

2.9

3.1

nV/

max

Noninverting Input Current Noise

f > 1MHz

pA/

max

Inverting Input Current Noise

f > 1MHz

pA/

max

Channel

Channel Crosstalk

f = 5MHz, Input Referred

-92

typ

DC Performance(4)

Open

Loop Transimpedance Gain

VO = 0V, RL = 100

110

min

Input Offset Voltage

VCM = 0V

0.8

3.5

4.0

4.3

max

Offset Voltage Drift

VCM = 0V

max

Noninverting Input Bias Current

VCM = 0V

max

Noninverting Input Bias Current Drift

VCM = 0V

nA/

max

Inverting Input Bias Current

VCM = 0V

max

Inverting Input Bias Current Drift

VCM = 0V

100

150

nA/

max

Input

Most Positive Input Voltage(5)

3.7

3.3

3.2

3.1

min

Most Negative Input Voltage(5)

1.3

1.7

1.8

1.9

min

Common

Mode Rejection Ratio (CMRR)

VCM = 2.5V, Input Referred

min

Noninverting Input Impedance

250

typ

Minimum Inverting Input Resistance

Open

Loop

min

Maximum Inverting Input Resistance

Open

Loop

max

Output

Most Positive Output Voltage

No Load

4.1

3.9

3.8

3.6

min

Most Positive Output Voltage

RL = 100

3.9

3.8

3.7

3.5

min

Most Negative Output Voltage

No Load

0.8

1.0

1.1

1.3

max

Most Negative Output Voltage

RL = 100

1.0

1.1

1.2

1.5

max

Current Output

VO = 0

260

200

180

160

min

Closed

Loop Output Impedance

G = +4, f

100kHz

0.02

typ

Output (SO-14 Only)

Current Output at Full Power

A1 = 1, A0 = 1, VO = 0

260

200

180

160

min

Current Output at Power Cutback

A1 = 1, A0 = 0, VO = 0

200

160

140

120

min

Current Output at Idle Power

A1 = 0, A0 = 1, VO = 0

min

(1) Junction temperature = ambient for +25

C specifications.

(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23

C at high temperature limit for over temperature

specifications.

(3) Test levels: (A) 100% tested at +25

C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and

simulation. (C) Typical value only for information.

(4) Current considered positive out of node. VCM is the input common-mode voltage.

(5) Tested < 3dB below minimum CMRR at min/max input ranges.

OPA2674

SBOS270 - AUGUST 2003

www.ti.com

ELECTRICAL CHARACTERISTICS: V

= +5V(continued)

Boldface limits are tested at +25

At T

= +25

C, A

= 1, A

= 1 (Full Power: for SO-14 only), G = +4, R

= 453

, and R

= 100

, unless otherwise noted. See Figure 3 for AC

performance only.

TEST

LEVEL

(3)

OPA2674ID, OPA2674I-14D

TEST

LEVEL

(3)

MIN/MAX OVER TEMPERATURE

TYP

PARAMETER

TEST

LEVEL

(3)

MIN/

MAX

UNITS

-40

C to

+85

C(2)

C to

+70

C(2)

+25

C(1)

+25

TEST CONDITIONS

Power Supply (Single-Supply Mode)

Specified Operating Voltage

typ

Maximum Operating Voltage

12.6

12.6

max

Maximum Quiescent Current

VS = +5V

13.6

14.8

15.2

15.6

max

Minimum Quiescent Current

VS = +5V

13.6

11.7

11.4

min

Power

Supply Rejection Ratio (PSRR)

f = 100kHz, Input Referred

typ

Power Control (SO-14 Only)

Maximum Logic 0

A1, A0, +VS = +5V

1.5

1.0

0.9

0.8

max

Minimum Logic 1

A1, A0, +VS = +5V

2.4

2.7

3.1

3.3

min

Logic Input Current

A1 = 0V, A0 = 0V, Each Line

max

Supply Current at Full Power

A1 = 1, A0 = 1 (logic levels)

13.8

14.8

15.2

15.6

max

Supply Current at Power Cutback

A1 = 1, A0 = 0 (logic levels)

10.2

10.8

11.1

11.4

max

Supply Current at Idle Power

A1 = 1, A0 = 1 (logic levels)

3.0

3.2

3.5

3.8

max

Supply Current at Shutdown

A1 = 0, A0 = 0 (logic levels)

0.6

0.9

1.0

1.1

max

Output Impedance in Idle Power

G = +4, f = 1MHz

typ

Output Impedance in Shutdown

100

typ

Supply Current Step Time

10% to 90% Change

200

typ

Output Switching Glitch

Inputs at GND

typ

Shutdown Isolation

G = +4, 1MHz, A1 = 0, A0 = 0

typ

Thermal Characteristics

Specification: ID, I-14D

-40 to

+85

Thermal Resistance,

ID SO

Junction

Ambient

125

C/W

typ

I-14D SO

100

C/W

typ

(1) Junction temperature = ambient for +25

C specifications.

(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23

C at high temperature limit for over temperature

specifications.

(3) Test levels: (A) 100% tested at +25

C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and

simulation. (C) Typical value only for information.

(4) Current considered positive out of node. VCM is the input common-mode voltage.

(5) Tested < 3dB below minimum CMRR at min/max input ranges.

OPA2674

SBOS270 - AUGUST 2003

www.ti.com

TYPICAL CHARACTERISTICS: V

At TA = +25

C, G = +4, RF = 402

, and RL = 100

, unless otherwise noted.

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE OVER GAIN

Frequency (MHz)

100

200

300

400

500

r
m

i
z

i
n

(
d

)

= 0.5V

See Figure 1

G = +8, R

= 250

G = +2,

= 475

G = +4, R

= 402

G = +1, R

= 511

INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE OVER GAIN

Frequency (MHz)

100

200

300

400

500

r
m

i
z

i
n

(
d

)

= 0.5V

See Figure 2

G =

1, R

= 475

G =

2, R

= 422

G =

8, R

= 402

G =

4, R

= 402

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE OVER POWER SETTINGS

Frequency (MHz)

100

200

300

400

500

i
n

(
d

)

G = +4

= 0.5V

Power Cutback

Idle Power

Full Power

See Figure 1

INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE OVER POWER SETTINGS

Frequency (MHz)

100

200

300

400

500

i
n

(
d

)

G =

= 0.5V

Power Cutback

Idle Power

Full Power

See Figure 2

NONINVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

Frequency (MHz)

100

200

300

400

500

i
n

(
d

)

G = +4

= 8V

= 10V

= 2V

See Figure 1

INVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

Frequency (MHz)

100

200

300

400

500

i
n

(
d

)

G =

= 8V

= 10V

= 5V

See Figure 2

OPA2674

SBOS270 - AUGUST 2003

www.ti.com

TYPICAL CHARACTERISTICS: V

6V (continued)

At TA = +25

C, G = +4, RF = 402

, and RL = 100

, unless otherwise noted.

NONINVERTING PULSE RESPONSE

Time (5ns/div)

tput

l
t
age

(
1

/
d

i
v

)

l
t
a

(
100

/
d

i
v

)

G = +4

= 100

200mV

Left Scale

Large Signal

Right Scale

Small Signal

See Figure 1

NONINVERTING PULSE RESPONSE

Time (5ns/div)

tput

l
t
age

(
1

/
d

i
v

)

l
t
a

(
100

/
d

i
v

)

G = +4

= 100

200mV

Left Scale

Large Signal

Right Scale

Small Signal

See Figure 1

HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

0.1

100

105

i
c

i
s

t
o

i
o

(
d

)

G = +4
V

= 2V

= 100

Single Channel, See Figure 1

2nd-Harmonic

3rd-Harmonic

HARMONIC DISTORTION vs OUTPUT VOLTAGE

Output Voltage (V

)

0.1

100

i
c

i
s

t
o

i
o

(
d

)

f = 5MHz
R

= 100

2nd-Harmonic

3rd-Harmonic

Single Channel, See Figure 1

HARMONIC DISTORTION vs NONINVERTING GAIN

Gain Magnitude (V/V)

i
c

i
s

t
o

i
o

(
d

)

= 2V

f = 5MHz
R

= 100

2nd-Harmonic

3rd-Harmonic

Single Channel, See Figure 1

HARMONIC DISTORTION vs INVERTING GAIN

Gain Magnitude (

V/V)

i
c

i
s

t
o

i
o

(
d

)

= 2V

f = 5MHz
R

= 100

2nd-Harmonic

3rd-Harmonic

Single Channel, See Figure 2

OPA2674

SBOS270 - AUGUST 2003

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TYPICAL CHARACTERISTICS: V

6V (continued)

At TA = +25

C, G = +4, RF = 402

, and RL = 100

, unless otherwise noted.

HARMONIC DISTORTION vs LOAD RESISTANCE

Load Resistance (

)

100

r
m

i
c

t
o

r
t
i
o

(
d

)

Single Channel, See Figure 1

= 2V

f = 5MHz

2nd-Harmonic

3rd-Harmonic

2-TONE, 3rd-ORDER SPURIOUS LEVEL

Single-Tone Load Power (dBm)

100

r
de

pur

i
o

Lev

(
d

)

20MHz

5MHz

1MHz

Power at Matched 50

Load, See Figure 1

10MHz

dBc = dB Below Carriers

MAXIMUM OUTPUT SWING vs LOAD RESISTANCE

Load Resistance (

)

100

t
p

l
t
a

(
V)

OUTPUT VOLTAGE AND CURRENT LIMITATIONS

(mA)

600

200

400

200

400

600

)

= 10

= 25

= 50

= 100

1 W In terna l P ow er

S ingle C ha nnel

1 W In ternal P ow er

Single Ch ann el

INPUT VOLTAGE AND CURRENT NOISE DENSITY

Frequency (Hz)

100

100k

10k

10M

l
t
age

i
s

(
n

)

r
r
en

(
p

)

Inverting Current N oise

Noninverting Current Noise

Voltage Noise

2.0nV/

16pA/

H z

24pA/

CHANNEL-TO-CHANNEL CROSSTALK

Frequency (Hz)

10M

100M

100

105

110

r
os

t
al

I
nput

fer

r
e

(
d

)

Input Referred

OPA2674

SBOS270 - AUGUST 2003

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TYPICAL CHARACTERISTICS: V

6V (continued)

At TA = +25

C, G = +4, RF = 402

, and RL = 100

, unless otherwise noted.

RECOMMENDED R

vs CAPACITIVE LOAD

Capacitive Load (pF)

100

(

)

FREQUENCY RESPONSE vs CAPACITIVE LOAD

Frequency (Hz)

10M

100M

r
m

i
z

i
n

apac

i
t
i
v

oad

(
d

)

= 10pF

= 22pF

= 100pF

= 47pF

1/2

OPA2674

402

133

(1)

NOTE: (1) 1k

is optional.

CMRR AND PSRR vs FREQUENCY

Frequency (Hz)

10k

100k

10M

100M

r
-
S

ppl

j
ec

t
i
o

(
dB

)

on-

j
e

t
i
o

ati

(
d

)

CMRR

PSRR

+PSRR

OPEN-LOOP TRANSIMPEDANCE GAIN AND PHASE

Frequency (Hz)

10k

100k

10M

100M

120

100

r
ans

i
m

dan

i
n

(
d

)

135

180

225

270

r
a

i
m

(

)

Gain

Phase

CLOSED-LOOP OUTPUT IMPEDANCE

vs FREQUENCY

Frequency (Hz)

100k

10M

100M

100

0.1

0.01

0.001

t
p

(

)

Idle Power

Full Power

Power Cutback

COMPOSITE VIDEO dG/dP

Number of 150

Loads

0.10

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

/
d

(
%

)

G = +2
R

= 475

dP, Negative Video

dP, Positive Video

dG, Positive Video

dG , Negative V ideo

OPA2674

SBOS270 - AUGUST 2003

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TYPICAL CHARACTERISTICS: V

6V (continued)

At TA = +25

C, G = +4, RF = 402

, and RL = 100

, unless otherwise noted.

NONINVERTING OVERDRIVE RECOVERY

Time (25ns/div)

tput

l
t
age

(
V

)

put

l
t
age

(
V

)

G = +4
R

= 100

See Figure 1

Input

Output

INVERTING OVERDRIVE RECOVERY

Time (25ns/div)

tpu

l
t
age

(
V

)

I
nput

l
t
age

(
V

)

Input

Output

G =

= 100

See Figure 2

TYPICAL DC DRIFT OVER TEMPERATURE

Ambient Temperature (

14
12
10

8
6
4
2
0

100

125

Inp

ffs

l
t
ag

(
m

)

I
n

i
a

r
ent

(

Noninverting Bias Current

Input Offset Voltage

Inverting Bias Current

SUPPLY AND OUTPUT CURRENT vs TEMPERATURE

Temperature (

750

700

650

600

550

500

450

400

350

300

250

100

125

tput

r
r
e

(
mA

)

ppl

r
r
e

t
,

t
h

nnel

(
m

)

Sourcing Output Current

Sinking Output Current

Supply Current, Full Power

Supply Current, Power Cutback

Supply Current, Idle Power

COMMON-MODE INPUT VOLTAGE RANGE

AND OUTPUT SWING vs SUPPLY VOLTAGE

Supply Voltage (

l
t
ag

(

Negative Output Swing

Negative Common-Mode Input Voltage

Positive Common-Mode Input Voltage

Positive Output Swing

OPA2674

SBOS270 - AUGUST 2003

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TYPICAL CHARACTERISTICS: V

At TA = +25

C, Differential Gain = +9, RF = 300

, and RL = 70

, unless otherwise noted. See Figure 5 for AC performance only.

DIFFERENTIAL SMALL-SIGNAL

FREQUENCY RESPONSE

Frequency (MHz)

250

100

150

200

300

r
m

l
i
z

i
n

(
d

)

= 70

= 1V

See Figure 5

= +2,

= 442

= +5,

= 383

= +9,

= 300

DIFFERENTIAL LARGE-SIGNAL

FREQUENCY RESPONSE

Frequency (MHz)

250

100

150

200

300

i
n

)

16V

= 70

= +9

See Figure 5

DIFFERENTIAL DISTORTION vs LOAD RESISTANCE

Load Resistance (

)

100

105

110

r
m

i
c

i
s

t
o

r
t
i
on

(
d

)

2nd-Harmonic

3rd-Harmonic

f = 500kHz

G = +9

= 70

= 4V

See Figure 5

DIFFERENTIAL DISTORTION vs FREQUENCY

Frequency (MHz)

0.1

100

110

i
c

i
s

t
o

i
o

(
d

)

2nd-Harmonic

3rd-Harmonic

G = +9

= 70

See Figure 5

DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE

Differential Output Voltage (V

)

0.1

100

110

r
m

i
c

t
o

r
ti

(
d

)

f = 500kHz
G = +9
R

= 70

2nd-Harmonic

3rd-Harmonic

See Figure 5

ADSL MULTITONE POWER RATIO

(Upstream)

Frequency (kHz)

120

140

100

160

100

(
d

)

See Figure 5

OPA2674

SBOS270 - AUGUST 2003

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TYPICAL CHARACTERISTICS: V

= +5V

At TA = +25

C, G = +4, RF = 453

, and RL = 100

, unless otherwise noted.

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Frequency (MHz)

100

200

300

400

500

r
m

i
z

i
n

(
d

)

See Figure 3

G = +1

= 549

G = +2

= 511

G = +4

= 453

G = +8

= 332

INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Frequency (MHz)

100

200

300

400

500

r
m

i
z

i
n

(
d

)

See Figure 4

G =

= 549

G =

= 511

G =

= 453

G =

= 402

NONINVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

Frequency (MHz)

100

200

300

400

500

i
n

(
d

)

= 3V

= 1V

= 2V

G = +4

= 100

to V

See Figure 3

INVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

Frequency (MHz)

100

200

300

400

500

i
n

(
d

)

= 3V

= 1V

= 2V

G =

= 100

to V

See Figure 4

NONINVERTING PULSE RESPONSE

Time (5ns/div)

t
p

l
t
a

(
0.

i
v

)

I
n

l
ta

(
1

/
d

i
v

)

Large Signal

200mV

Small Signal

Left Scale

Right Scale

G = +4
R

= 100

to V

See Figure 3

INVERTING PULSE RESPONSE

Time (5ns/div)

t
p

l
t
a

(
0.

i
v

)

I
n

l
ta

(
1

/
d

i
v

)

Large Signal

200mV

Small Signal

Left Scale

Right Scale

G =

= 100

to V

See Figure 4

OPA2674

SBOS270 - AUGUST 2003

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TYPICAL CHARACTERISTICS: V

= +5V (continued)

At TA = +25

C, G = +4, RF = 453

, and RL = 100

, unless otherwise noted.

HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

0.1

r
m

i
c

t
o

r
t
i
o

(
d

)

= 2V

G = +4
R

= 100

to V

Single Channel, See Figure 3

2nd-Harmonic

3rd-Harmonic

HARMONIC DISTORTION vs OUTPUT VOLTAGE

Output Voltage (V

)

0.1

r
m

oni

i
s

t
o

r
t
i
o

(
d

)

f = 5MHz
R

= 100

to V

Single Channel, See Figure 3

3rd-Harmonic

2nd-Harmonic

HARMONIC DISTORTION vs NONINVERTING GAIN

Gain Magnitude (V/V)

r
m

i
c

t
o

r
ti

(
d

)

2nd-Harmonic

3rd-Harmonic

= 2V

f = 5MHz
R

= 100

to V

Single Channel, See Figure 3

HARMONIC DISTORTION vs INVERTING GAIN

Gain (

V/V)

r
m

i
c

t
o

r
ti

(
d

)

2nd-Harmonic

3rd-Harmonic

= 2V

f = 5MHz
R

= 100

to V

Single Channel, See Figure 4

HARMONIC DISTORTION vs LOAD RESISTANCE

Load Resistance (

)

100

i
c

i
s

t
o

i
o

(
d

)

Single Channel, See Figure 3

= 2V

f = 5MHz

= 100

to V

2nd-Harmonic

3rd-Harmonic

2-TONE, 3rd-ORDER SPURIOUS LEVEL

Single-Tone Load Power (dBm)

-
O

r
der

i
o

(
dB

)

Single Channel. See Figure 3.
Power at matched 50

load.

20MHz

5MHz

1MHz

10MHz

OPA2674

SBOS270 - AUGUST 2003

www.ti.com

TYPICAL CHARACTERISTICS: V

= +5V

At TA = +25

C, Differential Gain = +9, RF = 316

, and RL = 70

, unless otherwise noted.

DIFFERENTIAL PERFORMANCE

TEST CIRCUIT

316

1+2

+5V

DIFFERENTIAL SMALL-SIGNAL

FREQUENCY RESPONSE

Frequency (MHz)

100

150

200

250

300

l
i
z

i
n

)

= +2

= 511

= +5

= 422

= +9

= 316

= 70

DIFFERENTIAL LARGE-SIGNAL

FREQUENCY RESPONSE

Frequency (MHz)

100

150

200

250

300

i
n

(
d

)

= 70

= +9

HARMONIC DISTORTION vs LOAD RESISTANCE

Load Resistance (

)

100

r
m

oni

i
s

t
o

r
t
i
o

(
dB

)

2nd-Harmonic

3rd-Harmonic

= +9

= 70

f = 500kHz

= 4V

DIFFERENTIAL DISTORTION vs FREQUENCY

Frequency (MHz)

0.1

100

r
m

i
c

t
o

r
ti

(
d

)

3rd-Harmonic

2nd-Harmonic

= +9

= 70

HARMONIC DISTORTION vs OUTPUT VOLTAGE

Output Voltage (V

)

100

r
m

i
c

t
o

r
ti

(
d

)

= +9

= 70

f = 500kHz

2nd-Harmonic

3rd-Harmonic

OPA2674

SBOS270 - AUGUST 2003

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APPLICATION INFORMATION

WIDEBAND CURRENT-FEEDBACK OPERATION

The OPA2674 gives the exceptional AC performance of a
wideband current-feedback op amp with a highly linear,
high-power output stage. Requiring only 9mA/ch
quiescent current, the OPA2674 swings to within 1V of
either supply rail and delivers in excess of 380mA at room
temperature. This low output headroom requirement,
along with supply voltage independent biasing, gives
remarkable single (+5V) supply operation. The OPA2674
delivers greater than 150MHz bandwidth driving a 2V

output into 100

on a single +5V supply. Previous boosted

output stage amplifiers typically suffer from very poor
crossover distortion as the output current goes through
zero. The OPA2674 achieves a comparable power gain
with much better linearity. The primary advantage of a
current-feedback op amp over a voltage-feedback op amp
is that AC performance (bandwidth and distortion) is
relatively independent of signal gain. Figure 1 shows the
DC-coupled, gain of +4, dual power-supply circuit
configuration used as the basis of the

6V Electrical and

Typical Characteristics. For test purposes, the input
impedance is set to 50

with a resistor to ground and the

output impedance is set to 50

with a series output

resistor. Voltage swings reported in the electrical
characteristics are taken directly at the input and output
pins whereas load powers (dBm) are defined at a matched
50

load. For the circuit of Figure 1, the total effective load

is 100

|| 535

= 84

1/2

OPA2674

+6V

Load

Source

133

402

6.8

0.1

6.8

0.1

Figure 1. DC-Coupled, G = +4, Bipolar Supply,

Specification and Test Circuit

Figure 2 shows the DC-coupled, bipolar supply circuit
inverting gain configuration used as the basis for the

Electrical and Typical Characteristics. Key design
considerations of the inverting configuration are
developed in the Inverting Amplifier Operation discussion.

1/2

OPA2674

+6V

Load

Source

100

402

100

Power-supply
decoupling
not shown.

Figure 2. DC-Coupled, G = -4, Bipolar Supply,

Specification and Test Circuit

Figure 3 shows the AC coupled, gain of +4, single-supply
circuit configuration used as the basis of the +5V Electrical
and Typical Characteristics. Though not a rail-to-rail
design, the OPA2674 requires minimal input and output
voltage headroom compared to other wideband
current-feedback op amps. It will deliver a 3V

output

swing on a single +5V supply with greater than 100MHz
bandwidth. The key requirement of broadband single-
supply operation is to maintain input and output signal
swings within the usable voltage ranges at both the input
and the output. The circuit of Figure 3 establishes an input
midpoint bias using a simple resistive divider from the +5V
supply (two 806

resistors). The input signal is then

AC-coupled into this midpoint voltage bias. The input
voltage can swing to within 1.3V of either supply pin, giving
a 2.4V

input signal range centered between the supply

pins. The input impedance matching resistor (57.6

) used

for testing is adjusted to give a 50

input match when the

parallel combination of the biasing divider network is
included. The gain resistor (R

) is AC-coupled, giving the

circuit a DC gain of +1

which puts the input DC bias

voltage (2.5V) on the output as well. The feedback resistor
value is adjusted from the bipolar supply condition to
re-optimize for a flat frequency response in +5V, gain of +4,
operation. Again, on a single +5V supply, the output
voltage can swing to within 1V of either supply pin while
delivering more than 200mA output current. A demanding
100

load to a midpoint bias is used in this

characterization circuit. The new output stage used in the
OPA2674 can deliver large bipolar output currents into this
midpoint load with minimal crossover distortion, as shown
by the +5V supply, harmonic distortion plots in the Typical
Characteristics charts.

OPA2674

SBOS270 - AUGUST 2003

www.ti.com

1/2

OPA2674

+5V

806

100

57.6

806

453

150

0.1

6.8

0.1

Figure 3. AC-Coupled, G = +4, Single-Supply,

Specification and Test Circuit

The last configuration used as the basis of the +5V
Electrical and Typical Characteristics is shown in Figure 4.
Design considerations for this inverting, bipolar supply
configuration are covered either in single-supply
configuration (as shown in Figure 3) or in the Inverting
Amplifier Operation discussion.

1/2

OPA2674

+5V

806

100

806

453

88.7

6.8

0.1

113

Figure 4. AC-Coupled, G = -4, Single-Supply,

Specification and Test Circuit

SINGLE-SUPPLY ADSL UPSTREAM DRIVER

Figure 5 shows a single-supply ADSL upstream driver.
The dual OPA2674 is configured as a differential gain
stage to provide signal drive to the primary of the
transformer (here, a step-up transformer with a turns ratio
of 1:1.7). The main advantage of this configuration is the

reduction of even-order harmonic distortion products.
Another important advantage for ADSL is that each
amplifier needs only half of the total output swing required
to drive the load.

82.5

0.1

17.4

100

AFE

Max

Assumed

324

1/2

OP A2674

1/2

OP A2674

+12V

1:1.7

17.7V

= 128mA

17.4

+6V

Line

Figure 5. Single-Supply ADSL Upstream Driver

The analog front-end (AFE) signal is AC-coupled to the
driver and the noninverting input of each amplifier is biased
to the mid-supply voltage (in this case, +6V). Furthermore,
by providing the proper biasing to the amplifier, this
scheme also provides high-pass filtering with a corner
frequency set here at 5kHz. As the upstream signal
bandwidth starts at 26kHz, this high-pass filter does not
generate any problems and has the advantage of filtering
out unwanted lower frequencies.

The input signal is amplified with a gain set by the following
equation:

)

With R

= 324

and R

= 82.5

, the gain for this

differential amplifier is 8.85. This gain boosts the AFE
signal, assumed to be a maximum of 2V

, to a maximum

of 17.7V

Refer to the Setting Resistor Values to Optimize
Bandwidth section for a discussion on which feedback
resistor value to choose.

The two back-termination resistors (17.4

each) added at

each input of the transformer make the impedance of the
modem match the impedance of the phone line, and also
provide a means of detecting the received signal for the
receiver. The value of these resistors (R

) is a function of

the line impedance and the transformer turns ratio (n),
given by the following equation:

LINE

(1)

(2)

OPA2674

SBOS270 - AUGUST 2003

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OPA2674 HDSL2 UPSTREAM DRIVER

Figure 6 shows an HDSL2 implementation of a single-
supply driver.

82.5

0.1

11.5

135

AFE

Max

Assumed

324

1/2

OPA 2674

1/2

OPA 2674

+12V

1:2.4

17.7V

= 185mA

11.5

+6V

Line

Figure 6. HDSL2 Upstream Driver

The two designs differ by the values of the matching
impedance, the load impedance, and the ratio turns of the
transformers. All of these differences are reflected in the
higher peak current and thus, the higher maximum power
dissipation in the output of the driver.

LINE DRIVER HEADROOM MODEL

The first step in a driver design is to compute the
peak-to-peak output voltage from the target specifications.
This is done using the following equations:

log

RMS

(1mW)

With P

power and V

RMS

voltage at the load, and R

load

impedance, this gives:

RMS

(1mW)

CrestFactor

RMS

with V

peak voltage at the load and CF Crest Factor;

LPP

RMS

with V

LPP

: peak-to-peak voltage at the load.

Consolidating Equations 3 through 6 allows the required
peak-to-peak voltage at the load function of the crest
factor, the load impedance, and the power in the load to be
expressed. Thus:

LPP

(1mW)

This V

LPP

is usually computed for a nominal line

impedance and may be taken as a fixed design target.

The next step for the driver is to compute the individual
amplifier output voltage and currents as a function of V

on the line and transformer turns ratio. As the turns ratio
changes, the minimum allowed supply voltage also
changes. The peak current in the amplifier is given by:

1
2

LPP

With V

LPP

defined in Equation 7 and R

defined in

Equation 2. The peak current is computed in Figure 7 by
noting that the total load is 4R

and that the peak current

is half of the peak-to-peak calculated using V

LPP

1:n

Figure 7. Driver Peak Output Model

With the required output voltage and current versus turns
ratio set, an output stage headroom model will allow the
required supply voltage versus turns ratio to be developed.

The headroom model (see Figure 8) can be described with
the following set of equations:

First, as available output voltage for each amplifier:

OPP

)

Or, second, as required single-supply voltage:

OPP

)

The minimum supply voltage for a power and load
requirement is given by Equation 10.

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

OPA2674

SBOS270 - AUGUST 2003

www.ti.com

Figure 8. Line Driver Headroom Model

Table 1 gives V

, V

, R

, and R

for both +12V and +5V

operation of the OPA2674.

Table 1. Line Driver Headroom Model Values

+5V

0.9V

0.8V

+12V

0.9V

TOTAL DRIVER POWER FOR xDSL
APPLICATIONS

The total internal power dissipation for the OPA2674 in an
xDSL line driver application will be the sum of the
quiescent power and the output stage power. The
OPA2674 holds a relatively constant quiescent current
versus supply voltage--giving a power contribution that is
simply the quiescent current times the supply voltage used
(the supply voltage will be greater than the solution given
in Equation 10). The total output stage power may be
computed with reference to Figure 9.

AVG

Figure 9. Output Stage Power Model

The two output stages used to drive the load of Figure 7
can be seen as an H-Bridge in Figure 9. The average
current drawn from the supply into this H-Bridge and load
will be the peak current in the load given by Equation 8
divided by the crest factor (CF) for the xDSL modulation.
This total power from the supply is then reduced by the
power in R

to leave the power dissipated internal to the

drivers in the four output stage transistors. That power is
simply the target line power used in Equation 2 plus the
power lost in the matching elements (R

). In the examples

here, a perfect match is targeted giving the same power in
the matching elements as in the load. The output stage
power is then set by Equation 11.

OUT

The total amplifier power is then:

TOT

)

For the ADSL CPE upstream driver design of Figure 5, the
peak current is 128mA for a signal that requires a crest
factor of 5.33 with a target line power of 13dBm into 100

(20mW). With a typical quiescent current of 18mA and a
nominal supply voltage of +12V, the total internal power
dissipation for the solution of Figure 5 will be:

TOT

18mA(12V)

)

128mA

5.33

(12V)

2(20mW)

464mW

DESIGN-IN TOOLS

DEMONSTRATION BOARDS

Several PC boards are available to assist in the initial
evaluation of circuit performance using the OPA2674 in
the two package styles. These are available, free, as
unpopulated PC boards delivered with descriptive
documentation. Table 2 shows the summary information
for these boards.

Table 2. Demo Board Availability

PRODUCT

PACKAGE

DEMO BOARD

ORDERING

PRODUCT

PACKAGE

DEMO BOARD

NUMBER

ORDERING

NUMBER

OPA2674ID

SO-8

DEM

OPA268XU

SBOU003

OPA2674I-14D

SO-14

DEM

OPA268XN

SBOU002

Go to the TI web site (www.ti.com) to request either of
these boards.

MACROMODELS AND APPLICATIONS
SUPPORT

Computer simulation of circuit performance using SPICE
is often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and
RF amplifier circuits where parasitic capacitance and

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inductance can have a major effect on circuit performance.
A SPICE model for the OPA2674 is available through the
TI web site (www.ti.com). This model does a good job of
predicting small-signal AC and transient performance
under a wide variety of operating conditions, but does not
do as well in predicting the harmonic distortion or dG/dP
characteristics. This model does not attempt to distinguish
between the package types in small-signal AC
performance, nor does it attempt to simulate channel-to-
channel coupling.

OPERATING SUGGESTIONS

SETTING RESISTOR VALUES TO OPTIMIZE
BANDWIDTH

A current-feedback op amp such as the OPA2674 can hold
an almost constant bandwidth over signal gain settings
with the proper adjustment of the external resistor values,
which are shown in the Typical Characteristics; the
small-signal bandwidth decreases only slightly with
increasing gain. These characteristic curves also show
that the feedback resistor is changed for each gain setting.
The resistor values on the inverting side of the circuit for a
current-feedback op amp can be treated as frequency
response compensation elements, whereas the ratios set
the signal gain. Figure 10 shows the small-signal
frequency response analysis circuit for the OPA2674.

(S)

ERR

Figure 10. Current-Feedback Transfer Function

Analysis Circuit

The key elements of this current-feedback op amp model
are:

= buffer gain from the noninverting input to the

inverting input

= buffer output impedance

ERR

= feedback error current signal

Z(s) = frequency dependent open

loop transimpe-

dance gain from I

ERR

to V

NoiseGain

)

The buffer gain is typically very close to 1.00 and is normal-
ly neglected from signal gain considerations. This gain,
however, sets the CMRR for a single op amp differential
amplifier configuration. For a buffer gain of

< 1.0, the

CMRR = -20

log(1 -

)dB.

, the buffer output impedance, is a critical portion of the

bandwidth control equation. The OPA2674 inverting
output impedance is typically 22

A current-feedback op amp senses an error current in the
inverting node (as opposed to a differential input error
voltage for a voltage-feedback op amp) and passes this on
to the output through an internal frequency dependent
transimpedance gain. The Typical Characteristics show
this open-loop transimpedance response, which is
analogous to the open-loop voltage gain curve for a
voltage-feedback op amp. Developing the transfer
function for the circuit of Figure 10 gives Equation 14:

)

Z(s)

+ a

)

Z(s)

This is written in a loop-gain analysis format, where the
errors arising from a non-infinite open-loop gain are shown
in the denominator. If Z(s) were infinite over all frequen-
cies, the denominator of Equation 14 reduces to 1 and the
ideal desired signal gain shown in the numerator is
achieved. The fraction in the denominator of Equation 14
determines the frequency response. Equation 15 shows
this as the loop-gain equation:

Z(s)

)

LoopGain

If 20 log(R

+ NG

) is drawn on top of the open-loop

transimpedance plot, the difference between the two
would be the loop gain at a given frequency. Eventually,
Z(s) rolls off to equal the denominator of Equation 15, at
which point the loop gain has reduced to 1 (and the curves
have intersected). This point of equality is where the
amplifier closed-loop frequency response given by
Equation 14 starts to roll off, and is exactly analogous to
the frequency at which the noise gain equals the open-loop
voltage gain for a voltage-feedback op amp. The
difference here is that the total impedance in the
denominator of Equation 15 may be controlled somewhat
separately from the desired signal gain (or NG). The
OPA2674 is internally compensated to give a maximally
flat frequency response for R

= 402

at NG = 4 on

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supplies. Evaluating the denominator of Equation 15
(which is the feedback transimpedance) gives an optimal
target of 490

. As the signal gain changes, the

contribution of the NG

term in the feedback

transimpedance changes, but the total can be held
constant by adjusting R

. Equation 16 gives an

approximate equation for optimum R

over signal gain:

490

As the desired signal gain increases, this equation
eventually suggests a negative R

. A somewhat subjective

limit to this adjustment can also be set by holding R

to a

minimum value of 20

. Lower values load both the buffer

stage at the input and the output stage if R

gets too

low

actually decreasing the bandwidth. Figure 11 shows

the recommended R

versus NG for both

6V and a single

+5V operation. The values for R

versus gain shown here

are approximately equal to the values used to generate the
Typical Characteristics. They differ in that the optimized
values used in the Typical Characteristics are also
correcting for board parasitic not considered in the
simplified analysis leading to Equation 16. The values
shown in Figure 11 give a good starting point for designs
where bandwidth optimization is desired.

600

500

400

300

200

Noise Gain

eedb

i
s

(

)

+5V

= 20

Figure 11. Feedback Resistor vs Noise Gain

The total impedance going into the inverting input may be
used to adjust the closed-loop signal bandwidth. Inserting
a series resistor between the inverting input and the
summing junction increases the feedback impedance (the
denominator of Equation 15), decreasing the bandwidth.
The internal buffer output impedance for the OPA2674 is
slightly influenced by the source impedance coming from
of the noninverting input terminal. High-source resistors
also have the effect of increasing R

, decreasing the

bandwidth. For those single-supply applications that
develop a midpoint bias at the noninverting input through
high valued resistors, the decoupling capacitor is essential
for power-supply ripple rejection, noninverting input noise
current shunting, and to minimize the high-frequency
value for R

in Figure 10.

INVERTING AMPLIFIER OPERATION

As the OPA2674 is a general-purpose, wideband
current-feedback op amp, most of the familiar op amp
application circuits are available to the designer. Those
dual op amp applications that require considerable
flexibility in the feedback element (for example,
integrators, transimpedance, and some filters) should
consider a unity-gain stable, voltage-feedback amplifier
such as the OPA2822, because the feedback resistor is
the compensation element for a current-feedback op amp.
Wideband inverting operation (and especially summing) is
particularly suited to the OPA2674. Figure 12 shows a
typical inverting configuration where the I/O impedances
and signal gain from Figure 1 are retained in an inverting
circuit configuration.

1 /2

O P A 2 6 7 4

392

97.6

+6V

Load

Power-supply
decoupling not
shown.

Source

102

Figure 12. Inverting Gain of -4 with Impedance

Matching

In the inverting configuration, two key design
considerations must be noted. First, the gain resistor (R

)

becomes part of the signal source input impedance. If
input impedance matching is desired (which is beneficial
whenever the signal is coupled through a cable, twisted
pair, long PC board trace, or other transmission line
conductor), it is normally necessary to add an additional
matching resistor to ground. R

, by itself, normally is not

set to the required input impedance since its value, along
with the desired gain, will determine an R

, which may be

nonoptimal from a frequency response standpoint. The
total input impedance for the source becomes the parallel
combination of R

and R

The second major consideration is that the signal source
impedance becomes part of the noise gain equation and
has a slight effect on the bandwidth through Equation 15.
The values shown in Figure 12 have accounted for this by
slightly decreasing R

(from the optimum values) to

reoptimize the bandwidth for the noise gain of Figure 12
(NG = 3.98). In the example of Figure 12, the R

value

combines in parallel with the external 50

source

impedance, yielding an effective driving impedance of
50

|| 102

= 33.5

. This impedance is added in series

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with R

for calculating the noise gain

which gives

NG = 3.98. This value, and the inverting input impedance
of 22

, are inserted into Equation 16 to get the R

that

appears in Figure 12. Note that the noninverting input in
this bipolar supply inverting application is connected
directly to ground.

It is often suggested that an additional resistor be
connected to ground on the noninverting input to achieve
bias current error cancellation at the output. The input bias
currents for a current-feedback op amp are not generally
matched in either magnitude or polarity. Connecting a
resistor to ground on the noninverting input of the
OPA2674 in the circuit of Figure 12 actually provides
additional gain for that input bias and noise currents, but
does not decrease the output DC error because the input
bias currents are not matched.

OUTPUT CURRENT AND VOLTAGE

The OPA2674 provides output voltage and current
capabilities that are unsurpassed in a low-cost dual
monolithic op amp. Under no-load conditions at 25

C, the

output voltage typically swings closer than 1V to either
supply rail; the tested (+25

C) swing limit is within 1.1V of

either rail. Into a 6

load (the minimum tested load), it

delivers more than

380mA.

The specifications described previously, though familiar in
the industry, consider voltage and current limits separately.
In many applications, it is the voltage times current (or V-I
product) that is more relevant to circuit operation. Refer to
the Output Voltage and Current Limitations plot in the
Typical Characteristics (see page 9). The X and Y axes of
this graph show the zero-voltage output current limit and
the zero-current output voltage limit, respectively. The four
quadrants give a more detailed view of the OPA2674
output drive capabilities, noting that the graph is bounded
by a safe operating area of 1W maximum internal power
dissipation (in this case, for one channel only).
Superimposing resistor load lines onto the plot shows that
the OPA2674 can drive

4V into 10

4.5V into 25

without exceeding the output capabilities or the 1W
dissipation limit. A 100

load line (the standard test circuit

load) shows the full

5.0V output swing capability, as

stated in the Electrical Characteristics tables. The
minimum specified output voltage and current over
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold startup will the output
current and voltage decrease to the numbers shown in the
Electrical Characteristics tables. As the output transistors
deliver power, the junction temperatures increase,
decreasing the V

's (increasing the available output

voltage swing), and increasing the current gains
(increasing the available output current). In steady-state
operation, the available output voltage and current will
always be greater than that shown in the over-temperature

specifications since the output stage junction
temperatures will be higher than the minimum specified
operating ambient.

DRIVING CAPACITIVE LOADS

One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an analog-to-digital (A/D)
converter

including additional external capacitance that

may be recommended to improve the A/D converter
linearity. A high-speed, high open-loop gain amplifier like
the OPA2674 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When
the amplifier open-loop output resistance is considered,
this capacitive load introduces an additional pole in the
signal path that can decrease the phase margin. Several
external solutions to this problem have been suggested.

When the primary considerations are frequency response
flatness, pulse response fidelity, and/or distortion, the
simplest and most effective solution is to isolate the
capacitive load from the feedback loop by inserting a
series isolation resistor between the amplifier output and
the capacitive load. This does not eliminate the pole from
the loop response, but rather shifts it and adds a zero at a
higher frequency. The additional zero acts to cancel the
phase lag from the capacitive load pole, thus increasing
the phase margin and improving stability. The Typical
Characteristics show the Recommended R

vs Capacitive

Load and the resulting frequency response at the load.
Parasitic capacitive loads greater than 2pF can begin to
degrade the performance of the OPA2674. Long PC board
traces, unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded.
Always consider this effect carefully, and add the
recommended series resistor as close as possible to the
OPA2674 output pin (see the Board Layout Guidelines
section).

DISTORTION PERFORMANCE

The OPA2674 provides good distortion performance into
a 100

load on

6V supplies. It also provides exceptional

performance into lighter loads and/or operating on a single
+5V supply. Generally, until the fundamental signal
reaches very high frequency or power levels, the
2nd-harmonic dominates the distortion with a negligible
3rd-harmonic component. Focusing then on the
2nd-harmonic, increasing the load impedance improves
distortion directly. Remember that the total load includes
the feedback network

in the noninverting configuration

(see Figure 1), this is the sum of R

+ R

; in the inverting

configuration, it is R

. Also, providing an additional supply

decoupling capacitor (0.01

F) between the supply pins

(for bipolar operation) improves the 2nd-order distortion
slightly (3dB to 6dB).

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In most op amps, increasing the output voltage swing
directly increases harmonic distortion. The Typical
Characteristics show the 2nd-harmonic increasing at a
little less than the expected 2x rate, whereas the
3rd-harmonic increases at a little less than the expected 3x
rate. Where the test power doubles, the difference
between it and the 2nd-harmonic decreases less than the
expected 6dB, whereas the difference between it and the
3rd-harmonic decreases by less than the expected 12dB.
This factor also shows up in the 2-tone, 3rd-order
intermodulation spurious (IM3) response curves. The
3rd-order spurious levels are extremely low at low-output
power levels. The output stage continues to hold them low
even as the fundamental power reaches very high levels.
As the Typical Characteristics show, the spurious
intermodulation powers do not increase as predicted by a
traditional intercept model. As the fundamental power
level increases, the dynamic range does not decrease
significantly. For two tones centered at 20MHz, with
10dBm/tone into a matched 50

load (i.e., 2V

for each

tone at the load, which requires 8V

for the overall 2-tone

envelope at the output pin), the Typical Characteristics
show 67dBc difference between the test-tone power and
the 3rd-order intermodulation spurious levels. This
exceptional performance improves further when operating
at lower frequencies.

NOISE PERFORMANCE

Wideband current-feedback op amps generally have a
higher output noise than comparable voltage-feedback op
amps. The OPA2674 offers an excellent balance between
voltage and current noise terms to achieve low output
noise. The inverting current noise (24pA/

Hz) is lower than

earlier solutions whereas the input voltage noise
(2.0nV/

Hz) is lower than most unity-gain stable,

wideband voltage-feedback op amps. This low input
voltage noise is achieved at the price of higher
noninverting input current noise (16pA/

Hz). As long as

the AC source impedance from the noninverting node is
less than 100

, this current noise does not contribute

significantly to the total output noise. The op amp input
voltage noise and the two input current noise terms
combine to give low output noise under a wide variety of
operating conditions. Figure 13 shows the op amp noise
analysis model with all noise terms included. In this model,
all noise terms are taken to be noise voltage or current
density terms in either nV/

Hz or pA/

Hz.

The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 17 shows the general form for the
output noise voltage using the terms given in Figure 13.

ENI

)

IBN

)

4kTR

)

IBI

)

4kTRFNG

4kT

1/2

OPA2674

4kT = 1.6E

20J

at 290

kTR

4kTR

Figure 13. Op Amp Noise Analysis Model

Dividing this expression by the noise gain (NG = (1 + R

))

gives the equivalent input referred spot noise voltage at the
noninverting input, as shown in Equation 18.

)

4kTR

)

4kTR

Evaluating these two equations for the OPA2674 circuit
and component values of Figure 1 gives a total output spot
noise voltage of 14.3nV/

Hz and a total equivalent input

spot noise voltage of 3.6nV/

Hz. This total input referred

spot noise voltage is higher than the 2.0nV/

specification for the op amp voltage noise alone. This
reflects the noise added to the output by the inverting
current noise times the feedback resistor. If the feedback
resistor is reduced in high-gain configurations (as
suggested previously), the total input referred voltage
noise given by Equation 18 approaches just the 2.0nV/

of the op amp. For example, going to a gain of +10 using
R

= 298

gives a total input referred noise of 2.3nV/

Hz.

DIFFERENTIAL NOISE PERFORMANCE

As the OPA2674 is used as a differential driver in xDSL
applications, it is important to analyze the noise in such a
configuration. See Figure 14 for the op amp noise model
for the differential configuration.

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Driver

kTR

4kTR

kTR

4kTR

Figure 14. Differential Op Amp Noise Analysis

Model

As a reminder, the differential gain is expressed as:

)

The output noise voltage can be expressed as shown below:

)

4kTR

)

2 i

)

2 4kTR

Dividing this expression by the differential noise gain
G

= (1 + 2R

) gives the equivalent input referred

spot noise voltage at the noninverting input, as shown in
Equation 21.

)

4kTR

)

2 i

)

4kTR

Evaluating this equation for the OPA2674 circuit and
component values of Figure 5 gives a total output spot
noise voltage of 31.0nV/

Hz and a total equivalent input

spot noise voltage of 3.5nV/

Hz.

In order to minimize the noise contributed by I

, it is

recommended to keep the noninverting source impedance
as low as possible.

DC ACCURACY AND OFFSET CONTROL

A current-feedback op amp such as the OPA2674
provides exceptional bandwidth in high gains, giving fast
pulse settling but only moderate DC accuracy. The
Electrical Characteristics show an input offset voltage
comparable to high-speed, voltage-feedback amplifiers;
however, the two input bias currents are somewhat higher
and are unmatched. While bias current cancellation
techniques are very effective with most voltage-feedback
op amps, they do not generally reduce the output DC offset
for wideband current-feedback op amps. Because the two
input bias currents are unrelated in both magnitude and
polarity, matching the input source impedance to reduce
error contribution to the output is ineffective. Evaluating
the configuration of Figure 1, using worst-case +25

input offset voltage and the two input bias currents, gives
a worst-case output offset range equal to:

(NG

IO(MAX)

)

NG)

)

where NG = noninverting signal gain

4.5mV)

(30

(402

18mV

3mV

14mV

35.0mV (max at 25

POWER CONTROL OPERATION (SO-14 ONLY)

The OPA2674I-14D provides a power control feature that
may be used to reduce system power. The four modes of
operation for this power control feature are full-power,
power cutback, idle state, and power shutdown. These
four operating modes are set through two logic lines A0
and A1. Table 3 shows the different modes of operation.

Table 3. Power Control Mode of Operation

MODE OF

OPERATION

Full

Power

Power Cutback

Idle State

Shutdown

The full-power mode is used for normal operating
condition. The power cutback mode brings the quiescent
power to 13.5mA. The idle state mode keeps a low output
impedance but reduces output power and bandwidth. The
shutdown mode has a high output impedance as well as
the lowest quiescent power (1.0mA).

If the A0 and A1 pins are left unconnected, the
OPA2674I-14D operates normally (full-power).

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To change the power mode, the control pins (either A0 or
A1) must be asserted low. This logic control is referenced
to the positive supply, as shown in the simplified circuit of
Figure 15.

46k

60k

1.2V

120k

Control

A0 or A1

Figure 15. Supply Power Control Circuit

The shutdown feature for the OPA2674 is a positive-sup-
ply referenced, current-controlled interface. Open-collec-
tor (or drain) interfaces are most effective, as long as the
controlling logic can sustain the resulting voltage (in open
mode) that appears at the A0 or A1 pins. The A0/A1 pin
voltage is one diode below the positive supply voltage
applied to the OPA2674 if the logic interface is open. For
voltage output logic interfaces, the on/off voltage levels
described in the Electrical Characteristics apply only for
either the +6V used for the

6V specifications or the +5V

for the single-supply specifications. An open-drain
interface is recommended to operate the A1 and A0 pins
using a higher positive supply and/or logic families with
inadequate high-level voltage swings.

THERMAL ANALYSIS

Due to the high output power capability of the OPA2674,
heat-sinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction temperature
sets the maximum allowed internal power dissipation,
described below. In no case should the maximum junction
temperature be allowed to exceed 150

Operating junction temperature (T

) is given by T

+ P

. The total internal power dissipation (P

) is the sum of

quiescent power (P

) and additional power dissipation in

the output stage (P

) to deliver load power. Quiescent

power is the specified no-load supply current times the
total supply voltage across the part. P

depends on the

required output signal and load. Using the example power
calculation for the ADSL CPE line driver concluded in
Equation 13, and a worst-case analysis at +70

C ambient,

the maximum internal junction temperature for the SO-8
package will be:

J MAX

= T

AMBIENT

+ P

MAX

125

C/W

J MAX

= 70

C + ((12V

18.8mA) + 12V

128mA/(5.33)

- 40mW)

125

C/W = 129

This maximum junction temperature is well below the
maximum of 150

C but may exceed system design

targets. Lower junction temperature would be possible
using the SO-14 package and the power cutback feature.
Repeating this calculation for that solution gives:

J MAX

= 70

C + ((12V

14.2mA) + 12V

128mA/(5.33)

- 40mW)

100

C/W = 112

For extremely high internal power applications, where
improved thermal performance is required, consider the
PSO-8 package of the OPA2677--a similar part with no
output stage current limit and a thermal impedance of less
than 50

C/W.

BOARD LAYOUT GUIDELINES

Achieving optimum performance with a high-frequency
amplifier like the OPA2674 requires careful attention to
board layout parasitic and external component types.
Recommendations that optimize performance include:

a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability; on the
noninverting input, it can react with the source impedance
to cause unintentional band limiting. To reduce unwanted
capacitance, a window around the signal I/O pins should
be opened in all of the ground and power planes around
those pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.

b) Minimize the distance (< 0.25

) from the power-supply

pins to high-frequency 0.1

F decoupling capacitors. At the

device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections (on pins 4 and 8 for an SO-8 package) should
always be decoupled with these capacitors. An optional
supply decoupling capacitor across the two power supplies
(for bipolar operation) improves 2nd-harmonic distortion
performance. Larger (2.2

F to 6.8

F) decoupling

capacitors, effective at a lower frequency, should also be
used on the main supply pins. These can be placed
somewhat farther from the device and may be shared
among several devices in the same area of the PC board.

c) Careful selection and placement of external
components preserve the high-frequency performance
of the OPA2674. Resistors should be of a very low
reactance type. Surface-mount resistors work best and
allow a tighter overall layout. Metal film and carbon
composition axially leaded resistors can also provide good
high-frequency performance. Again, keep the leads and
PC board trace length as short as possible. Never use
wire-wound type resistors in a high-frequency application.
Although the output pin and inverting input pin are the most

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sensitive to parasitic capacitance, always position the
feedback and series output resistor, if any, as close as
possible to the output pin. Other network components,
such as noninverting input termination resistors, should
also be placed close to the package. Where double-side
component mounting is allowed, place the feedback
resistor directly under the package on the other side of the
board between the output and inverting input pins. The
frequency response is primarily determined by the
feedback resistor value as described previously.
Increasing the value reduces the bandwidth, whereas
decreasing it gives a more peaked frequency response.
The 402

feedback resistor used in the Typical

Characteristics at a gain of +4 on

6V supplies is a good

starting point for design. Note that a 511

feedback

resistor, rather than a direct short, is recommended for the
unity-gain follower application. A current-feedback op amp
requires a feedback resistor even in the unity-gain follower
configuration to control stability.

d) Connections to other wideband devices on the board
may be made with short direct traces or through onboard
transmission lines. For short connections, consider the
trace and the input to the next device as a lumped
capacitive load. Relatively wide traces (50mils to 100mils)
should be used, preferably with ground and power planes
opened up around them. Estimate the total capacitive load
and set R

from the plot of Recommended R

Capacitive Load (see page 10). Low parasitic capacitive
loads (< 5pF) may not need an R

because the OPA2674

is nominally compensated to operate with a 2pF parasitic
load. If a long trace is required, and the 6dB signal loss
intrinsic to a doubly-terminated transmission line is
acceptable, implement a matched impedance transmis-
sion line using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and stripline layout
techniques). A 50

environment is normally not necessary

onboard. In fact, a higher impedance environment
improves distortion; see the distortion versus load plots.
With a characteristic board trace impedance defined
based on board material and trace dimensions, a matching
series resistor into the trace from the output of the
OPA2674 is used, as well as a terminating shunt resistor
at the input of the destination device. Remember also that
the terminating impedance is the parallel combination of
the shunt resistor and the input impedance of the
destination device.

This total effective impedance should be set to match the
trace impedance. The high output voltage and current
capability of the OPA2674 allows multiple destination

devices to be handled as separate transmission lines,
each with their own series and shunt terminations. If the
6dB attenuation of a doubly-terminated transmission line
is unacceptable, a long trace can be series-terminated at
the source end only. Treat the trace as a capacitive load in
this case, and set the series resistor value as shown in the
plot of R

vs Capacitive Load. However, this does not

preserve signal integrity as well as a doubly-terminated
line. If the input impedance of the destination device is low,
there is some signal attenuation due to the voltage divider
formed by the series output into the terminating
impedance.

e) Socketing a high-speed part like the OPA2674 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an
extremely troublesome parasitic network, which can make
it almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the
OPA2674 onto the board.

INPUT AND ESD PROTECTION

The OPA2674 is built using a high-speed complementary
bipolar process. The internal junction breakdown voltages
are relatively low for these very small geometry devices
and are reflected in the absolute maximum ratings table.
All device pins have limited ESD protection using internal
diodes to the power supplies, as shown in Figure 16.

These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA continuous
current. Where higher currents are possible (for example,
in systems with

15V supply parts driving into the

OPA2674), current-limiting series resistors should be
added into the two inputs. Keep these resistor values as
low as possible, because high values degrade both noise
performance and frequency response.

External

Internal
Circuitry

Figure 16. ESD Steering Diodes

PACKAGING INFORMATION

Orderable Device

Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

MSL Peak Temp

(3)

OPA2674I-14D

ACTIVE

SOIC

None

CU SNPB

Level-3-220C-168 HR

OPA2674I-14DR

ACTIVE

SOIC

2500

None

CU SNPB

Level-3-220C-168 HR

OPA2674ID

ACTIVE

SOIC

100

None

CU SNPB

Level-3-235C-168 HR

OPA2674IDR

ACTIVE

SOIC

2500

None

CU SNPB

Level-3-235C-168 HR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check

http://www.ti.com/productcontent

for the latest availability information and additional

product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com

9-Dec-2004

Addendum-Page 1

IMPORTANT NOTICE

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