1991 Burr-Brown Corporation
PDS-1120D
Printed in U.S.A. October, 1993
OPA671
Wide Bandwidth, Fast Settling
Difet
OPERATIONAL AMPLIFIER
Difet
Burr-Brown Corporation
Trim
5
Trim
1
+In
3
In
2
V
4
V
O
6
V+
7
FEATURES
q
HIGH GAIN-BANDWIDTH: 35MHz
q
LOW INPUT NOISE: 10nV/
Hz
q
HIGH SLEW RATE: 100V/
s
q
FAST SETTLING: 240ns to 0.01%
q
FET INPUT: I
B
= 50pA max
q
HIGH OUTPUT CURRENT: 50mA
q
WIDE SUPPLY RANGE: V
S
=
4.5 to
18V
APPLICATIONS
q
HIGH-SPEED DATA ACQUISITION
q
OPTOELECTRONICS
q
TRANSIMPEDANCE AMPLIFIER
q
LINE DRIVER
q
CCD BUFFER AMPLIFIER
DESCRIPTION
The OPA671 is a FET-input monolithic operational
amplifier featuring wide bandwidth and fast settling
time. Fabricated using Burr-Brown's
Difet
, comple-
mentary bipolar process, it provides an excellent com-
bination of high speed, accuracy, and high output
current.
The OPA671 is versatile, operating from
4.5V to
18V power supplies. It can deliver
10V signals into
a 200
load at slew rates of 100V/
s. OPA671's
Difet
input provides input bias current thousands of times
lower than bipolar-input wideband op amps.
The OPA671 is internally compensated to be unity-gain
stable, allowing use in the widest range of applications.
The OPA671 is available in an 8-pin plastic DIP, rated
for the industrial temperature range.
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111 Twx: 910-952-1111
Internet: http://www.burr-brown.com/ FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
OPA671
2
OPA671
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
OFFSET VOLTAGE
Input Offset Voltage
0.5
5
mV
Average Drift
10
V/
C
Power Supply Rejection
V
S
=
4.5 to
16.5V
72
94
dB
INPUT BIAS CURRENT
(1)
Input Bias Current
V
CM
= 0V
5
50
pA
Input Offset Current
V
CM
= 0V
2
pA
NOISE
Input Voltage Noise
Noise Density, f = 100Hz
24
nV/
Hz
f = 1kHz
15
nV/
Hz
f = 10kHz
12
nV/
Hz
f = 100kHz
10
nV/
Hz
Voltage Noise, BW = 10Hz to 1MHz
60
Vp-p
Input Bias Current Noise
Current Noise Density, f = 10Hz to 1MHz
2
fA/
Hz
INPUT VOLTAGE RANGE
Common-Mode Input Range
12
13
V
Common-Mode Rejection
V
CM
=
10V
74
92
dB
INPUT IMPEDANCE
Differential
10
12
|| 4.5
|| pF
Common-Mode
10
12
|| 6
|| pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain
V
O
=
10V, R
L
= 1k
80
dB
V
O
=
10V, R
L
= 200
74
78
dB
FREQUENCY RESPONSE
Gain-Bandwidth Product
35
MHz
Slew Rate
G = 1, 10V Step
107
V/
s
Settling Time 0.01%
G = 1, 10V Step
240
ns
0.1%
G = 1, 10V Step
150
ns
1%
G = 1, 10V Step
85
ns
Total Harmonic Distortion
G = 1, f = 100kHz
0.0006
%
V
O
= 3V, R
L
= 200
OUTPUT
Voltage Output
R
L
= 200
10.5
11.5
V
Current Output
V
O
=
10V
50
mA
Short Circuit Current
90/+105
mA
Output Resistance, Open-Loop
DC
20
POWER SUPPLY
Specified Operating Voltage
15
V
Operating Voltage Range
4.5
18
V
Quiescent Current
V
S
=
15V
14.8
17
mA
TEMPERATURE RANGE
Specification
25
+85
C
Operating
40
+100
C
Storage
40
+125
C
Thermal Resistance,
JA
Junction to Ambient
100
C/W
NOTE: (1) Tested without warm-up at T
J
= T
A
= 25
C.
SPECIFICATIONS
At T
A
= +25
C, V
S
=
15V, unless otherwise noted.
OPA671AP
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
3
OPA671
PIN CONFIGURATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
An integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published
specifications.
Top View
DIP
NC
V+
V
O
V
OS
Trim
V
OS
Trim
In
+In
V
NC = No Internal Connection
1
2
3
4
8
7
6
5
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage ........................................................................
18V
Input Voltage ............................................................. (V+) +1V to (V) 1V
Operating Temperature ................................................... 40
C to +100
C
Storage Temperature ...................................................... 40
C to +125
C
Output Short-Circuit to Ground ............................................................ 15s
Junction Temperature .................................................................... +150
C
Lead Temperature (soldering, 10s) ................................................ +300
C
PACKAGE
DRAWING
TEMPERATURE
PRODUCT
PACKAGE
NUMBER
(1)
RANGE
OPA671AP
8-Pin Plastic DIP
006
25
C to +85
C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
PACKAGE/ORDERING INFORMATION
4
OPA671
TYPICAL PERFORMANCE CURVES
T
A
= +25
C, V
S
=
15V unless otherwise noted.
OPEN-LOOP GAIN AND PHASE
vs FREQUENCY
Frequency (Hz)
1k
10k
100k
1M
10M
100M
90
70
50
30
0
45
90
135
Gain (dB)
10
Phase ()
10
180
0
20
40
60
80
Phase
Gain
INPUT VOLTAGE NOISE SPECTRAL DENSITY
Frequency (Hz)
1
10
100
1k
1M
10M
1k
100
10
Voltage Noise (nV/ Hz)
0
10k
100k
GAIN-BANDWIDTH PRODUCT AND
SLEW RATE vs TEMPERATURE
Temperature (C)
25
0
25
50
75
100
45
40
115
110
105
100
Gain-Bandwidth Product (MHz)
25
Slew Rate (V/s)
30
35
SR
GBW
POWER SUPPLY REJECTION AND
COMMON-MODE REJECTION vs TEMPERATURE
Temperature (C)
25
0
25
50
75
100
110
100
90
PSR & CMR (dB)
PSR
80
CMR
OPEN-LOOP GAIN vs TEMPERATURE
Temperature (C)
25
0
25
50
75
100
90
80
70
Open-Loop Gain (dB)
60
R
L
= 200
OPEN-LOOP GAIN vs LOAD RESISTANCE
Load Resistance (
)
20
1k
90
70
60
Open-Loop Gain (dB)
50
200
80
100
2k
5
OPA671
TYPICAL PERFORMANCE CURVES
(CONT)
T
A
= +25
C, V
S
=
15V unless otherwise noted.
POWER SUPPLY CURRENT vs TEMPERATURE
Temperature (C)
16.0
15.5
14.5
Power Supply Current (mA)
14.0
15.0
25
0
25
50
75
100
SHORT-CIRCUIT CURRENT
vs TEMPERATURE
Temperature (C)
25
0
25
50
75
100
120
110
90
80
Short-Circuit Current (mA)
I
SC
60
100
70
+
I
SC
INPUT BIAS CURRENT AND INPUT OFFSET CURRENT
vs JUNCTION TEMPERATURE
Junction Temperature (C)
25
0
25
50
100
125
1000
100
10
Input Bias And Offset Current (pA)
0
1
I
B
75
I
OS
TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
Frequency (Hz)
10
100
1k
10k
100k
0.001
THD + N (%)
0.0001
0.0004
G = 1
G = 10
R
L
= 200
Frequency (Hz)
100k
1M
10M
100M
30
20
Max Output Voltage Swing (Vp-p)
10
MAX OUTPUT VOLTAGE SWING vs FREQUENCY
0
6
OPA671
TYPICAL PERFORMANCE CURVES
(CONT)
T
A
= +25
C, V
S
=
15V unless otherwise noted.
G = +1 SMALL SIGNAL RESPONSE
G = +1 LARGE SIGNAL RESPONSE
G = 1 SMALL SIGNAL RESPONSE
G = 1 LARGE SIGNAL RESPONSE
7
OPA671
CIRCUIT LAYOUT
With any high-speed, wide-bandwidth circuitry, careful circuit
layout will ensure best performance. Make short, direct circuit
interconnections and avoid stray wiring capacitance--espe-
cially at the inverting input pin. A component-side ground plane
will help ensure low ground impedance. Do not place the
ground plane under or near the inputs and feedback network.
The power supply connections should be bypassed with good
high-frequency capacitors positioned close to the op amp pins.
In most cases, both a 1
F solid tantalum capacitor and a 0.1
F
ceramic capacitor are required on each supply. The OPA671
can deliver peak load currents up to 100mA. Even if steady-
state load currents are lower, signal transients may demand
large current transients from the power supplies. It is the power
supply bypass capacitors which must supply these current
transients. Larger bypass capacitors such as 4.7
F solid tanta-
lum capacitors may improve dynamic performance in some
applications.
OFFSET ADJUSTMENT
Many applications require no external offset voltage adjust-
ment. Figure 1 shows an optional circuit for trimming the offset
voltage. Do not use this offset voltage adjustment to correct for
offsets produced in other circuitry since this can introduce large
offset voltage temperature drift.
CAPACITIVE LOADS
The OPA671 is internally compensated to be unity-gain stable
with minimal capacitive load. The combination of low closed-
loop gain and capacitive load will decrease the phase margin
and may lead to gain peaking or oscillations. Load capacitance
reacts with the op amp's open-loop output resistance to form an
additional pole in the feedback loop. With wideband op amps,
load capacitance as low as 50pF can introduce enough phase
shift to degrade dynamic performance. Figure 2 shows circuits
which preserve phase margin with capacitive load. Request
Application Bulletin AB-028 for details on various compensa-
tion circuits and analysis techniques.
POWER DISSIPATION
High output current can cause large internal power dissipation
in the OPA671. Copper leadframe construction improves heat
dissipation compared to conventional plastic packages. To
achieve best heat dissipation, solder the device directly to the
circuit board and use wide circuit board traces close to the
device pins. Limit the ambient temperature, load and signal to
47k
V
O
C
L
100pF
C
L
100pF
1000pF
C
C
10pF
47pF
R
C
20
20
250pF
G = 1
V
I
V
O
C
L
G = 1
V
I
1k
1k
C
C
R
C
V
O
C
L
100pF
V
I
1k
1k
R
C
330
100pF
(c)
(b)
(a)
G = 1
See application bulletin AB-028 for
details on circuits for driving capacitive loads.
FIGURE 2. Compensation Circuits for Capacitive Loads.
assure that the maximum junction temperature is not exceeded.
The OPA671 may be operated at reduced power supply voltage
to minimize power dissipation.
OUTPUT CURRENT LIMIT
Output current is limited by internal circuitry to approximately
90mA at 25
C. The short-circuit limit current decreases with
increasing junction temperature as shown in the typical curves.
The current limit will protect the device from inadvertent short-
circuits to ground. The internal power dissipation under this
condition, however, is quite high so short-circuits should be
avoided.
INPUT BIAS CURRENT
The OPA671 is fabricated with Burr-Brown's dielectrically
isolated
Difet
process, giving it extremely low input bias
current. As with other FET-input amplifiers, input bias current
approximately doubles with every 10
C increase in junction
temperature. Input bias current can be minimized by soldering
the device to the circuit board to provided best heat dissipation.
Reduced power supply voltage will also minimize input bias
current by reducing internal power dissipation.
DEMONSTRATION BOARD
The OPA671 may be evaluated using a high frequency PC
board developed for the OPA65x op amp family. This board
may be ordered from your local Burr-Brown distribution as part
# DEM-OPA65xP. It comes partially assembled but does not
include the amplifier. Since this board was intended for
5V
amplifier, verify that any electrolytic capacitors loaded on the
board can support the higher supply voltages possible with the
OPA671.
10k
V
V+
3
4
2
7
1
OPA671
5k
to 50k
Potentiometer
(10k
preferred)
6
5
FIGURE 1. Optional Offset Voltage Trim Circuit.
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