Document Outline
- FEATURES
- APPLICATIONS
- DESCRIPTION
- RELATED PRODUCTS
- ABSOLUTE MAXIMUM RATINGS(1)
- PACKAGE/ORDERING INFORMATION
- PIN CONFIGURATION
- ELECTRICAL CHARACTERISTICS: VS = 5V
- ELECTRICAL CHARACTERISTICS: VS = +5V
- TYPICAL CHARACTERISTICS: VS = 5V
- TYPICAL CHARACTERISTICS: VS = + 5V
- APPLICATIONS INFORMATION
- WIDEBAND VOLTAGE-FEEDBACK OPERATION
- WIDEBAND INVERTING OPERATION
- WIDEBAND SINGLE-SUPPLY OPERATION
- BUFFERING HIGH-PERFORMANCE ADCs
- VIDEO LINE DRIVING
- SINGLE OP AMP DIFFERENTIAL AMPLIFIER
- THREE OP AMP DIFFERENCING
- (Instrumentation Topology)
- DAC TRANSIMPEDANCE AMPLIFIER
- ACTIVE FILTERS
- DESIGN-IN TOOLS
- DEMONSTRATION BOARDS
- MACROMODELS AND APPLICATIONS SUPPORT
- OPERATING SUGGESTIONS
- OPTIMIZING RESISTOR VALUES
- BANDWIDTH vs GAIN
- OUTPUT DRIVE CAPABILITY
- DRIVING CAPACITIVE LOADS
- DISTORTION PERFORMANCE
- NOISE PERFORMANCE
- DC OFFSET CONTROL
- THERMAL ANALYSIS
- BOARD LAYOUT
- INPUT AND ESD PROTECTION
FEATURES
D
HIGH BANDWIDTH (240MHz, G = +2)
D
HIGH OUTPUT CURRENT (
110mA)
D
LOW INPUT NOISE (2.5nV/
Hz)
D
LOW SUPPLY CURRENT (5.6mA)
D
FLEXIBLE SUPPLY VOLTAGE
Dual
2.5V to
6V
Single +5V to +12V
D
EXCELLENT DC ACCURACY
Maximum 25
C Input Offset Voltage =
750
V
Maximum 25
C Input Offset Current =
400nA
APPLICATIONS
D
LOW-COST VIDEO LINE DRIVERS
D
ADC PREAMPLIFIERS
D
ACTIVE FILTERS
D
LOW-NOISE INTEGRATORS
D
PORTABLE TEST EQUIPMENT
D
OPTICAL CHANNEL AMPLIFIERS
D
LOW-POWER, BASEBAND AMPLIFIERS
D
CCD IMAGING CHANNEL AMPLIFIERS
D
OPA650 AND OPA620 UPGRADE
DESCRIPTION
The OPA820 provides a wideband, unity-gain stable,
voltage-feedback amplifier with a very low input noise voltage
and high output current using a low 5.6mA supply current. At
unity-gain, the OPA820 gives > 800MHz bandwidth with < 1dB
peaking. The OPA820 complements this high-speed
operation with excellent DC precision in a low-power device.
A worst-case input offset voltage of
750
V and an offset
current of
400nA give excellent absolute DC precision for
pulse amplifier applications.
Minimal input and output voltage swing headroom allow the
OPA820 to operate on a single +5V supply with > 2V
PP
output
swing. While not a rail-to-rail (RR) output, this swing will
support most emerging analog-to-digital converter (ADC)
input ranges with lower power and noise than typical RR
output op amps.
Exceptionally low dG/dP (0.01%/0.03
) supports low-cost
composite video line driver applications. Existing designs can
use the industry-standard pinout SO-8 package while
emerging high-density portable applications can use the
SOT23-5. Offering the industry's lowest thermal impedance in
a SOT package, along with full specification over both the
commercial and industrial temperature ranges, gives solid
performance over a wide temperature range.
RELATED PRODUCTS
SINGLES
DUALS
TRIPLES
QUADS
FEATURES
OPA354
OPA2354
--
OPA4354
CMOS RR Output
OPA690
OPA2690
OPA3690
--
High Slew Rate
--
OPA2652
--
--
SOT23-8
--
OPA2822
--
--
Low Noise
--
--
--
OPA4820
Quad OPA820
AC-Coupled, 14-Bit ADS850 Interface
OPA820
V
IN
402
402
ADS850
14-Bit
10MSPS
R
S
24.9
2k
2k
2k
2k
0.1
F
0.1
F
IN
IN
(+2V)
REFB
(+1V)
VREF
SEL
REFT
(+3V)
100pF
+5V
-
5V
50
+5V
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
Unity-Gain Stable, Low-Noise, Voltage-Feedback
Operational Amplifier
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
www.ti.com
Copyright
2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
2
ABSOLUTE MAXIMUM RATINGS
(1)
Power Supply
6.5VDC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Power Dissipation
See Thermal Information
. . . . . . . . . . . .
Differential Input Voltage
1.2V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Common-Mode Voltage Range
VS
. . . . . . . . . . . . . . . . . . . .
Storage Temperature Range
-40
C to +125
C
. . . . . . . . . . . . . . . . .
Lead Temperature (soldering, 10s)
+300
C
. . . . . . . . . . . . . . . . . . . .
Junction Temperature (TJ)
+150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD Rating
Human Body Model (HBM)
+3000V
. . . . . . . . . . . . . . . . . . . . . .
Charge Device Model (CDM)
+1000V
. . . . . . . . . . . . . . . . . . . .
Machine Model (MM)
+300V
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
OPA820
SO-8
D
-45
C to +85
C
OPA820
OPA820ID
Rails, 100
OPA820IDR
Tape and Reel, 2500
OPA820
SOT23-5
DBV
-45
C to +85
C
NSO
OPA820IDBVT
Tape and Reel, 250
OPA820IDBVR
Tape and Reel, 3000
(1) For the most current specification and package information, refer to our web site at www.ti.com.
PIN CONFIGURATION
Top View
SO
Top View
SOT
1
2
3
4
8
7
6
5
NC
+V
S
Output
NC
NC
Inverting Input
Noninverting Input
-
V
S
NC = No Connection
1
2
3
5
4
+V
S
Inverting Input
Output
-
V
S
Noninverting Inut
NSO
1
2
3
5
4
Pin Orientation/Package Marking
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
3
ELECTRICAL CHARACTERISTICS: V
S
=
5V
Boldface limits are tested at +25
C.
RF = 402
, RL = 100
, and G = +2, unless otherwise noted.
OPA820ID, IDBV
TYP
MIN/MAX OVER TEMPERATURE
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(1)
0
C to
70
C
(2)
-40
C to
+85
C
(2)
UNITS
MIN/
MAX
TEST
LEVEL
(3)
AC PERFORMANCE
Small-Signal Bandwidth
G = +1, V
O
= 0.1V
PP
, R
F
= 0
800
MHz
typ
C
G = +2, V
O
= 0.1V
PP
240
170
160
155
MHz
min
B
G = +10, V
O
= 0.1V
PP
30
23
21
20
MHz
min
B
Gain-Bandwidth Product
G
20
280
220
204
200
MHz
min
B
Bandwidth for 0.1dB Gain Flatness
G = +2, V
O
= 0.1V
PP
38
MHz
typ
C
Peaking at a Gain of +1
V
O
= 0.1V
PP
, R
F
= 0
0.5
dB
typ
C
Large-Signal Bandwidth
G = +2, V
O
= 2V
PP
85
MHz
typ
C
Slew Rate
G = +2, 2V Step
240
192
186
180
V/
s
min
B
Rise Time and Fall Time
G = +2, V
O
= 0.2V Step
1.5
ns
typ
C
Settling Time to 0.02%
G = +2, V
O
= 2V Step
22
ns
typ
C
to 0.1%
G = +2, V
O
= 2V Step
18
ns
typ
C
Harmonic Distortion
G = +2, f = 1MHz, V
O
= 2V
PP
2nd-Harmonic
R
L
= 200
-85
-81
-80
-79
dBc
max
B
R
L
500
-90
-85
-83
-81
dBc
max
B
3rd-Harmonic
R
L
= 200
-95
-90
-89
-88
dBc
max
B
R
L
500
-110
-105
-102
-100
dBc
max
B
Input Voltage Noise
f > 100kHz
2.5
2.7
2.8
2.9
nV/
Hz
max
B
Input Current Noise
f > 100kHz
1.7
2.6
2.8
3.0
pA/
Hz
max
B
Differential Gain
G = +2, PAL, V
O
= 1.4V
PP
, R
L
= 150
0.01
%
typ
C
Differential Phase
G = +2, PAL, V
O
= 1.4V
PP
, R
L
= 150
0.03
typ
C
DC PERFORMANCE
(4)
Open-Loop Voltage Gain (A
OL
)
V
O
= 0V, Input-Referred
66
62
61
60
dB
min
A
Input Offset Voltage
V
CM
= 0V
0.2
0.75
1.0
1.2
mV
max
A
Average Input Offset Voltage Drift
V
CM
= 0V
4
4
V/
C
max
B
Input Bias Current
V
CM
= 0V
-9
-17
-19
-23
max
A
Average Input Bias Current Drift
V
CM
= 0V
30
50
nA/
C
max
B
Input Offset Current
V
CM
= 0V
100
400
600
700
nA
max
A
Inverting Input Bias Current Drift
V
CM
= 0V
5
5
nA/
C
max
B
INPUT
Common-Mode Input Range (CMIR)
(5)
4.0
3.8
3.7
3.6
V
min
A
Common-Mode Rejection Ratio
V
CM
= 0V, Input-Referred
85
76
75
73
dB
min
A
Input Impedance
Differential Mode
V
CM
= 0V
18
0.8
k
pF
typ
C
Common Mode
V
CM
= 0V
6
1.0
M
pF
typ
C
OUTPUT
Output Voltage Swing
No Load
3.7
3.5
3.45
3.4
V
min
A
R
L
= 100
3.6
3.5
3.45
3.4
V
min
A
Output Current
V
O
= 0
110
90
80
75
mA
min
A
Short-Circuit Output Current
Output Shorted to Ground
125
mA
typ
C
Closed-Loop Output Impedance
G = +2, f
100kHz
0.04
typ
C
POWER SUPPLY
Specified Operating Voltage
5
V
typ
C
Maximum Operating Voltage
6.0
6.0
6.0
v
max
A
Maximum Quiescent Current
V
S
=
5V
5.6
5.75
6.2
6.4
mA
max
A
Minimum Quiescent Current
V
S
=
5V
5.6
5.45
5.0
4.8
mA
min
A
Power-Supply Rejection Ratio (-PSRR)
Input Referred
72
64
63
62
dB
min
A
THERMAL CHARACTERISTICS
Specification: ID, IDBV
-40 to +85
C
typ
C
Thermal Resistance,
q
JA
D
SO-8
Junction-to-Ambient
125
C/W
typ
C
DBV
SOT23-5
Junction-to-Ambient
150
C/W
typ
C
(1)
Junction temperature = ambient for +25
C specifications.
(2)
Junction temperature = ambient at low temperature limits; junction temperature = ambient +9
C at high temperature limit for over temperature.
(3)
Test levels: (A) 100% tested at +25
C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only
for information.
(4)
Current is considered positive out-of-node. V
CM
is the input common-mode voltage.
(5)
Tested < 3dB below minimum specified CMRR at
CMIR limits.
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
4
ELECTRICAL CHARACTERISTICS: V
S
= +5V
Boldface limits are tested at +25
C.
RF = 402
, RL = 100
, and G = +2, unless otherwise noted.
OPA820ID, IDBV
TYP
MIN/MAX OVER TEMPERATURE
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(1)
0
C to
70
C
(2)
-40
C to
+85
C
(2)
UNITS
MIN/
MAX
TEST
LEVEL
(3)
AC PERFORMANCE
Small-Signal Bandwidth
G = +1, V
O
= 0.1V
PP
, R
F
= 0
550
MHz
typ
C
G = +2, V
O
= 0.1V
PP
230
168
155
151
MHz
min
B
G = +10, V
O
= 0.1V
PP
28
21
20
19
MHz
min
B
Gain-Bandwidth Product
G
20
260
200
190
185
MHz
min
B
Peaking at a Gain of 1
V
O
= 0.1V
PP
, R
F
= 0
0.5
dB
typ
C
Large-Signal Bandwidth
G = +2, V
O
= 2V
PP
70
MHz
typ
C
Slew Rate
G = +2, 2V Step
200
145
140
135
V/
s
min
B
Rise Time and Fall Time
G = +2, V
O
= 2V Step
1.7
ns
typ
C
Settling Time to 0.02%
G = +2, V
O
= 2V Step
24
ns
typ
C
to 0.1%
G = +2, V
O
= 2V Step
21
ns
typ
C
Harmonic Distortion
G = +2, f = 1MHz, V
O
= 2V
PP
2nd-Harmonic
R
L
= 200
-80
-76
-75
-74
dBc
max
B
R
L
500
-83
-79
-77
-75
dBc
max
B
3rd-Harmonic
R
L
= 200
-100
-92
-91
-90
dBc
max
B
R
L
500
-98
-95
-93
-92
dBc
max
B
Input Voltage Noise
f > 100kHz
2.5
2.8
2.9
3.0
nV/
Hz
max
B
Input Current Noise
f > 100kHz
1.6
2.5
2.7
2.9
pA/
Hz
max
B
DC PERFORMANCE
(4)
Open-Loop Voltage Gain (A
OL
)
V
O
= 2.5V, R
L
= 100
65
60
59
58
dB
min
A
Input Offset Voltage
V
CM
= 2.5V
0.3
1.1
1.4
1.6
mV
max
A
Average Input Offset Voltage Drift
V
CM
= 2.5V
4
4
V/
C
max
B
Input Bias Current
V
CM
= 2.5V
-8
-16
-18
-22
max
A
Average Input Bias Current Drift
V
CM
= 2.5V
30
50
nA/
C
max
B
Input Offset Current
V
CM
= 2.5V
100
400
600
700
nA
max
A
Inverting Input Bias Current Drift
V
CM
= 2.5V
5
5
nA/
C
max
B
INPUT
Least Positive Input Voltage
0.9
1.1
1.2
1.3
V
min
A
Most Positive Input Voltage
4.5
4.2
4.1
4.0
V
max
A
Common-Mode Rejection Ratio (CMRR)
V
CM
= 2.5V, Input-Referred
83
74
73
72
dB
min
A
Input Impedance
Differential Mode
V
CM
= 2.5V
15
1
k
pF
typ
C
Common Mode
V
CM
= 2.5V
5
1.3
M
pF
typ
C
OUTPUT
Most Positive Output Voltage
No Load
+3.9
+3.8
+3.75
+3.7
V
min
A
R
L
= 100
to 2.5V
+3.8
+3.7
+3.65
+3.6
V
min
A
Least Positive Output Voltage
No Load
+1.2
+1.3
+1.35
+1.4
V
max
A
R
L
= 100
to 2.5V
+1.2
+1.3
+1.35
+1.4
V
max
A
Output Current
V
O
= 2.5V
105
80
70
65
mA
min
A
Short-Circuit Output Current
Output Shorted to Ground
115
mA
typ
C
Closed-Loop Output Impedance
G = +2, f
100kHz
0.04
typ
C
POWER SUPPLY
Specified Operating Voltage
+5
V
typ
C
Maximum Operating Voltage
+12
+12
+12
V
max
A
Maximum Quiescent Current
V
S
= +5V
5.0
5.4
5.5
5.6
mA
max
A
Minimum Quiescent Current
V
S
= +5V
5.0
4.4
4.25
4.1
mA
min
A
Power-Supply Rejection Ratio (+PSRR)
Input-Referred
68
dB
typ
C
THERMAL CHARACTERISTICS
Specification: ID, IDBV
-40 to +85
C
typ
C
Thermal Resistance,
q
JA
D
SO-8
Junction-to-Ambient
125
C/W
typ
C
DBV
SOT23-5
Junction-to-Ambient
150
C/W
typ
C
(1)
Junction temperature = ambient for +25
C specifications.
(2)
Junction temperature = ambient at low temperature limits; junction temperature = ambient +7
C at high temperature limit for over temperature.
(3)
Test levels: (A) 100% tested at +25
C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only
for information.
(4)
Current is considered positive out-of-node. V
CM
is the input common-mode voltage.
(5)
Tested < 3dB below minimum specified CMRR at
CMIR limits.
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
5
TYPICAL CHARACTERISTICS: V
S
=
5V
RF = 402
, RL = 100
, and G = +2, unless otherwise noted.
3
0
-
3
-
6
-
9
-
12
-
15
-
18
NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE
Frequency (Hz)
N
o
r
m
a
liz
e
d
G
a
in
(
d
B
)
1M
10M
100M
1G
G = +1
R
F
= 0
V
O
= 0.1V
PP
R
L
= 100
See Figure 1
G = +10
G = +2
G = +5
9
6
3
0
-
3
-
6
-
9
-
12
NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE
Frequency (MHz)
Ga
i
n
(d
B
)
1
10
100
500
V
O
= 0.5V
PP
V
O
= 1V
PP
V
O
= 2V
PP
V
O
= 4V
PP
G = +2
R
L
= 100
See Figure 1
0.4
0.3
0.2
0.1
0
-
0.1
-
0.2
-
0.3
-
0.4
NONINVERTING PULSE RESPONSE
Time (10ns/div)
S
m
al
l
-
S
i
gna
l
O
utp
u
t
V
ol
ta
ge
(
100m
V
/
di
v
)
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
La
r
g
e-
S
i
gn
al
O
u
tpu
t
V
o
l
t
ag
e
(
5
0
0
m
V
/d
i
v
)
Large Signal
1V
Right Scale
Small Signal
100mV
Left Scale
G = +2
See Figure 1
3
0
-
3
-
6
-
9
-
12
-
15
-
18
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
Frequency (MHz)
N
o
r
m
a
liz
e
d
G
a
in
(
d
B
)
1
10
100
500
G =
-
1
G =
-
2
G =
-
5
G =
-
10
V
O
= 0.1V
PP
R
L
= 100
See Figure 2
3
0
-
3
-
6
-
9
-
12
-
15
-
18
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
Frequency (MHz)
Ga
i
n
(d
B
)
1
10
100
500
V
O
= 0.5V
PP
V
O
= 1V
PP
V
O
= 2V
PP
V
O
= 4V
PP
G =
-
1
R
L
= 100
See Figure 2
0.4
0.3
0.2
0.1
0
-
0.1
-
0.2
-
0.3
-
0.4
INVERTING PULSE RESPONSE
Time (10ns/div)
S
m
al
l
-
S
i
gna
l
O
utp
u
t
V
ol
ta
ge
(
100m
V
/
di
v
)
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
La
r
g
e-
S
i
gn
al
O
u
tpu
t
V
o
l
t
ag
e
(
5
0
0
m
V
/d
i
v
)
Large Signal
1V
Right Scale
Small Signal
100mV
Left Scale
G =
-
1
See Figure 2
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
6
TYPICAL CHARACTERISTICS: V
S
=
5V (continued)
RF = 402
, RL = 100
, and G = +2, unless otherwise noted.
-
70
-
75
-
80
-
85
-
90
-
95
-
100
HARMONIC DISTORTION vs LOAD RESISTANCE
Resistance (
)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c)
100
1k
2nd-Harmonic
3rd-Harmonic
f = 1MHz
V
O
= 2V
PP
G = +2V/V
See Figure 1
-
60
-
65
-
70
-
75
-
80
-
85
-
90
-
95
-
100
-
105
HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c)
0.1
1
10
2nd-Harmonic
3rd-Harmonic
See Figure 1
V
O
= 2V
PP
R
L
= 100
G = +2V/V
-
70
-
75
-
80
-
85
-
90
-
95
-
100
-
105
-
110
HARMONIC DISTORTION vs NONINVERTING GAIN
Gain (V/V)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c)
1
10
2nd-Harmonic
3rd-Harmonic
See Figure 1
f = 1MHz
R
L
= 200
V
O
= 2V
PP
-
75
-
80
-
85
-
90
-
95
-
100
-
105
1MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE
Supply Voltage (
V
S
)
Ha
r
m
o
n
i
c
Di
s
t
o
r
t
i
o
n
(
d
B
c
)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
V
O
= 2V
PP
R
L
= 200
G = +2V/V
See Figure 1
2nd-Harmonic
3rd-Harmonic
-
75
-
80
-
85
-
90
-
95
-
100
-
105
-
110
HARMONIC DISTORTION vs OUTPUT VOLTAGE
Output Voltage (V
PP
)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c)
0.1
1
10
2nd-Harmonic
3rd-Harmonic
f = 1MHz
R
L
= 200
G = +2V/V
See Figure 1
-
70
-
75
-
80
-
85
-
90
-
95
-
100
HARMONIC DISTORTION vs INVERTING GAIN
Gain (
|
V/V
|
)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c)
1
10
2nd-Harmonic
3rd-Harmonic
f = 1MHz
R
L
= 200
V
O
= 2V
PP
See Figure 2
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
7
TYPICAL CHARACTERISTICS: V
S
=
5V (continued)
RF = 402
, RL = 100
, and G = +2, unless otherwise noted.
100
10
1
INPUT VOLTAGE AND CURRENT NOISE
Frequency (Hz)
10
100
1k
10k
100k
1M
10M
V
o
l
t
ag
e
N
oi
s
e
(
n
V
/
Hz
)
C
u
r
r
ent
N
o
i
s
e
(
pA
/
Hz
)
Voltage Noise (2.5nV/
Hz)
Current Noise (1.7pA/
Hz)
100
10
1
RECOMMENDED R
S
vs CAPACITIVE LOAD
Capacitive Load (pF)
1
10
100
1000
R
S
(
)
0dB Peaking Targeted
90
80
70
60
50
40
30
20
10
0
CMRR AND PSRR vs FREQUENCY
Frequency (Hz)
Co
m
m
o
n
-
M
o
d
e
Re
j
e
c
t
i
o
n
R
a
t
i
o
(
d
B
)
Po
w
e
r
-
S
u
p
p
ly
R
e
je
ct
io
n
R
a
t
i
o
(
d
B)
1k
10k
100k
1M
10M
100M
CMRR
+PSRR
-
PSRR
50
45
40
35
30
25
20
15
TWO-TONE, 3RD-ORDER
INTERMODULATION INTERCEPT
Frequency (MHz)
Int
e
r
c
ept
P
o
i
n
t
(
+
d
B
m
)
0
5
10
15
20
25
30
40 2
O P A 82 0
P
I
P
O
5 0
2 00
40 2
8
7
6
5
4
3
2
1
0
-
1
-
2
-
3
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Frequency (MHz)
N
o
r
m
a
l
i
z
ed
G
a
i
n
to
C
a
pa
c
i
t
i
v
e
Lo
a
d
(
d
B
)
1
10
100
400
C
L
= 10pF
C
L
= 22pF
C
L
= 47pF
C
L
= 100pF
4 02
R
S
OPA 820
V
I
V
O
50
1k
(1)
C
L
402
NOTE: (1) 1k
is o ptional.
80
70
60
50
40
30
20
10
0
-
10
OPEN-LOOP GAIN AND PHASE
Frequency (Hz)
Op
e
n
-
L
o
o
p
Ga
i
n
(d
B
)
0
-
20
-
40
-
60
-
80
-
100
-
120
-
140
-
160
-
180
O
p
en-
Loo
p
P
h
a
s
e
(
_
)
100
1k
10k
100k
1M
10M
100M
1G
20 log (A
OL
)
A
OL
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
8
TYPICAL CHARACTERISTICS: V
S
=
5V (continued)
RF = 402
, RL = 100
, and G = +2, unless otherwise noted.
5
4
3
2
1
0
-
1
-
2
-
3
-
4
-
5
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
I
O
(mA)
V
O
(V
)
-
150
-
100
-
50
0
50
100
150
R
L
= 100
R
L
= 25
R
L
= 50
1W Internal
Power Limit
Output Current
Limit
Output Current
Limit
1W Internal
Power Limit
8
6
4
2
0
-
2
-
4
-
6
-
8
NONINVERTING OVERDRIVE RECOVERY
Time (40ns/div)
O
u
t
put
V
o
l
t
ag
e
(
2
V
/di
v
)
4
3
2
1
0
-
1
-
2
-
3
-
4
Inpu
t
V
ol
tage
(
1
V
/
di
v
)
Input Right Scale
Output Left Scale
R
L
= 100
G = +2V/V
See Figure 1
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
COMPOSITE VIDEO dG/dP
Video Loads
D
i
ffe
r
e
n
t
i
a
l
G
ai
n
(
%
)
0.40
0.36
0.32
0.28
0.24
0.20
0.16
0.12
0.08
0.04
0
Di
ffe
r
e
n
t
i
a
l
P
ha
s
e
(
_
)
1
2
3
4
dG Negative Video
dG Positive Video
dP Negative Video
dP Positive Video
G = +2V/V
10
1
0.1
0.01
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
Frequency (Hz)
1k
10k
100k
1M
10M
100M
O
u
t
p
u
t
I
m
pedan
c
e
(
)
5
4
3
2
1
0
-
1
-
2
-
3
-
4
-
5
INVERTING OVERDRIVE RECOVERY
Time (40ns/div)
O
u
tp
ut
V
o
l
t
ag
e
(
1V
/di
v
)
5
4
3
2
1
0
-
1
-
2
-
3
-
4
-
5
In
put
V
o
l
t
age
(
1
V
/
d
i
v
)
Input
Right Scale
Output
Left Scale
R
L
= 100
G =
-
1V/V
See Figure 2
1.0
0.5
0
-
0.5
-
1.0
TYPICAL DC DRIFT OVER TEMPERATURE
Ambient Temperature (
_
C)
In
put
O
f
fs
e
t
V
o
l
t
ag
e
(
m
V
)
20
10
0
-
10
-
20
In
put
B
i
as
a
n
d
O
ff
s
e
t
C
u
r
r
e
nt
(
V)
-
50
-
25
0
25
50
75
100
125
10x Input Offset Current (I
OS
) Right Scale
Input Offset Voltage (V
OS
)
Left Scale
Input Bias Current (I
B
)
Right Scale
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
9
TYPICAL CHARACTERISTICS: V
S
=
5V (continued)
RF = 402
, RL = 100
, and G = +2, unless otherwise noted.
125
100
75
50
25
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
Ambient Temperature (
_
C)
O
u
t
p
u
t
C
u
rr
e
n
t
(m
A
)
12
9
6
3
0
S
u
p
p
l
y
C
u
r
r
ent
(
m
A
)
-
50
-
25
0
25
50
75
100
125
Supply Current
Right Scale
Sink/Source Output Current
Left Scale
10M
1M
100k
10k
1k
COMMON-MODE AND DIFFERENTIAL
INPUT IMPEDANCE
Frequency (Hz)
In
put
I
m
ped
a
n
c
e
(
)
100
1k
10k
100k
1M
10M
100M
Common-Mode Input Impedance
Differential Input Impedance
6
5
4
3
2
1
0
COMMON-MODE INPUT RANGE AND OUTPUT SWING
vs SUPPLY VOLTAGE
Supply Voltage (
V
S
)
V
o
l
t
ag
e
R
ang
e
(
V
)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
+V
IN
-
V
IN
+V
OUT
-
V
OUT
2500
2000
1500
1000
500
0
TYPICAL INPUT OFFSET VOLTAGE DISTRIBUTION
Input Offset Voltage (
V)
Co
u
n
t
-
73
0
-
66
0
-
58
0
-
51
0
-
44
0
-
37
0
-
29
0
-
22
0
-
15
0
-
70
0
70
150
220
290
370
440
510
580
660
730
Mean =
-
30
V
Standard Deviation = 80
V
Total Count = 6115
2000
1800
1600
1400
1200
1000
800
600
400
200
0
TYPICAL INPUT OFFSET CURRENT DISTRIBUTION
Input Offset Current (nA)
Co
u
n
t
-
380
-
342
-
304
-
266
-
228
-
190
-
152
-
114
-
76
-
38
0
38
76
11
4
15
2
19
0
22
8
26
6
30
4
34
2
38
0
Mean = 26nA
Standard Deviation = 57nA
Total Count = 6115
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
10
TYPICAL CHARACTERISTICS: V
S
= +5V
RF = 402
, RL = 100
, and G = +2, unless otherwise noted.
3
0
-
3
-
6
-
9
-
12
-
15
-
18
NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE
Frequency (Hz)
N
o
r
m
a
liz
e
d
G
a
in
(
d
B
)
1M
10M
100M
1G
G = +1
V
O
= 0.1V
PP
R
L
= 100
See Figure 3
G = +10
G = +2
G = +5
9
6
3
0
-
3
-
6
-
9
-
12
NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE
Frequency (MHz)
N
o
r
m
a
liz
e
d
G
a
in
(
d
B
)
1
10
100
600
V
O
= 0.5V
PP
V
O
= 1V
PP
V
O
= 2V
PP
V
O
= 4V
PP
G = +2V/V
R
L
= 100
See Figure 3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
NONINVERTING PULSE RESPONSE
Time (10ns/div)
S
m
al
l
-
S
i
g
nal
O
u
t
put
V
o
l
t
a
g
e
(
10
0mV
/
d
i
v
)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
La
r
g
e
-
S
i
g
n
a
l
O
u
t
p
ut
V
o
l
t
a
g
e
(
50
0mV
/
di
v
)
Large Signal
1V
Right Scale
Small Signal
100mV
Left Scale
G = +2
See Figure 3
3
0
-
3
-
6
-
9
-
12
-
15
-
18
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
Frequency (MHz)
N
o
r
m
a
liz
e
d
G
a
in
(
d
B
)
1
10
100
500
G =
-
1
G =
-
2
G =
-
5
G =
-
10
V
O
= 0.1V
PP
R
L
= 100
See Figure 4
3
0
-
3
-
6
-
9
-
12
-
15
-
18
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
Frequency (MHz)
Ga
i
n
(d
B
)
1
10
100
500
V
O
= 0.5V
PP
V
O
= 1V
PP
V
O
= 2V
PP
V
O
= 4V
PP
G =
-
1
R
L
= 100
See Figure 4
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
INVERTING PULSE RESPONSE
Time (10ns/div)
S
m
al
l
-
S
i
g
nal
O
u
t
put
V
o
l
t
a
g
e
(
10
0mV
/
d
i
v
)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
La
r
g
e
-
S
i
g
n
a
l
O
u
t
p
ut
V
o
l
t
a
g
e
(
50
0mV
/
di
v
)
Large Signal
1V
Right Scale
Small Signal
100mV
Left Scale
G =
-
1
See Figure 4
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
11
TYPICAL CHARACTERISTICS: V
S
= +5V (continued)
RF = 402
, RL = 100
, and G = +2, unless otherwise noted.
-
75
-
80
-
85
-
90
-
95
-
100
-
105
HARMONIC DISTORTION vs LOAD RESISTANCE
Resistance (
)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c)
100
1k
2nd-Harmonic
3rd-Harmonic
f = 1MHz
V
O
= 2V
PP
G = +2V/V
See Figure 3
-
70
-
80
-
90
-
100
-
110
HARMONIC DISTORTION vs OUTPUT VOLTAGE
Output Voltage Swing (V
PP
)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c)
0.1
1
10
2nd-Harmonic
3rd-Harmonic
V
O
= 2V
PP
f = 1MHz
G = +2V/V
R
L
= 200
See Figure 3
-
70
-
75
-
80
-
85
-
90
-
95
-
100
HARMONIC DISTORTION vs INVERTING GAIN
Gain (
|
V/V
|
)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c)
1
10
2nd-Harmonic
3rd-Harmonic
f = 1MHz
R
L
= 200
V
O
= 2V
PP
See Figure 4
-
60
-
70
-
80
-
90
-
100
-
110
HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c)
0.1
1
10
2nd-Harmonic
3rd-Harmonic
G = +2V/V
R
L
= 200
V
O
= 2V
PP
See Figure 3
-
60
-
70
-
80
-
90
-
100
-
110
HARMONIC DISTORTION vs NONINVERTING GAIN
Gain (V/V)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c)
1
10
2nd-Harmonic
3rd-Harmonic
See Figure 3
f = 1MHz
R
L
= 200
V
O
= 2V
PP
40
35
30
25
20
15
TWO-TONE, 3RD-ORDER
INTERMODULATION INTERCEPT
Frequency (MHz)
Int
e
r
c
ept
P
o
i
n
t
(
+
d
B
m
)
0
5
10
15
20
25
30
402
OPA820
P
I
+5V
P
O
57.6
200
806
806
402
0.01
F
0.01
F
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
12
TYPICAL CHARACTERISTICS: V
S
= +5V (continued)
RF = 402
, RL = 100
, and G = +2, unless otherwise noted.
100
10
1
RECOMMENDED R
S
vs CAPACITIVE LOAD
Capacitive Load (pF)
1
10
100
1000
R
S
(
)
0dB Peaking Targeted
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
TYPICAL DC DRIFT OVER TEMPERATURE
Ambient Temperature (
_
C)
In
put
O
f
fs
e
t
V
o
l
t
ag
e
(
m
V
)
15
10
5
0
-
5
-
10
-
15
In
put
B
i
as
a
n
d
O
ff
s
e
t
C
u
r
r
e
nt
(
V)
-
50
-
25
0
25
50
75
100
125
10x Input Offset Current (I
OS
)
Right Scale
Input Offset Voltage (V
OS
)
Left Scale
Input Bias Current (I
B
)
Right Scale
3500
3000
2500
2000
1500
1000
500
0
TYPICAL INPUT OFFSET VOLTAGE DISTRIBUTION
Input Offset Voltage (mV)
C
ount
-
1.
0
8
-
0.
9
7
-
0.
8
6
-
0.
7
6
-
0.
6
5
-
0.
5
4
-
0.
4
3
-
0.
3
2
-
0.
2
2
-
0.
1
1
0
0.11
0.22
0.32
0.43
0.54
0.65
0.76
0.86
0.97
1.08
Mean =
-
490
V
Standard Deviation = 90
V
Total Count = 6115
8
7
6
5
4
3
2
1
0
-
1
-
2
-
3
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Frequency (MHz)
N
o
r
m
al
i
z
e
d
G
a
i
n
t
o
C
a
p
a
c
i
ti
v
e
Load
(
d
B
)
1
10
100
300
C
L
= 10pF
C
L
= 22pF
C
L
= 47pF
C
L
= 100pF
402
R
S
OPA820
V
I
+5V
V
O
57.6
1k
(1)
806
806
C
L
402
0.01
F
0.01
F
NOTE: (1) 1k
is optional.
125
100
75
50
25
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
Ambient Temperature (
_
C)
O
u
t
p
u
t
C
u
rr
e
n
t
(m
A
)
12
9
6
3
0
S
u
p
p
l
y
C
u
r
r
ent
(
m
A
)
-
50
-
25
0
25
50
75
100
125
Source Output Current
Supply Current
Sink Output Current
2000
1800
1600
1400
1200
1000
800
600
400
200
0
TYPICAL INPUT OFFSET CURRENT DISTRIBUTION
Input Offset Current (nA)
C
ount
-
38
0
-
34
2
-
30
4
-
26
6
-
22
8
-
19
0
-
15
2
-
11
4
-
76
-
38
0
38
76
114
152
190
228
266
304
342
380
Mean = 43nA
Standard Deviation = 50nA
Total Count = 6115
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
13
APPLICATIONS INFORMATION
WIDEBAND VOLTAGE-FEEDBACK
OPERATION
The combination of speed and dynamic range offered by the
OPA820 is easily achieved in a wide variety of application
circuits, providing that simple principles of good design
practice are observed. For example, good power-supply
decoupling, as shown in Figure 1, is essential to achieve the
lowest possible harmonic distortion and smooth frequency
response.
Proper PC board layout and careful component selection will
maximize the performance of the OPA820 in all applications,
as discussed in the following sections of this data sheet.
Figure 1 shows the gain of +2 configuration used as the basis
for most of the typical characteristics. Most of the curves were
characterized using signal sources with 50
driving
impedance and with measurement equipment presenting
50
load impedance. In Figure 1, the 50
shunt resistor at the
V
I
terminal matches the source impedance of the test
generator while the 50
series resistor at the V
O
terminal
provides a matching resistor for the measurement equipment
load. Generally, data sheet specifications refer to the voltage
swings at the output pin (V
O
in Figure 1). The 100
load,
combined with the 804
total feedback network load,
presents the OPA820 with an effective load of approximately
90
in Figure 1.
OPA820
+5V
-
5V
-
V
S
+V
S
R
S
50
V
O
V
IN
50
+
2.2
F
+
2.2
F
0.1
F
R
G
402
R
F
402
50
Source
50
Load
0.1
F
Figure 1. Gain of +2, High-Frequency Application
and Characterization Circuit
WIDEBAND INVERTING OPERATION
Operating the OPA820 as an inverting amplifier has several
benefits and is particularly useful when a matched 50
source
and input impedance is required. Figure 2 shows the inverting
gain of -1 circuit used as the basis of the inverting mode
typical characteristics.
OPA820
+5V
-
5V
50
V
O
V
I
+
0.1
F
2.2
F
+
0.1
F
2.2
F
R
M
57.6
R
T
205
R
F
402
50
Source
50
Load
0.01
F
R
G
402
Figure 2. Inverting G = -1 Specifications and Test
Circuit
In the inverting case, just the feedback resistor appears as
part of the total output load in parallel with the actual load. For
the 100
load used in the typical characteristics, this gives a
total load of 80
in this inverting configuration. The gain
resistor is set to get the desired gain (in this case 402
for a
gain of -1) while an additional input matching resistor (R
M
) can
be used to set the total input impedance equal to the source
if desired. In this case, R
M
= 57.6
in parallel with the 402
gain setting resistor gives a matched input impedance of 50
.
This matching is only needed when the input needs to be
matched to a source impedance, as in the characterization
testing done using the circuit of Figure 2.
The OPA820 offers extremely good DC accuracy as well as
low noise and distortion. To take full advantage of that DC
precision, the total DC impedance looking out of each of the
input nodes must be matched to get bias current cancellation.
For the circuit of Figure 2, this requires the 205
resistor
shown to ground on the noninverting input. The calculation for
this resistor includes a DC-coupled 50
source impedance
along with R
G
and R
M
. Although this resistor will provide
cancellation for the bias current, it must be well decoupled
(0.01
F in Figure 2) to filter the noise contribution of the
resistor and the input current noise.
As the required R
G
resistor approaches 50
at higher gains,
the bandwidth for the circuit in Figure 2 will far exceed the
bandwidth at that same gain magnitude for the noninverting
circuit of Figure 1. This occurs due to the lower noise gain for
the circuit of Figure 2 when the 50
source impedance is
included in the analysis. For instance, at a signal gain of -10
(R
G
= 50
, R
M
= open, R
F
= 499
) the noise gain for the
circuit of Figure 2 will be 1 + 499
/(50
+ 50
) = 6 as a result
of adding the 50
source in the noise gain equation. This
gives considerable higher bandwidth than the noninverting
gain of +10. Using the 240MHz gain bandwidth product for the
OPA820, an inverting gain of -10 from a 50
source to a 50
R
G
gives 55MHz bandwidth, whereas the noninverting gain of
+10 gives 30MHz.
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
14
WIDEBAND SINGLE-SUPPLY OPERATION
Figure 3 shows the AC-coupled, single +5V supply, gain of
+2V/V circuit configuration used as a basis for the +5V only
Electrical and Typical Characteristics. The key requirement for
single-supply operation is to maintain input and output signal
swings within the useable voltage ranges at both the input and
the output. The circuit of Figure 3 establishes an input
midpoint bias using a simple resistive divider from the +5V
supply (two 806
resistors) to the noninverting input. The
input signal is then AC-coupled into this midpoint voltage bias.
The input voltage can swing to within 0.9V of the negative
supply and 0.5V of the positive supply, giving a 3.6V
PP
input
signal range. The input impedance matching resistor (57.6
)
used in Figure 3 is adjusted to give a 50
input match when
the parallel combination of the biasing divider network is
included. The gain resistor (R
G
) is AC-coupled, giving the
circuit a DC gain of +1. This puts the input DC bias voltage
(2.5V) on the output as well. On a single +5V supply, the output
voltage can swing to within 1.3V of either supply pin while
delivering more than 80mA output current giving 2.4V output
swing into 100
(5.6dBm maximum at the matched load).
Figure 4 shows the AC-coupled, single +5V supply, gain of
-1V/V circuit configuration used as a basis for the +5V only
Typical Characteristic curves. In this case, the midpoint DC
bias on the noninverting input is also decoupled with an
additional 0.01
F decoupling capacitor. This reduces the
source impedance at higher frequencies for the noninverting
input bias current noise. This 2.5V bias on the noninverting
input pin appears on the inverting input pin and, since R
G
is DC
blocked by the input capacitor, will also appear at the output
pin.
The single-supply test circuits of Figure 3 and Figure 4 show
+5V operation. These same circuits can be used over a single-
supply range of +5V to +12V. Operating on a single +12V
supply, with the Absolute Maximum Supply voltage
specification of +13V, gives adequate design margin for the
typical
5% supply tolerance.
OPA820
+5V
+V
S
DIS
100
R
G
402
806
806
57.6
0.01
F
+
6.8
F
0.1
F
0.01
F
V
I
50
Source
R
F
402
V
O
V
S
/2
Figure 3. AC-Coupled, G = +2V/V, Single-Supply Specifications and Test Circuit
OPA820
+5V
+V
S
DIS
100
R
G
402
806
806
0.01
F
0.01
F
V
I
R
F
402
V
O
V
S
/2
+
6.8
F
0.1
F
Figure 4. AC-Coupled, G = -1V/V, Single-Supply Specifications and Test Circuit
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
15
BUFFERING HIGH-PERFORMANCE ADCs
To achieve full performance from a high dynamic range ADC,
considerable care must be exercised in the design of the input
amplifier interface circuit. The example circuit on the front
page shows a typical AC-coupled interface to a very high
dynamic range converter. This AC-coupled example allows
the OPA820 to be operated using a signal range that swings
symmetrically around ground (0V). The 2V
PP
swing is then
level-shifted through the blocking capacitor to a midscale
reference level, which is created by a well-decoupled resistive
divider off the converter's internal reference voltages. To have
a negligible effect (1dB) on the rated spurious-free dynamic
range (SFDR) of the converter, the amplifier's SFDR should be
at least 18dB greater than the converter. The OPA820 has
minimal effect on the rated distortion of the ADS850, given its
79dB SFDR at 2V
PP
, 1MHz. The > 90dB (< 1MHz) SFDR for
the OPA820 in this configuration implies a < 3dB degradation
(for the system) from the converter's specification. For further
SFDR improvement with the OPA820, a differential
configuration is suggested.
Successful application of the OPA820 for ADC driving
requires careful selection of the series resistor at the amplifier
output, along with the additional shunt capacitor at the ADC
input. To some extent, selection of this RC network will be
determined empirically for each converter. Many high-
performance CMOS ADCs, such as the ADS850, perform
better with the shunt capacitor at the input pin. This capacitor
provides low source impedance for the transient currents
produced by the sampling process. Improved SFDR is often
obtained by adding this external capacitor, whose value is
often recommended in this converter data sheet. The external
capacitor, in combination with the built-in capacitance of the
ADC input, presents a significant capacitive load to the
OPA820. Without a series isolation resistor, an undesirable
peaking or loss of stability in the amplifier may result.
Since the DC bias current of the CMOS ADC input is
negligible, the resistor has no effect on overall gain or offset
accuracy. Refer to the typical characteristic R
S
vs Capacitive
Load to obtain a good starting value for the series resistor. This
will ensure flat frequency response to the ADC input.
Increasing the external capacitor value will allow the series
resistor to be reduced. Intentionally bandlimiting using this RC
network can also be used to limit noise at the converter input.
VIDEO LINE DRIVING
Most video distribution systems are designed with 75
series
resistors to drive a matched 75
cable. In order to deliver a net
gain of 1 to the 75
matched load, the amplifier is typically set
up for a voltage gain of +2, compensating for the 6dB
attenuation of the voltage divider formed by the series and
shunt 75
resistors at either end of the cable.
The circuit of Figure 1 applies to this requirement if all
references to 50
resistors are replaced by 75
values.
Often, the amplifier gain is further increased to 2.2, which
recovers the additional DC loss of a typical long cable run. This
change would require the gain resistor (R
G
) in Figure 1 to be
reduced from 402
to 335
. In either case, both the gain
flatness and the differential gain/phase performance of the
OPA820 will provide exceptional results in video distribution
applications. Differential gain and phase measure the change
in overall small-signal gain and phase for the color sub-carrier
frequency (3.58MHz in NTSC systems) versus changes in the
large-signal output level (which represents luminance
information in a composite video signal). The OPA820, with
the typical 150
load of a single matched video cable, shows
less than 0.01%/0.01
differential gain/phase errors over the
standard luminance range for a positive video (negative sync)
signal. Similar performance would be observed for multiple
video signals, as shown in Figure 5.
OPA820
V
OUT
402
335
Video
Input
75
75
75
Transmission Line
V
OUT
75
75
V
OUT
75
75
75
High output current drive capability allows three
back-terminated 75
transmission lines to be simultaneously driven.
Figure 5. Video Distribution Amplifier
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
16
SINGLE OP AMP DIFFERENTIAL AMPLIFIER
The voltage-feedback architecture of the OPA820, with its
high common-mode rejection ratio (CMRR), will provide
exceptional performance in differential amplifier configura-
tions. Figure 6 shows a typical configuration. The starting
point for this design is the selection of the R
F
value in the range
of 200
to 2k
. Lower values reduce the required R
G
,
increasing the load on the V
2
source and on the OPA820
output. Higher values increase output noise as well as the
effects of parasitic board and device capacitances. Following
the selection of R
F
, R
G
must be set to achieve the desired
inverting gain for V
2
. Remember that the bandwidth will be set
approximately by the gain bandwidth product (GBP) divided
by the noise gain (1 + R
F
/R
G
). For accurate differential
operation (that is, good CMRR), the ratio R
2
/R
1
must be set
equal to R
F
/R
G
.
OPA820
+5V
-
5V
R
2
50
Power-supply decoupling not shown.
V
2
R
1
V
1
R
F
R
G
V
O
=
(V
1
-
V
2
)
R
F
R
G
when
=
R
2
R
1
R
F
R
G
Figure 6. High-Speed, Single Differential
Amplifier
Usually, it is best to set the absolute values of R
2
and R
1
equal
to R
F
and R
G
, respectively; this equalizes the divider
resistances and cancels the effect of input bias currents.
However, it is sometimes useful to scale the values of R
2
and
R
1
in order to adjust the loading on the driving source, V
1
. In
most cases, the achievable low-frequency CMRR will be
limited by the accuracy of the resistor values. The 85dB
CMRR of the OPA820 itself will not determine the overall circuit
CMRR unless the resistor ratios are matched to better than
0.003%. If it is necessary to trim the CMRR, then R
2
is the
suggested adjustment point.
THREE OP AMP DIFFERENCING
(Instrumentation Topology)
The primary drawback of the single op amp differential
amplifier is its relatively low input impedances. Where high
impedance is required at the differential input, a standard
instrumentation amplifier (INA) topology may be built using the
OPA820 as the differencing stage. Figure 7 shows an
example of this, in which the two input amplifiers are packaged
together as a dual voltage-feedback op amp, the OPA2822.
This approach saves board space, cost, and power compared
to using two additional OPA820 devices, and still achieves
very good noise and distortion performance as a result of the
moderate loading on the input amplifiers.
OPA820
Power-supply decoupling not shown.
V
O
V
1
R
G
500
V
2
OPA2822
+5V
+5V
-
5V
-
5V
OPA2822
500
500
R
F1
500
500
500
R
F1
500
Figure 7. Wideband 3-Op Amp Differencing
Amplifier
In this circuit, the common-mode gain to the output is always
1, because of the four matched 500
resistors, whereas the
differential gain is set by (1 + 2R
F1
/R
G
), which is equal to 2
using the values in Figure 7. The differential to single-ended
conversion is still performed by the OPA820 output stage. The
high-impedance inputs allow the V
1
and V
2
sources to be
terminated or impedance-matched as required. If the V
1
and
V
2
inputs are already truly differential, such as the output from
a signal transformer, then a single matching termination
resistor may be used between them. Remember, however,
that a defined DC signal path must always exist for the V
1
and
V
2
inputs; for the transformer case, a center-tapped secon-
dary connected to ground would provide an optimum DC
operating point.
DAC TRANSIMPEDANCE AMPLIFIER
High-frequency Digital-to-Analog Converters (DACs) require
a low-distortion output amplifier to retain their SFDR
performance into real-world loads. See Figure 8 for a
single-ended output drive implementation. In this circuit, only
one side of the complementary output drive signal is used. The
diagram shows the signal output current connected into the
virtual ground-summing junction of the OPA820, which is set
up as a transimpedance stage or I-V converter. The unused
current output of the DAC is connected to ground. If the DAC
requires its outputs to be terminated to a compliance voltage
other than ground for operation, then the appropriate voltage
level may be applied to the noninverting input of the OPA820.
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
17
OPA820
High-Speed
DAC
V
O
= I
D
R
F
R
F
C
F
GBP
Gain Bandwidth
Product (Hz) for the OPA820.
C
D
I
D
I
D
Figure 8. Wideband, Low-Distortion DAC
Transimpedance Amplifier
The DC gain for this circuit is equal to R
F
. At high frequencies,
the DAC output capacitance (C
D
) will produce a zero in the
noise gain for the OPA820 that may cause peaking in the
closed-loop frequency response. C
F
is added across R
F
to
compensate for this noise-gain peaking. To achieve a flat
transimpedance frequency response, this pole in the
feedback network should be set to:
1
2
p
R
F
C
F
+
GBP
4
p
R
F
C
D
which will give a corner frequency f
-3dB
of approximately:
f
*
3dB
+
GBP
2
p
R
F
C
D
ACTIVE FILTERS
Most active filter topologies will have exceptional performance
using the broad bandwidth and unity-gain stability of the
OPA820. Topologies employing capacitive feedback require
a unity-gain stable, voltage-feedback op amp. Sallen-Key
filters simply use the op amp as a noninverting gain stage
inside an RC network. Either current- or voltage-feedback op
amps may be used in Sallen-Key implementations.
Figure 9 shows an example Sallen-Key low-pass filter, in
which the OPA820 is set up to deliver a low-frequency gain of
+2. The filter component values have been selected to
achieve a maximally-flat Butterworth response with a 5MHz,
-3dB bandwidth. The resistor values have been slightly
adjusted to compensate for the effects of the 240MHz
bandwidth provided by the OPA820 in this configuration. This
filter may be combined with the ADC driver suggestions to
provide moderate (2-pole) Nyquist filtering, limiting noise, and
out-of-band harmonics into the input of an ADC. This filter will
deliver the exceptionally low harmonic distortion required by
high SFDR ADCs such as the ADS850 (14-bit, 10MSPS,
82dB SFDR).
OPA820
+5V
-
5V
R
2
505
C
1
150pF
R
1
124
V
O
V
1
R
G
402
R
F
402
C
2
100pF
Power-supply
decoupling not shown.
Figure 9. 5MHz Butterworth Low-Pass Active
Filter
Another type of filter, a high-Q bandpass filter, is shown in
Figure 10. The transfer function for this filter is:
V
OUT
V
IN
+
s
R
3
)
R
4
R
1
R
4
C
1
s
2
)
s
1
R
1
C
1
)
R
3
R
2
R
4
R
5
C
1
C
2
with
w
O
2
+
R
3
R
2
R
4
R
5
C
1
C
2
and
w
O
Q
+
1
R
1
C
1
For the values chosen in Figure 10:
f
O
+
w
O
2
p ]
1MHz
and
Q = 100
See Figure 11 for the frequency response of the filter
shown in Figure 10.
OPA820
OPA820
V
OUT
R
3
500
R
4
500
R
5
158
C
2
1000pF
R
1
15.8k
R
2
158
V
IN
C
1
1000pF
Figure 10. High-Q 1MHz Bandpass Filter
(1)
(2)
(3)
(4)
(5)
(6)
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
18
6
0
-
6
-
12
-
18
-
24
-
30
-
36
-
42
-
48
-
54
-
60
-
66
-
72
Frequency (Hz)
Ga
i
n
(d
B
)
100k
1M
10M
100M
Figure 11. High-Q 1MHz Bandpass Filter
Frequency Response
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Two PC boards are available to assist in the initial evaluation
of circuit performance using the OPA820 in its two package
styles. Both of these are available, free, as an unpopulated PC
board delivered with descriptive documentation. The
summary information for these boards is shown in the table
below.
PRODUCT
PACKAGE
BOARD PART
NUMBER
LITERATURE
REQUEST
NUMBER
OPA820ID
SO-8
DEM-OPA68xU
SBOU010
OPA820IDBV
SOT23-5
DEM-OPA6xxN
SBOU009
Go to the TI web site (www.ti.com) to request evaluation
boards in the OPA820 product folder.
MACROMODELS AND APPLICATIONS
SUPPORT
Computer simulation of circuit performance using SPICE is
often a quick way to analyze the performance of the OPA820
and its circuit designs. This is particularly true for video and R
F
amplifier circuits where parasitic capacitance and inductance
can play a major role on circuit performance. A SPICE model
for the OPA820 is available through the TI web page
(www.ti.com). The applications department is also available
for design assistance. These models predict typical
small-signal AC, transient steps, DC performance, and noise
under a wide variety of operating conditions. The models
include the noise terms found in the electrical specifications of
the data sheet. These models do not attempt to distinguish
between the package types in their small-signal AC
performance.
OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES
Since the OPA820 is a unity-gain stable, voltage-feedback op
amp, a wide range of resistor values may be used for the
feedback and gain-setting resistors. The primary limits on
these values are set by dynamic range (noise and distortion)
and parasitic capacitance considerations. Usually, the feed-
back resistor value should be between 200
and 1k
. Below
200
, the feedback network will present additional output
loading which can degrade the harmonic distortion perfor-
mance of the OPA820. Above 1k
, the typical parasitic
capacitance (approximately 0.2pF) across the feedback
resistor may cause unintentional band limiting in the amplifier
response. A direct short is suggested as a feedback for
A
V
= +1V/V.
A good rule of thumb is to target the parallel combination of R
F
and R
G
(see Figure 1) to be less than about 200
. The
combined impedance R
F
|| R
G
interacts with the inverting input
capacitance, placing an additional pole in the feedback
network, and thus a zero in the forward response. Assuming
a 2pF total parasitic on the inverting node, holding R
F
|| R
G
<
200
will keep this pole above 400MHz. By itself, this
constraint implies that the feedback resistor R
F
can increase
to several k
at high gains. This is acceptable as long as the
pole formed by R
F
and any parasitic capacitance appearing in
parallel is kept out of the frequency range of interest.
In the inverting configuration, an additional design
consideration must be noted. R
G
becomes the input resistor
and therefore the load impedance to the driving source. If
impedance matching is desired, R
G
may be set equal to the
required termination value. However, at low inverting gains,
the resulting feedback resistor value can present a significant
load to the amplifier output. For example, an inverting gain of
2 with a 50
input matching resistor (= R
G
) would require a
100
feedback resistor, which would contribute to output
loading in parallel with the external load. In such a case, it
would be preferable to increase both the R
F
and R
G
values,
and then achieve the input matching impedance with a third
resistor to ground (see Figure 2). The total input impedance
becomes the parallel combination of R
G
and the additional
shunt resistor.
BANDWIDTH vs GAIN
Voltage-feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the GBP shown in the
specifications. Ideally, dividing GBP by the noninverting signal
gain (also called the noise gain, or NG) will predict the
closed-loop bandwidth. In practice, this only holds true when
the phase margin approaches 90
, as it does in high-gain
configurations. At low signal gains, most amplifiers will exhibit
a more complex response with lower phase margin. The
OPA820 is optimized to give a maximally-flat, 2nd-order
Butterworth response in a gain of 2. In this configuration, the
OPA820 has approximately 64
of phase margin and will show
a typical -3dB bandwidth of 240MHz. When the phase margin
is 64
, the closed-loop bandwidth is approximately
2 greater
than the value predicted by dividing GBP by the noise gain.
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
19
Increasing the gain will cause the phase margin to approach
90
and the bandwidth to more closely approach the predicted
value of (GBP/NG). At a gain of +10, the 30MHz bandwidth
shown in the Electrical Characteristics agrees with that
predicted using the simple formula and the typical GBP of
280MHz.
OUTPUT DRIVE CAPABILITY
The OPA820 has been optimized to drive the demanding load
of a doubly-terminated transmission line. When a 50
line is
driven, a series 50
into the cable and a terminating 50
load
at the end of the cable are used. Under these conditions, the
cable impedance will appear resistive over a wide frequency
range, and the total effective load on the OPA820 is 100
in
parallel with the resistance of the feedback network. The
electrical characteristics show a
3.6V swing into this
load--which will then be reduced to a
1.8V swing at the
termination resistor. The
75mA output drive over tempera-
ture provides adequate current drive margin for this load.
Higher voltage swings (and lower distortion) are achievable
when driving higher impedance loads.
A single video load typically appears as a 150
load (using
standard 75
cables) to the driving amplifier. The OPA820
provides adequate voltage and current drive to support up to
three parallel video loads (50
total load) for an NTSC signal.
With only one load, the OPA820 achieves an exceptionally low
0.01%/0.03
dG/dP error.
DRIVING CAPACITIVE LOADS
One of the most demanding, and yet very common, load
conditions for an op amp is capacitive loading. A high-speed,
high open-loop gain amplifier like the OPA820 can be very
susceptible to decreased stability and closed-loop response
peaking when a capacitive load is placed directly on the output
pin. In simple terms, the capacitive load reacts with the
open-loop output resistance of the amplifier to introduce an
additional pole into the loop and thereby decrease the phase
margin. This issue has become a popular topic of application
notes and articles, and several external solutions to this
problem have been suggested. When the primary
considerations are frequency response flatness, pulse
response fidelity, and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This does not
eliminate the pole from the loop response, but rather shifts it
and adds a zero at a higher frequency. The additional zero
acts to cancel the phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
The Typical Characteristics show the recommended R
S
vs
Capacitive Load and the resulting frequency response at the
load. The criterion for setting the recommended resistor is
maximum bandwidth, flat frequency response at the load.
Since there is now a passive low-pass filter between the
output pin and the load capacitance, the response at the
output pin itself is typically somewhat peaked, and becomes
flat after the roll-off action of the RC network. This is not a
concern in most applications, but can cause clipping if the
desired signal swing at the load is very close to the amplifier's
swing limit. Such clipping would be most likely to occur in pulse
response applications where the frequency peaking is
manifested as an overshoot in the step response.
Parasitic capacitive loads greater than 2pF can begin to
degrade the performance of the OPA820. Long PC board
traces, unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded. Always
consider this effect carefully, and add the recommended
series resistor as close as possible to the OPA820 output pin
(see the Board Layout section).
DISTORTION PERFORMANCE
The OPA820 is capable of delivering an exceptionally low
distortion signal at high frequencies and low gains. The
distortion plots in the Typical Characteristics show the typical
distortion under a wide variety of conditions. Most of these
plots are limited to 100dB dynamic range. The OPA820
distortion does not rise above -90dBc until either the signal
level exceeds 0.9V and/or the fundamental frequency ex-
ceeds 500kHz. Distortion in the audio band is
-100dBc.
Generally, until the fundamental signal reaches very high
frequencies or powers, the 2nd-harmonic will dominate the
distortion with a negligible 3rd-harmonic component.
Focusing then on the 2nd-harmonic, increasing the load
impedance improves distortion directly. Remember that the
total load includes the feedback network--in the noninverting
configuration this is the sum of R
F
+ R
G
, whereas in the
inverting configuration this is just R
F
(see Figure 1). Increasing
the output voltage swing increases harmonic distortion
directly. Increasing the signal gain will also increase the
2nd-harmonic distortion. Again, a 6dB increase in gain will
increase the 2nd- and 3rd-harmonic by 6dB even with a
constant output power and frequency. Finally, the distortion
increases as the fundamental frequency increases because
of the roll-off in the loop gain with frequency. Conversely, the
distortion will improve going to lower frequencies down to the
dominant open-loop pole at approximately 100kHz. Starting
from the -85dBc 2nd-harmonic for 2V
PP
into 200
, G = +2
distortion at 1MHz (from the Typical Characteristics), the
2nd-harmonic distortion will not show any improvement below
100kHz and will then be:
-100dB - 20log (1MHz/100kHz) = -105dBc
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
20
NOISE PERFORMANCE
The OPA820 complements its low harmonic distortion with low
input noise terms. Both the input-referred voltage noise and
the two input-referred current noise terms combine to give a
low output noise under a wide variety of operating conditions.
Figure 12 shows the op amp noise analysis model with all the
noise terms included. In this model, all the noise terms are
taken to be noise voltage or current density terms in either
nV/
Hz or pA/
Hz.
4kT
R
G
R
G
R
F
R
S
OPA820
I
BI
E
O
I
BN
4kT = 1.6E
-
20J
at 290
_
K
E
RS
E
NI
4kTR
S
4kTR
F
Figure 12. Op Amp Noise Analysis Model
The total output spot noise voltage is computed as the square
root of the squared contributing terms to the output noise
voltage. This computation is adding all the contributing noise
powers at the output by superposition, then taking the square
root to get back to a spot noise voltage. Equation 3 shows the
general form for this output noise voltage using the terms
presented in Figure 12.
E
O
+
E
2
NI
)
I
BN
R
S
2
)
4kTR
S
NG
2
)
I
BI
R
F
2
)
4kTR
F
NG
Dividing this expression by the noise gain (NG = 1 + R
F
/R
G
)
will give the equivalent input referred spot noise voltage at the
noninverting input, as shown in Equation 4.
E
N
+
E
2
NI
)
I
BN
R
S
2
)
4kTR
S
)
I
BI
R
F
NG
2
)
4kTR
F
NG
Evaluating these two equations for the OPA820 circuit
presented in Figure 1 will give a total output spot noise voltage
of 6.44nV/
Hz and an equivalent input spot noise voltage of
3.22nV/
Hz.
DC OFFSET CONTROL
The OPA820 can provide excellent DC signal accuracy
because of its high open-loop gain, high common-mode
rejection, high power-supply rejection, and low input offset
voltage and bias current offset errors. To take full advantage
of this low input offset voltage, careful attention to input bias
current cancellation is also required. The high-speed input
stage for the OPA820 has a moderately high input bias current
(9
A typ into the pins) but with a very close match between the
two input currents--typically 100nA input offset current. The
total output offset voltage may be considerably reduced by
matching the source impedances looking out of the two inputs.
For example, one way to add bias current cancellation to the
circuit of Figure 1 would be to insert a 175
series resistor into
the noninverting input from the 50
terminating resistor. When
the 50
source resistor is DC-coupled, this will increase the
source impedance for the noninverting input bias current to
200
. Since this is now equal to the impedance looking out of
the inverting input (R
F
|| R
G
), the circuit will cancel the gains for
the bias currents to the output leaving only the offset current
times the feedback resistor as a residual DC error term at the
output. Using a 402
feedback resistor, this output error will
now be less than
0.4
A
402
=
160
V at 25
C.
THERMAL ANALYSIS
The OPA820 will not require heatsinking or airflow in most
applications. Maximum desired junction temperature would
set the maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed +150
C.
Operating junction temperature (T
J
) is given by
T
A
+ P
D
q
JA
. The total internal power dissipation (P
D
) is the
sum of quiescent power (P
DQ
) and additional power
dissipated in the output stage (P
DL
) to deliver load power.
Quiescent power is simply the specified no-load supply
current times the total supply voltage across the part. P
DL
will
depend on the required output signal and load but would, for
a grounded resistive load, be at a maximum when the output
is fixed at a voltage equal to 1/2 of either supply voltage (for
equal bipolar supplies). Under this worst-case condition,
P
DL
= V
S
2
/(4
R
L
), where R
L
includes feedback network
loading.
Note that it is the power in the output stage and not in the load
that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an
OPA820IDBV (SOT23-5 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85
C.
P
D
= 10V(6.4mA) + 5
2
/(4
(100
|| 800
)) = 134mW
Maximum T
J
= +85
C + (134mW
150
C/W) = 105
C
BOARD LAYOUT
Achieving optimum performance with a high-frequency
amplifier such as the OPA820 requires careful attention to
board layout parasitics and external component types.
Recommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the
noninverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be
unbroken elsewhere on the board.
(7)
(8)
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
21
b) Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1
F decoupling capacitors. At
the device pins, the ground and power-plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between the pins
and the decoupling capacitors. The power-supply connec-
tions should always be decoupled with these capacitors.
Larger (2.2
F to 6.8
F) decoupling capacitors, effective at
lower frequency, should also be used on the main supply pins.
These may be placed somewhat farther from the device and
may be shared among several devices in the same area of the
PC board.
c) Careful selection and placement of external compo-
nents will preserve the high-frequency performance of
the OPA820. Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a tighter overall
layout. Metal-film and carbon composition, axially leaded
resistors can also provide good high-frequency performance.
Again, keep their leads and PC board trace length as short as
possible. Never use wire-wound type resistors in a
high-frequency application. Since the output pin and inverting
input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if any,
as close as possible to the output pin. Other network
components, such as noninverting input termination resistors,
should also be placed close to the package. Where
double-side component mounting is allowed, place the
feedback resistor directly under the package on the other side
of the board between the output and inverting input pins. Even
with a low parasitic capacitance shunting the external
resistors, excessively high resistor values can create
significant time constants that can degrade performance.
Good axial metal-film or surface-mount resistors have
approximately 0.2pF in shunt with the resistor. For resistor
values > 1.5k
, this parasitic capacitance can add a pole
and/or a zero below 500MHz that can effect circuit operation.
Keep resistor values as low as possible consistent with
load-driving considerations. It has been suggested here that
a good starting point for design would be to set R
G
|| R
F
=
200
. Using this setting will automatically keep the resistor
noise terms low, and minimize the effect of their parasitic
capacitance.
d) Connections to other wideband devices on the board
may be made with short direct traces or through onboard
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R
S
from the
plot of Recommended R
S
vs Capacitive Load. Low parasitic
capacitive loads (< 5pF) may not need an R
S
since the
OPA820 is nominally compensated to operate with a 2pF
parasitic load. Higher parasitic capacitive loads without an R
S
are allowed as the signal gain increases (increasing the
unloaded phase margin). If a long trace is required, and the
6dB signal loss intrinsic to a doubly-terminated transmission
line is acceptable, implement a matched impedance
transmission line using microstrip or stripline techniques
(consult an ECL design handbook for microstrip and stripline
layout techniques). A 50
environment is normally not
necessary onboard, and in fact, a higher impedance
environment will improve distortion as shown in the distortion
versus load plots. With a characteristic board trace impedance
defined based on board material and trace dimensions, a
matching series resistor into the trace from the output of the
OPA820 is used as well as a terminating shunt resistor at the
input of the destination device. Remember also that the
terminating impedance will be the parallel combination of the
shunt resistor and input impedance of the destination device;
this total effective impedance should be set to match the trace
impedance. If the 6dB attenuation of a doubly-terminated
transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the trace as a
capacitive load in this case and set the series resistor value as
shown in the plot of R
S
vs Capacitive Load. This will not
preserve signal integrity as well as a doubly-terminated line.
If the input impedance of the destination device is low, there
will be some signal attenuation due to the voltage divider
formed by the series output into the terminating impedance.
e) Socketing a high-speed part like the OPA820 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an extremely
troublesome parasitic network, which can make it almost
impossible to achieve a smooth, stable frequency response.
Best results are obtained by soldering the OPA820 onto the
board.
OPA820
SBOS303A - JUNE 2004 - REVISED JULY 2004
www.ti.com
22
INPUT AND ESD PROTECTION
The OPA820 is built using a very high-speed complementary
bipolar process. The internal junction breakdown voltages are
relatively low for these very small geometry devices. These
breakdowns are reflected in the Absolute Maximum Ratings
table. All device pins are protected with internal ESD
protection diodes to the power supplies, as shown in
Figure 13.
External
Pin
+V
CC
-
V
CC
Figure 13. Internal ESD Protection
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (for example, in systems with
15V
supply parts driving into the OPA820), current-limiting series
resistors should be added into the two inputs. Keep these
resistor values as low as possible since high values degrade
both noise performance and frequency response. Figure 14
shows an example protection circuit for I/O voltages that may
exceed the supplies.
OPA820
+5V
-
5V
50
50
Power-supply
decoupling not shown.
174
D1
D2
V
1
R
G
301
50
R
F
301
V
O
D1 = D2 IN5911 (or equivalent)
50
Source
Figure 14. Gain of +2 with Input Protection
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