Document Outline
- FEATURES
- APPLICATIONS
- DESCRIPTION
- OPA847 RELATED PRODUCTS
- ABSOLUTE MAXIMUM RATINGS(
- PACKAGE/ORDERING INFORMATION
- PIN CONFIGURATIONS
- ELECTRICAL CHARACTERISTICS: VS = 5V
- TYPICAL CHARACTERISTICS: VS = 5V
- APPLICATIONS INFORMATION
- WIDEBAND, NONINVERTING OPERATION
- WIDEBAND, INVERTING GAIN OPERATION
- WIDEBAND, HIGH SENSITIVITY, TRANSIMPEDANCE DESIGN
- LOW- GAIN COMPENSATION FOR IMPROVED SFDR
- LOW-NOISE FIGURE, HIGH DYNAMIC RANGE AMPLIFIER
- NONINVERTING GAIN FLATNESS COMPENSATION
- DIFFERENTIAL OPERATION
- SINGLE-SUPPLY OPERATION
- DESIGN-IN TOOLS
- DEMONSTRATION BOARDS
- MACROMODELS AND APPLICATIONS SUPPORT
- OPERATING SUGGESTIONS
- SETTING RESISTOR VALUES TO MINIMIZE NOISE
- FREQUENCY RESPONSE CONTROL
- DRIVING CAPACITIVE LOADS
- DISTORTION PERFORMANCE
- DC ACCURACY AND OFFSET CONTROL
- POWER SHUTDOWN OPERATION
- THERMAL ANALYSIS
- BOARD LAYOUT
- PACKAGE DRAWINGS
- D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
- DBV (R-PDSO-G6) PLASTIC SMALL-OUTLINE
- IMPORTANT NOTICE
Wideband, Ultra-Low Noise, Voltage-Feedback
OPERATIONAL AMPLIFIER with Shutdown
APPLICATIONS
HIGH DYNAMIC RANGE ADC PREAMPS
LOW NOISE, WIDEBAND, TRANSIMPEDANCE
AMPLIFIERS
WIDEBAND, HIGH GAIN AMPLIFIERS
LOW NOISE DIFFERENTIAL RECEIVERS
ULTRASOUND CHANNEL AMPLIFIERS
IMPROVED UPGRADE FOR THE OPA687,
CLC425, AND LMH6624
FEATURES
HIGH GAIN BANDWIDTH: 3.9GHz
LOW INPUT VOLTAGE NOISE: 0.85nV/
Hz
VERY LOW DISTORTION: 105dBc (5MHz)
HIGH SLEW RATE: 950V/s
HIGH DC ACCURACY: V
IO
< 100V
LOW SUPPLY CURRENT: 18.1mA
LOW SHUTDOWN POWER: 2mW
STABLE FOR GAINS
12
Ultra-High Dynamic Range
Differential ADC Driver
DESCRIPTION
The OPA847 combines very high gain bandwidth and large
signal performance with an ultra-low input noise voltage
(0.85nV/
Hz
) while using only 18mA supply current. Where
power savings is critical, the OPA847 also includes an
optional power shutdown pin that, when pulled low, disables
the amplifier and decreases the supply current to < 1% of the
powered-up value. This optional feature may be left discon-
nected to ensure normal amplifier operation when no power-
down is required.
The combination of very low input voltage and current noise,
along with a 3.9GHz gain bandwidth product, make the
OPA847 an ideal amplifier for wideband transimpedance
applications. As a voltage gain stage, the OPA847 is opti-
mized for a flat frequency response at a gain of +20V/V and
is stable down to gains as low as +12V/V. New external
compensation techniques allow the OPA847 to be used at
any inverting gain with excellent frequency response control.
Using this technique in a differential Analog-to-Digital Con-
verter (ADC) interface application, shown below, can deliver
one of the highest dynamic-range interfaces available.
OPA847
SBOS251C JULY 2002 REVISED OCTOBER 2003
www.ti.com
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002-2003, Texas Instruments Incorporated
+5V
5V
OPA847
+5V
+5V
5V
850
39pF
OPA847
1.7pF
100pF
V
IN
+
V
IN
0.1
F
1.7pF
850
39pF
100
20
2k
2k
20
0.001
F
0.001
F
1:2
50
Source
< 5.1dB
Noise
Figure
ADS5421
14-Bit
40MSPS
100
100pF
V
CM
24.6dB Gain
Frequency (MHz)
DIFFERENTIAL OPA847 DRIVER DISTORTION
Harmonic Distortion (dBc)
10
70
75
80
85
90
95
100
105
110
20
30
40
50
2V
PP
, at converter input.
2nd-Harmonic
3rd-Harmonic
OPA847
OPA847 RELATED PRODUCTS
INPUT NOISE
GAIN BANDWIDTH
SINGLES
VOLTAGE (nV/
Hz
)
PRODUCT (MHz)
OPA842
2.6
200
OPA843
2.0
800
OPA846
1.2
1750
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
OPA847
2
SBOS251C
www.ti.com
PIN CONFIGURATIONS
Top View
SO
ABSOLUTE MAXIMUM RATINGS
(1)
Power Supply ............................................................................... 6.5V
DC
Internal Power Dissipation ........................ See Thermal Analysis Section
Differential Input Voltage .................................................................. 1.2V
Input Voltage Range ............................................................................ V
S
Storage Temperature Range: D, DBV .......................... 40C to +125C
Lead Temperature (soldering, 10s) .............................................. +300C
Junction Temperature (T
J
) ............................................................ +150C
ESD Rating (Human Body Model) .................................................. 1500V
(Charge Device Model) ............................................... 1500V
(Machine Model) ........................................................... 100V
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those specified is not implied.
PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE-LEAD
DESIGNATOR
(1)
RANGE
MARKING
NUMBER
MEDIA, QUANTITY
OPA847
SO-8
D
40C to +85C
OPA847
OPA847ID
Rails, 100
"
"
"
"
"
OPA847IDR
Tape and Reel, 2500
OPA847
SOT23-6
DBV
40C to +85C
OATI
OPA847IDBVT
Tape and Reel, 250
"
"
"
"
"
OPA847IDBVR
Tape and Reel, 3000
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
Top View
SOT
1
2
3
4
8
7
6
5
NC
Inverting Input
Noninverting Input
V
S
DIS
+V
S
Output
NC
NC = No Connection
1
2
3
6
4
+V
S
Inverting Input
Output
V
S
5
DIS
Noninverting Input
OATI
1
2
3
6
5
4
Pin Orientation/Package Marking
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from
performance degradation to complete device failure. Texas
Instruments recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
OPA847
3
SBOS251C
www.ti.com
OPA847ID, IDBV
TYP
MIN/MAX OVER TEMPERATURE
0C to
40C to
MIN/
TEST
PARAMETER
CONDITIONS
+25C
+25C
(1)
70C
(2)
+85C
(2)
UNITS
MAX LEVEL
(3)
ELECTRICAL CHARACTERISTICS: V
S
= 5V
Boldface limits are tested at +25C.
R
L
= 100
, R
F
= 750
,
R
G
= 39.2
, and G = +20 (see Figure 1 for AC performance only), unless otherwise noted.
NOTES: (1) Junction temperature = ambient for +25C specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23C
at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at 25C. Over temperature limits by characterization and simulation.
(B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. V
CM
is the input common-mode
voltage. (5) Tested < 3dB below minimum specified CMRR at CMIR limits.
AC PERFORMANCE (see Figure 1)
Closed-Loop Bandwidth
G = +12, R
G
= 39.2
, V
O
= 200mV
PP
600
MHz
typ
C
G = +20, R
G
= 39.2
, V
O
= 200mV
PP
350
230
210
195
MHz
min
B
G = +50, R
G
= 39.2
, V
O
= 200mV
PP
78
63
60
57
MHz
min
B
Gain Bandwidth Product (GBP)
G
+50
3900
3100
3000
2800
MHz
min
B
Bandwidth for 0.1dB Gain Flatness
G = +20, R
L
= 100
60
40
35
30
MHz
min
B
Peaking at a Gain of +12
4.5
7
10
12
dB
max
B
Harmonic Distortion
G = +20, f = 5MHz, V
O
= 2V
PP
2nd-Harmonic
R
L
= 100
74
70
69
68
dBc
max
B
R
L
= 500
105
90
89
88
dBc
max
B
3rd-Harmonic
R
L
= 100
103
96
91
88
dBc
max
B
R
L
= 500
110
105
100
90
dBc
max
B
2-Tone, 3rd-Order Intercept
G = +20, f = 20MHz
39
37
36
35
dBm
min
B
Input Voltage Noise Density
f > 1MHz
0.85
0.92
0.98
1.0
nV/
Hz
max
B
Input Current Noise Density
f > 1MHz
2.5
3.5
3.6
3.7
pA/
Hz
max
B
Pulse Response
Rise-and-Fall Time
0.2V Step
1.2
1.75
2.0
2.2
ns
max
B
Slew Rate
2V Step
950
700
625
535
V/s
min
B
Settling Time to 0.01%
2V Step
20
ns
typ
C
0.1%
2V Step
10
12
14
18
ns
max
B
1%
2V Step
6
8
10
12
ns
max
B
DC PERFORMANCE
(4)
Open-Loop Voltage Gain (A
OL
)
V
O
= 0V
98
90
89
88
dB
min
A
Input Offset Voltage
V
CM
= 0V
0.1
0.5
0.58
0.60
mV
max
A
Average Offset Voltage Drift
V
CM
= 0V
0.25
0.25
1.5
1.5
V/C
max
B
Input Bias Current
V
CM
= 0V
19
39
41
42
A
max
A
Input Bias Current Drift (magnitude)
V
CM
= 0V
15
15
40
70
nA/C
max
B
Input Offset Current
V
CM
= 0V
0.1
0.6
0.7
0.85
A
max
A
Input Offset Current Drift
V
CM
= 0V
0.1
0.1
2
3.5
nA/C
max
B
INPUT
Common-Mode Input Range (CMIR)
(5)
3.3
3.1
3.0
2.9
V
min
A
Common-Mode Rejection Ratio (CMRR)
V
CM
= 0.5V, Input Referred
110
95
93
90
dB
min
A
Input Impedance
Differential
V
CM
= 0V
2.7 || 2.0
k
|| pF
typ
C
Common-Mode
V
CM
= 0V
2.3 || 1.7
M
|| pF
typ
C
OUTPUT
Output Voltage Swing
400
Load
3.5
3.3
3.1
3.0
V
min
A
100
Load
3.4
3.2
3.0
2.9
V
min
A
Current Output, Sourcing
V
O
= 0V
100
60
56
52
mA
min
A
Current Output, Sinking
V
O
= 0V
75
60
56
52
mA
min
A
Closed-Loop Output Impedance
G = +20, f = < 100kHz
0.003
typ
C
POWER SUPPLY
Specified Operating Voltage
5
V
typ
C
Maximum Operating Voltage
6
6
6
6
V
max
A
Maximum Quiescent Current
V
S
= 5V
18.1
18.4
18.7
18.9
mA
max
A
Minimum Quiescent Current
V
S
= 5V
18.1
17.8
17.5
17.1
mA
min
A
Power-Supply Rejection Ratio
+PSRR, PSRR
|V
S
| = 4.5V to 5.5V, Input Referred
100
95
93
90
dB
min
A
POWER-DOWN (disabled low)
(Pin 8 on SO-8; Pin 5 on SOT23-6)
Power-Down Quiescent Current (+V
S
)
200
270
320
370
A
max
A
On Voltage (enabled high or floated)
3.5
3.75
3.85
3.95
V
min
A
Off Voltage (disabled asserted low)
1.8
1.7
1.6
1.5
V
max
A
Power-Down Pin Input Bias Current
(V
DIS
= 0)
150
190
200
210
A
max
A
Power-Down Time
200
ns
typ
C
Power-Up Time
60
ns
typ
C
Off Isolation
5MHz, Input to Output
70
dB
typ
C
THERMAL
Specification ID, IDBV
40 to +85
C
typ
C
Thermal Resistance,
JA
Junction-to-Ambient
D
SO-8
125
C/W
typ
C
DBV
SOT23
150
C/W
typ
C
OPA847
4
SBOS251C
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= 5V
T
A
= 25C, G = +20V/V, R
G
= 39.2
, and R
L
= 100
, unless otherwise noted.
6
3
0
3
6
9
12
15
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Frequency (MHz)
Normalized Gain (dB)
1
10
100
1000
G = +50
See Figure 1
V
O
= 0.2V
PP
R
G
= 39.2
R
L
= 100
R
F
Adjusted
G = +30
G = +12
G = +20
6
3
0
3
6
9
12
15
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Frequency (MHz)
Normalized Gain (dB)
1
10
100
1000
G = 50
See Figure 2
V
O
= 0.2V
PP
R
L
= 100
R
G
= R
S
= 50
R
F
Adjusted
G = 40
G = 30
G = 20
29
26
23
20
17
14
11
8
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
Frequency (MHz)
Gain (dB)
10
100
1000
V
O
= 2V
PP
See Figure 1
R
G
= 39.2
R
L
= 100
G = +20V/V
V
O
= 5V
PP
V
O
= 1V
PP
V
O
= 200mV
PP
35
32
29
26
23
20
17
14
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
Frequency (MHz)
Gain (dB)
10
100
1000
V
O
= 2V
PP
See Figure 2
R
L
= 100
R
G
= R
S
= 50
G = 40V/V
V
O
= 5V
PP
V
O
= 0.2V
PP
V
O
= 1V
PP
0.25
0.20
0.15
0.10
0.05
0
0.05
0.10
0.15
0.20
0.25
1.25
1.00
0.75
0.50
0.25
0
0.25
0.50
0.75
1.00
1.25
NONINVERTING PULSE RESPONSE
Time (5ns/div)
Output Voltage (50mV/div)
Output Voltage (250mV/div)
Small Signal
100mV
See Figure 1
G = +20V/V
Left Scale
Large Signal
1V
Right Scale
0.25
0.20
0.15
0.10
0.05
0
0.05
0.10
0.15
0.20
0.25
1.25
1.00
0.75
0.50
0.25
0
0.25
0.50
0.75
1.00
1.25
INVERTING PULSE RESPONSE
Time (5ns/div)
Output Voltage (50mV/div)
Output Voltage (250mV/div)
Small Signal
100mV
See Figure 2
G = 40V/V
R
G
= R
S
= 50
R
L
= 100
Left Scale
Large Signal
1V
Right Scale
OPA847
5
SBOS251C
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= 5V
(Cont.)
T
A
= 25C, G = +20V/V, R
G
= 39.2
, and R
L
= 100
, unless otherwise noted.
70
75
80
85
90
95
100
105
110
115
5MHz HARMONIC DISTORTION vs LOAD RESISTANCE
Load Resistance (
)
Harmonic Distortion (dBc)
100
150
200
250
300
350
400
450
500
See Figure 1
G = +20V/V
V
O
= 2V
PP
2nd-Harmonic
3rd-Harmonic
75
80
85
90
95
100
105
1MHz HARMONIC DISTORTION vs LOAD RESISTANCE
Load Resistance (
)
Harmonic Distortion (dBc)
100
150
200
250
300
350
400
450
500
See Figure 1
G = +20V/V
V
O
= 5V
PP
2nd-Harmonic
3rd-Harmonic
65
75
85
95
105
115
HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
Harmonic Distortion (dBc)
0.1
1
10
100
3rd-Harmonic
2nd-Harmonic
G = +20V/V
V
O
= 2
V
PP
R
L
= 200
See Figure 1
75
80
85
90
95
100
105
110
115
HARMONIC DISTORTION vs OUTPUT VOLTAGE
Output Voltage Swing (V
PP
)
Harmonic Distortion (dBc)
0.1
1
10
See Figure 1
G = +20V/V
F = 5MHz
R
L
= 200
2nd-Harmonic
3rd-Harmonic
75
80
85
90
95
100
105
110
HARMONIC DISTORTION vs NONINVERTING GAIN
Gain (V/V)
Harmonic Distortion (dBc)
15
20
25
30
35
40
45
50
55
50
See Figure 1
V
O
= 2V
PP
R
L
= 200
F = 5MHz
R
F
= 750
R
G
Adjusted
2nd-Harmonic
3rd-Harmonic
70
75
80
85
90
95
100
105
110
HARMONIC DISTORTION vs INVERTING GAIN
Gain
V/V
Harmonic Distortion (dBc)
20
25
30
35
40
45
50
See Figure 2
V
O
= 2V
PP
R
L
= 200
F = 5MHz
R
G
= 50
R
F
Adjusted
2nd-Harmonic
3rd-Harmonic
OPA847
6
SBOS251C
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= 5V
(Cont.)
T
A
= 25C, G = +20V/V, R
G
= 39.2
, and R
L
= 100
, unless otherwise noted.
10
1
0
INPUT VOLTAGE AND CURRENT NOISE
Frequency (Hz)
Voltage Noise (nV/
Hz)
Current Voise (pA/
Hz)
10
1
10
2
10
3
10
4
10
5
10
6
10
7
2.7pA/
Hz
Current Noise
0.85nV/
Hz
Voltage Noise
50
45
40
35
30
25
20
2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT
Frequency (MHz)
Intercept Point (+dBm)
5
10
15
20
25
30
35
40
45
50
G = +20V/V
20dB to matched load.
750
50
OPA847
P
I
P
O
50
50
39.2
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
NONINVERTING GAIN FLATNESS TUNE
Frequency (MHz)
Deviation from 21.58dB Gain (0.1dB)
1
10
100
1000
NG = 12
NG = 14
NG = 20
NG = 18
NG = 16
V
O
= 200mV
PP
A
V
= +12V/V
NG = Noise Gain
External Compensation
See Figure 8
1
0
1
2
3
4
5
6
7
8
9
LOW GAIN INVERTING BANDWIDTH
Frequency (MHz)
Normalized Gain (1dB)
1
10
100
1000
G = 8
G = 4
G = 2
G = 1
V
O
= 0.2V
PP
R
F
= 750
External Compensation
See Figure 6
100
10
1
RECOMMENDED R
S
vs CAPACITIVE LOAD
Capacitive Load (pF)
R
S
(
)
1
10
100
1000
G = +20V/V
29
26
23
20
17
14
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Frequency (MHz)
Normalized Gain to Capacitive Load (dB)
1
10
100
1000
C = 22pF
C = 47pF
C = 100pF
C = 10pF
R
S
adjusted for capacitive load.
750
R
S
OPA847
V
I
V
O
50
1k
C
L
39.2
(1k
is optional.)
OPA847
7
SBOS251C
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= 5V
(Cont.)
T
A
= 25C, G = +20V/V, R
G
= 39.2
, and R
L
= 100
, unless otherwise noted.
120
110
100
90
80
70
60
50
40
30
20
COMMON-MODE REJECTION RATIO AND
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
Frequency (Hz)
CMRR and PSRR (dB)
10
2
10
4
10
5
10
3
10
6
10
7
10
8
CMRR
+PSRR
PSRR
120
100
80
60
40
20
0
20
0
30
60
90
120
150
180
210
OPEN-LOOP GAIN AND PHASE
Frequency (Hz)
Open-Loop Gain (dB)
Open-Loop Phase (
)
10
2
10
4
10
5
10
3
10
6
10
7
10
8
10
9
20log (A
OL
)
A
OL
4
3
2
1
0
1
2
3
4
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
I
O
(mA)
V
O
(V)
150
100
50
0
50
100
150
R
L
= 100
R
L
= 25
R
L
= 50
10
1
0.1
0.01
0.001
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
Frequency (Hz)
Output Impedance (
)
10
3
10
4
10
5
10
6
10
7
10
8
G = +20V/V
750
OPA847
Z
O
V
DIS
39.2
10
8
6
4
2
0
2
4
6
8
10
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
NONINVERTING OVERDRIVE RECOVERY
Time (40ns/div)
Output Voltage (V)
Input Voltage (mV)
See Figure 1
G = +20V/V
R
L
= 100
Output
Left Scale
Input
Right Scale
10
8
6
4
2
0
2
4
6
8
10
0.25
0.20
0.15
0.10
0.05
0
0.05
0.10
0.15
0.20
0.25
INVERTING OVERDRIVE RECOVERY
Time (40ns/div)
Output Voltage (V)
Input Voltage (mV)
See Figure 2
G = 40V/V
R
G
= 50
R
L
= 100
Output
Left Scale
Input
Right Scale
OPA847
8
SBOS251C
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= 5V
(Cont.)
T
A
= 25C, G = +20V/V, R
G
= 39.2
, and R
L
= 100
, unless otherwise noted.
0.25
0.20
0.15
0.10
0.05
0
0.05
0.10
0.15
0.20
0.25
SETTLING TIME
Time (ns)
Percent of Final Value (%)
0
5
10
15
20
25
30
35
40
G = +20V/V
R
L
= 100
V
O
= 2V Step
See Figure 1
89
86
83
80
77
74
71
PHOTODIODE TRANSIMPEDANCE
FREQUENCY RESPONSE
Frequency (MHz)
Transimpedance Gain (dB
)
1
10
100
C
D
= 100pF
R
F
= 20k
C
F
Adjusted
C
D
= 50pF
C
D
= 20pF
C
D
= 10pF
[20log 20k
]
20k
OPA847
20k
V
O
C
DIODE
[C
D
]
C
F
I
O
0.01
F
0.2
0.1
0
0.1
0.2
25.0
12.5
0
12.5
25.0
TYPICAL DC DRIFT OVER TEMPERATURE
Ambient Temperature (
C)
Input Offset Voltage (mV)
Input Bias and Offset Current (
A)
50
25
0
25
50
75
100
125
100 x I
OS
V
IO
I
b
100
90
80
70
60
50
20
18
16
14
12
10
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
Ambient Temperature (
C)
Output Current (mA)
Supply Current (mA)
50
25
0
25
50
75
100
125
Sourcing Output Current
Supply Current
Sinking Output Current
5
4
3
2
1
0
1
2
3
4
5
COMMON-MODE INPUT RANGE AND OUTPUT SWING
vs SUPPLY VOLTAGE
Supply Voltage (
V)
Voltage Range (V)
2.50
2.75
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
5.00
5.25
5.50
5.75
6.00
Positive Output
R
L
= 100
Negative Output
Negative Input
Positive Input
10
7
10
6
10
5
10
4
10
3
10
2
COMMON-MODE AND DIFFERENTIAL
INPUT IMPEDANCE
Frequency (Hz)
Input Impedance (
)
10
2
10
4
10
5
10
3
10
6
10
7
10
8
Common-Mode
(2.3M
, DC)
Differential
(2.7k
, DC)
OPA847
9
SBOS251C
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= 5V
T
A
= 25C, G
D
= 40V/V, R
G
= 50
, and R
L
= 400
, unless otherwise noted.
R
F
OPA847
+5V
+5V
DIS
V
O
V
I
R
G
50
R
F
R
L
DIS
OPA847
5V
5V
R
G
50
G
D
=
=
V
O
V
I
R
F
R
G
3
0
3
6
9
12
15
18
DIFFERENTIAL SMALL-SIGNAL
FREQUENCY RESPONSE
Frequency (MHz)
Normalized Gain (dB)
10
100
1000
G
D
= +30V/V
G
D
= +40V/V
G
D
= +50V/V
G
D
= +20V/V
R
G
= 50
V
O
= 400mV
PP
R
F
Adjusted
35
32
29
26
23
DIFFERENTIAL LARGE-SIGNAL
FREQUENCY RESPONSE
Frequency (MHz)
Gain (dB)
1
10
100
1000
V
O
= 5V
PP
V
O
= 8V
PP
V
O
= 400mV
PP
G
D
= 40V/V
55
60
65
70
75
80
85
90
95
100
105
110
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
Resistance (
)
Harmonic Distortion (dBc)
50
100
150
200
250
300
350
400
450
500
2nd-Harmonic
3rd-Harmonic
G
D
= 40V/V
V
O
= 4V
PP
F = 5MHz
65
75
85
95
105
115
DIFFERENTIAL DISTORTION vs FREQUENCY
Frequency (MHz)
Harmonic Distortion (dBc)
1
10
100
2nd-Harmonic
G
D
= 40V/V
R
L
= 400
V
O
= 4V
PP
3rd-Harmonic
75
80
85
90
95
100
105
110
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
Differential Output Voltage Swing (V
PP
)
Harmonic Distortion (dBc)
1
10
2nd-Harmonic
G
D
= 40V/V
R
L
= 400
F = 5MHz
3rd-Harmonic
DIFFERENTIAL PERFORMANCE TEST CIRCUIT
OPA847
10
SBOS251C
www.ti.com
APPLICATIONS INFORMATION
WIDEBAND, NONINVERTING OPERATION
The OPA847 provides a unique combination of a very low
input voltage noise along with a very low distortion output
stage to give one of the highest dynamic range op amps
available. Its very high gain bandwidth product (GBP) can be
used to either deliver high signal bandwidths at high gains, or
to deliver very low distortion signals at moderate frequencies
and lower gains. To achieve the full performance of the
OPA847, careful attention to PC board layout and compo-
nent selection is required, as discussed in the following
sections of this data sheet.
Figure 1 shows the noninverting gain of a +20V/V circuit used
as the basis for most of the Typical Characteristics. Most of
the curves are characterized using signal sources with a
50
driving impedance and with measurement equipment
presenting a 50
load impedance. In Figure 1, the 50
shunt resistor at the V
I
terminal matches the source imped-
ance of the test generator, while the 50
series resistor at
the V
O
terminal provides a matching resistor for the mea-
surement equipment load. Generally, data sheet voltage
swing specifications are at the output pin (V
O
in Figure 1)
while output power specifications are at the matched 50
load. The total 100
load at the output combined with the
790
total feedback network load presents the OPA847 with
an effective output load of 89
for the circuit of Figure 1.
Voltage-feedback op amps, unlike current-feedback designs,
can use a wide range of resistor values to set their gain. The
circuit of Figure 1, and the specifications at other gains, use an
R
G
set to 39.2
and R
F
adjusted to get the desired gain. Using
this guideline ensures that the noise added at the output due
to the Johnson noise of the resistors does not significantly
increase the total over that due to the 0.85nV/
Hz
input
voltage noise for the op amp itself. This R
G
is suggested as
a good starting point for design. Other values are certainly
acceptable, if required by the design.
WIDEBAND, INVERTING GAIN OPERATION
There can be significant benefits to operating the OPA847 as
an inverting amplifier. This is particularly true when a matched
input impedance is required. Figure 2 shows the inverting
gain of a 40V/V circuit used as a starting point for the
Typical Characteristics showing inverting mode performance.
Driving this circuit from a 50
source, and constraining the gain
resistor (R
G
) to equal 50
, gives both a signal bandwidth and a noise
advantage. R
G
, in this case, acts as both the input termination resistor
and the gain setting resistor for the circuit. Although the signal gain
for the circuit of Figure 2 is double that for Figure 1, their noise gains
are nearly equal when the 50
source resistor is included. This has
the interesting effect of approximately doubling the equivalent GBP for
the amplifier. This can be seen by observing that the gain of 40
bandwidth of 240MHz shown in the Typical Characteristics implies a
gain bandwidth product of 9.6GHz, giving a far higher bandwidth at
a gain of 40 than at a gain of +40. While the signal gain from R
G
to
the output is 40, the noise gain for bandwidth setting purposes is
1 + R
F
/(2 R
G
). In the case of a 40V/V gain, using an R
G
= R
S
=
50
gives a noise gain = 1 + 2k
/100
= 21. This inverting gain of
40V/V therefore has a frequency response that more closely
matches the gain of a +20 frequency response.
If the signal source is actually the low impedance output of
another amplifier, R
G
should be increased to be greater than
the minimum value allowed at the output for that amplifier
and R
F
adjusted to get the desired gain. It is critical for stable
operation of the OPA847 that this driving amplifier show a
very low output impedance through frequencies exceeding
the expected closed-loop bandwidth for the OPA847.
WIDEBAND, HIGH SENSITIVITY,
TRANSIMPEDANCE DESIGN
OPA847
+5V
5V
V
S
+V
S
50
V
O
V
DIS
V
I
50
+
0.1
F
+
6.8
F
6.8
F
R
G
39.2
R
F
750
50
Source
50
Load
0.1
F
FIGURE 1. Noninverting G = +20 Specification and Test Circuit.
FIGURE 2. Noninverting G = 40 Specification and Test Circuit.
OPA847
+5V
5V
+V
S
V
S
95.3
50
V
O
V
I
+
6.8
F
0.1
F
+
6.8
F
0.1
F
0.01
F
R
F
2k
R
G
50
50
Source
50
Load
V
DIS
OPA847
11
SBOS251C
www.ti.com
The high GBP and low input voltage and current noise for the
OPA847 make it an ideal wideband transimpedance ampli-
fier for low to moderate transimpedance gains. Very high
transimpedance gains (> 100k
) will benefit from the low
input noise current of a JFET input op amp such as the
OPA657. Unity-gain stability in the op amp is not required for
application as a transimpedance amplifier. Figure 3 shows
one possible transimpedance design example that would be
particularly suitable for the 155Mbit data rate of an OC-3
receiver. Designs that require high bandwidth from a large
area detector with relatively low transimpedance gain will
benefit from the low input voltage noise for the OPA847. The
amplifier's input voltage noise is peaked up over frequency
by the diode source capacitance, and can (in many cases)
become the limiting factor to input sensitivity. The key ele-
ments to the design are the expected diode capacitance (C
D
)
with the reverse bias voltage (V
B
) applied, the desired
transimpedance gain (R
F
), and the GBP for the OPA847
(3900MHz). With these three variables set (including the
parasitic input capacitance for the OPA847 added to C
D
), the
feedback capacitor value (C
F
) can be set to control the
frequency response.
To achieve a maximally flat 2nd-order Butterworth frequency
response, set the feedback pole as shown in Equation 1.
Equation 2 gives the approximate 3dB bandwidth that
results if C
F
is set using Equation 1.
( )
Hz
C
R
2
GBP
f
D
F
dB
3
=
-
(2)
The example of Figure 3 gives approximately 104MHz flat
bandwidth using the 0.18pF feedback compensation capaci-
tor. This bandwidth easily supports an OC-3 receiver with
exceptional sensitivity.
If the total output noise is bandlimited to a frequency less
than the feedback pole frequency, a very simple expression
for the equivalent input noise current is shown as Equation 3.
(
)
3
F
C
2
e
R
e
R
kT
4
i
i
2
D
N
2
F
N
F
2
EQ
N
+
+
+
=
(3)
where:
i
EQ
= Equivalent input noise current if the output noise is
bandlimited to F < 1/(2
R
F
C
F
)
i
N
= Input current noise for the op amp inverting input
e
N
= Input voltage noise for the op amp
C
D
= Total Inverting Node Capacitance
f = Bandlimiting frequency in Hz (usually a post filter prior
to further signal processing)
Evaluating this expression up to the feedback pole fre-
quency at 74MHz for the circuit of Figure 3 gives an equiva-
lent input noise current of 3.0pA/
Hz
. This is slightly higher
than the 2.5pA/
Hz
input current noise for the op amp. This
total equivalent input current noise is slightly increased by
the last term in the equivalent input noise expression. It is
essential in this case to use a low-voltage noise op amp. For
example, if a slightly higher input noise voltage, but other-
wise identical, op amp were used instead of the OPA847 in
this application (say 2.0nV/
Hz
), the total input referred
current noise would increase to 3.7pA/
Hz
. Low input volt-
age noise is required for the best sensitivity in these wideband
transimpedance applications. This is often unspecified for
dedicated transimpedance amplifiers with a total output
noise for a specified source capacitance given instead. It is
the relatively high input voltage noise for those components
that cause higher than expected output noise if the source
capacitance is higher than specified.
The output DC error for the circuit of Figure 3 is minimized
by including a 12k
to ground on the noninverting input.
This reduces the contribution of input bias current errors (for
total output offset voltage) to the offset current times the
feedback resistor. To minimize the output noise contribution
of this resistor, 0.01F and 100pF capacitors are included in
parallel. Worst-case output DC error for the circuit of Figure
3 at 25C is:
V
os
= 0.5mV (input offset voltage) 0.6uA (input offset
current) 12k
= 7.2mV
Worst-case output offset DC drift (over the 0C to 70C span) is:
dV
os
/dT = 1.5V/C (input offset drift) 2nA/C (input
offset current drift) 12k
= 21.5V/C.
D
F
F
F
C
R
4
GBP
C
R
2
1
=
(1)
Adding the common-mode and differential mode input ca-
pacitance (1.2 + 2.5)pF to the 1pF diode source capacitance
of Figure 3, and targeting a 12k
transimpedance gain
using the 3900MHz GBP for the OPA847 requires a feed-
back pole set to 74MHz to get a nominal Butterworth fre-
quency response design. This requires a total feedback
capacitance of 0.18pF. That total is shown in Figure 3, but
recall that typical surface-mount resistors have a parasitic
capacitance of 0.2pF, leaving no external capacitor required
for this design.
FIGURE 3. Wideband, High Sensitivity, OC-3 Transimpedance
Amplifier.
R
F
12k
12k
0.1
F
100pF
Power-supply
decoupling not shown.
OPA847
+5V
5V
V
B
C
F
0.18pF
1pF
Photodiode
V
DIS
OPA847
12
SBOS251C
www.ti.com
Even with bias current cancellation, the output DC errors are
dominated in this example by the offset current term. Im-
proved output DC precision and drift are possible, particu-
larly at higher transimpedance gains, using the JFET input
OPA657. The JFET input removes the input bias current
from the error equation (eliminating the need for the resistor
to ground on the noninverting input), leaving only the input
offset voltage and drift as an output DC error term.
Included in the Typical Characteristics are transimpedance
frequency response curves for a fixed 20k
gain over
various detector diode capacitance settings. These curves
are repeated in Figure 4, along with the test circuit. As the
photodiode capacitance changes, the feedback capacitor
must change to maintain a stable and flat frequency re-
sponse. Using Equation 1, C
F
is adjusted to give the
Butterworth frequency responses shown in Figure 4.
Considering only the noise gain (which is the same as the
noninverting signal gain) for the circuit of Figure 5, the low-
frequency noise gain (N
G1
) is set by the resistor ratio, while
the high-frequency noise gain (N
G2
) is set by the capacitor
ratio. The capacitor values set both the transition frequencies
and the high-frequency noise gain. If the high-frequency
noise gain, determined by N
G2
= 1 + C
S
/C
F
, is set to a value
greater than the recommended minimum stable gain for the
op amp, and the noise gain pole (set by 1/R
F
C
F
) is placed
correctly, a very well controlled 2nd-order low-pass fre-
quency response results.
LOW-GAIN COMPENSATION FOR IMPROVED SFDR
Where a low gain is desired, and inverting operation is
acceptable, a new external compensation technique can be
used to retain the full slew rate and noise benefits of the
OPA847, while giving increased loop gain and the associ-
ated distortion improvements offered by a non-unity-gain
stable op amp. This technique shapes the loop gain for good
stability, while giving an easily controlled 2nd-order low-pass
frequency response. This technique is used for the circuit on
the front page of this data sheet in a differential configuration
to achieve extremely low distortion through high frequencies
(< 90dBc through 30MHz). The amplifier portion of this
circuit is set up for a differential gain of 8.5V/V from a
differential input signal to the output. Using the input trans-
former shown improves the noise figure and translates from
a single-ended to a differential signal. If the source is differ-
ential already, it can be fed directly into the gain setting
resistors. To set the compensation capacitors (C
S
and C
F
),
consider the half circuit of Figure 5, where the 50
source
is reflected through the 1:2 transformer, then cut in half, and
grounded to give a total impedance to the AC ground for the
circuit on the front page equal to 200
.
FIGURE 4. Transimpedance Bandwidth vs C
D
.
89
86
83
80
77
74
71
PHOTODIODE TRANSIMPEDANCE
FREQUENCY RESPONSE
Frequency (MHz)
Transimpedance Gain (dB
)
1
10
100
C
D
= 100pF
R
F
= 20k
C
F
Adjusted
C
D
= 50pF
C
D
= 20pF
C
D
= 10pF
20k
OPA847
20k
V
O
C
D
C
F
I
O
0.01
F
[20 log(20k
)]
To choose the values for both C
S
and C
F
, two parameters and only
three equations need to be solved. The first parameter is the target
high-frequency noise gain (NG
2
), which should be greater than the
minimum stable gain for the OPA847. Here, a target of NG
2
= 24 is
used. The second parameter is the desired low-frequency signal
gain, which also sets the low-frequency noise gain (NG
1
). To simplify
this discussion, we will target a maximally flat 2nd-order low-pass
Butterworth frequency response (Q = 0.707). The signal gain shown
in Figure 5 sets the low-frequency noise gain to NG
1
= 1 + R
F
/R
G
(= 5.25 in this example). Then, using only these two gains and the
GBP for the OPA847 (3900MHz), the key frequency in the compen-
sation is set by Equation 4.
-
-
-
=
2
1
2
1
2
1
O
NG
NG
2
1
NG
NG
1
NG
GBP
Z
(4)
Physically, this Z
O
(4.4MHz for the values shown above) is
set by 1/(2
R
F
(C
F
+ C
S
)) and is the frequency at which the
rising portion of the noise gain would intersect the unity gain
if projected back to a 0dB gain. The actual zero in the noise
gain occurs at NG
1
Z
O
and the pole in the noise gain occurs
at NG
2
Z
O
. That pole is physically set by 1/(R
F
C
F
). Since
GBP is expressed in Hz, multiply Z
O
by 2
and use to get C
F
by solving Equation 5.
C
F
=
1
2
R
F
Z
O
NG
2
= 1.76pF
(
)
(5)
FIGURE 5. Broadband, Low-Inverting Gain External
Compensation.
R
F
850
C
S
39pF
OPA847
+5V
5V
V
O
V
I
C
F
1.7pF
R
G
200
V
DIS
OPA847
13
SBOS251C
www.ti.com
Finally, since C
S
and C
F
set the high-frequency noise gain,
determine C
S
using Equation 6 (solving for C
S
by using NG
2
= 24):
F
2
S
C
)
1
NG
(
C
-
=
(6)
which gives C
S
= 40.6pF.
Both of these calculated values have been reduced slightly
in Figure 5 to account for parasitics. The resulting closed-
loop bandwidth is approximately equal to Equation 7.
GBP
Z
f
O
dB
3
(7)
For the values shown in Figure 5, f
3dB
is approximately
131MHz. This is less than that predicted by simply dividing
the GBP product by NG
1
. The compensation network controls
the bandwidth to a lower value, while providing the full slew
rate at the output and an exceptional distortion performance
due to increased loop gain at frequencies below NG
1
Z
O
.
Using this low-gain inverting compensation, along with the
differential structure for the circuit shown on the front page of
this data sheet, gives a significant reduction in harmonic
distortion. The measured distortion at 2V
PP
output does not
rise above 95dB until frequencies > 20MHz are applied.
The Typical Characteristics show the exceptional bandwidth con-
trol possible using this technique at low inverting gains. Figure 6
repeats the measured results with the test circuit shown.
The compensation capacitors, C
S
and C
F
, are set by targeting a
high-frequency noise gain of 21 and using equations 4 through
6. This approach allows relatively low inverting gain applications
to use the full slew rate and low input noise of the OPA847.
LOW-NOISE FIGURE,
HIGH DYNAMIC RANGE AMPLIFIER
The low input noise voltage of the OPA847 and its very high
2-tone, 3rd-order intermodulation intercept can be used to
good advantage as a fixed-gain amplifier. While input noise
figures in the 10dB range (for a matched 50
input) are
easily achieved with just the OPA847, Figure 7 illustrates a
technique to reduce the noise figure even further, while
providing a broadband, high-gain HF amplifier stage using
two stages of the OPA847.
FIGURE 6. Low-Gain Inverting Performance.
1
0
1
2
3
4
5
6
7
8
9
LOW GAIN INVERTING BANDWIDTH
Frequency (MHz)
Normalized Gain (1dB)
1
10
100
1000
G = 8
G = 4
G = 2
G = 1
V
O
= 0.2V
PP
R
F
750
C
S
OPA847
V
O
V
I
C
F
R
G
0
Source
V
DIS
+5V
5V
FIGURE 7. Very High Dynamic Range HF Amplifier.
OPA847
10pF
P
I
1.6pF
6.19k
750
1.5k
200
30.1
420
4.3dB
Noise
Figure
1:2
50
Source
P
O
> 55dBm
intercept
to 30MHz
OPA847
46pF
Input match
set by this
feedback path
Overall Gain = 35.6dB
P
O
P
I
+5V
5V
+5V
5V
OPA847
14
SBOS251C
www.ti.com
This circuit uses two stages of forward gain with an overall
feedback loop to set the input impedance match. The input
transformer provides both a noiseless voltage gain and a
signal inversion to retain an overall noninverting signal path
from P
I
to P
O
. The second amplifier stage is inverting to
provide the correct feedback polarity through the 6.19k
resistor. To achieve a 50
input match at the primary of the
1:2 transformer, the secondary must see a 200
load
impedance. At higher frequencies, the match is provided by
the 200
resistor in series with 10pF. The low-noise figure
(4.3dB) for this circuit is achieved by using the transformer,
the low-voltage noise OPA847, and the input match set by
the feedback at lower frequencies intended for this HF
design. The 1st-stage amplifier provides a gain of +15V/V.
The very high SFDR is provided by operating the output
stage at a low signal gain of 2 and using the inverting
compensation technique to shape the noise gain to hold it
stable. This 2nd-stage compensation is set to intentionally
bandlimit the overall response to approximately 100MHz. For
output loads > 400
, this circuit can give a 2-tone SFDR that
exceeds 90dB through 30MHz. In narrowband applications,
the 3rd-order intercept exceeds 55dBm. Besides offering a
very high dynamic range, this circuit improves on standard
HF amplifiers by offering a precisely controlled gain and a
very flexible output interface capability.
NONINVERTING GAIN FLATNESS COMPENSATION
Decreasing the operating gain from the nominal design point of
+20 decreases the phase margin. This increases Q for the
closed-loop poles, peaks up the frequency response, and
extends the bandwidth. A peaked frequency response shows
overshoot and ringing in the pulse response, as well as higher
integrated output noise. When operating the OPA847 at a
noninverting gain < +12V/V, increased peaking and possible
sustained oscillations may result. However, operation at low
gains may be desirable to take advantage of the higher slew
rate and exceptional DC precision of the OPA847. Numerous
external compensation techniques are suggested for operating
a high-gain op amp at low gains. Most of these give zero/pole
pairs in the closed-loop response that cause long term settling
tails in the pulse response and/or phase nonlinearity in the
frequency response.
Figure 8 shows a resistor based compensation technique
that allows the flatness at low noninverting signal gains to be
controlled separately from the signal gain. This approach
retains the full slew rate to the output but gives up some of
the low-noise benefit of the OPA847. Including the effect of
the total source impedance (25
in Figure 8), tuning resistor
R
1
can be set using Equation 8.
R
1
=
R
F
+ R
S
A
V
NG
- A
V
(8)
where,
A
V
= desired signal gain (+12V/V in Figure 8)
NG = target noise gain (adjusted in Figure 9)
R
S
= total source impedance
The effect of this noninverting gain flatness tune is shown in
Figure 9. At an NG of 12, R
1
is removed and only R
F
and R
G
are present in Figure 8. The peaking is typically 4.5dB, as
shown in the small-signal frequency response curves versus
gain curves at this setting. As R
1
is decreased, the operating
noise gain (NG) increases, reducing the peaking and band-
width until the nominal design point of +20 noise gain gives
a non-peaked response.
FIGURE 8. Low Noninverting Gain Flatness Trim.
R
F
750
R
G
66.5
R
1
50
OPA847
+5V
5V
V
I
V
O
50
50
V
DIS
FIGURE 9. Frequency Response Flatness with External
Tuning Resistor.
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
NONINVERTING GAIN FLATNESS TUNE
Frequency (MHz)
Deviation from 21.58dB Gain (0.1dB)
1
10
100
1000
NG = 12
NG = 14
NG = 20
NG = 18
NG = 16
V
O
= 200mV
PP
A
V
= +12V/V
NG = Noise Gain
DIFFERENTIAL OPERATION
Operating two OPA847 amplifiers in a differential inverting
configuration can further suppress even-order harmonic terms.
The Typical Characteristics show measured performance for
this condition. These measurements were done at the relatively
high gain of 40V/V. Even lower distortion is possible operating
at lower gains using the external inverting compensation tech-
niques, as discussed previously. For the distortion data pre-
sented in Figure 10, the output swing is increased to 4V
PP
into
400
to allow direct comparison to the single-channel data at
2V
PP
into 200
. Comparing the 2nd- and 3rd-harmonics at
20MHz in Figure 10 to the gain of +20, 2V
PP
, 200
data, shows
the 2nd-harmonic is reduced to 76dBc (from 67dBc) and the
3rd-harmonic is reduced from 80dBc to 85dBc. Using the two
OPA847
15
SBOS251C
www.ti.com
OPA847 can support this mode of operation down to a single
supply of +5V and up to a single supply of +12V. If shutdown
is desired for single-supply operation, it is important to
realize that the shutdown pin is referenced from the positive
supply pin. Open collector (drain) interfaces are suggested
for single-supply operation above +5V.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Two PC boards are available to assist in the initial evaluation
of circuit performance using the OPA847 in its two package
styles. Both of these are available, free, as unpopulated PC
boards delivered with descriptive documentation. The sum-
mary information for these boards is shown in Table I.
Contact your sales representative or go to the TI web site
(www.ti.com) to request these evaluation boards.
amplifiers in this configuration has significantly reduced the
2nd-harmonic, even after doubling the output voltage swing (to 4V
PP
)
and the gain (to 40V/V).
SINGLE-SUPPLY OPERATION
The OPA847 can be operated from a single power supply if
system constraints require it. Operation from a single +5V to
+12V supply is possible with minimal change in AC perfor-
mance. The Typical Characteristics show the input and
output voltage ranges for a bipolar supply range from 2.5V
to 6.0V. The Common-Mode Input Range and Output Swing
vs Supply Voltage curve shows that the required headroom
on both the input and output pins remains at approximately
1.5V over this entire range. On a single +5V supply, for
instance, this means the noninverting input should remain
centered at +2.5V 1V, as should the output pin. Figure 11
shows an example application biasing the noninverting input
at mid-supply and running an AC-coupled input to the invert-
ing gain path. Since the gain resistor is blocked off for DC,
the bias point on the noninverting input appears at the output,
centering up the output as well as on the power supply. The
FIGURE 10. Differential Distortion vs Frequency.
65
75
85
95
105
115
Frequency (MHz)
Harmonic Distortion (dBc)
1
10
100
2nd-Harmonic
G
D
= 40V/V
R
L
= 400
V
O
= 4V
PP
3rd-Harmonic
FIGURE 11. Single-Supply Inverting Amplifier.
R
F
Power-supply decoupling
not shown.
Range
2R
F
2R
F
0.01
F
R
G
V
I
OPA847
+V
CC
+12V
+5V
V
O
=
V
DIS
V
I
V
CC
2
R
F
R
G
BOARD
LITERATURE
PART
REQUEST
PRODUCT
PACKAGE
NUMBER
NUMBER
OPA847ID
SO-8
DEMOPA68XU
SBOU009
OPA847IDBV
SOT23-6
DEMOPA6XXN
SBOU010
TABLE I. Demo Board Part Numbers.
MACROMODELS AND APPLICATIONS SUPPORT
Computer simulation of circuit performance using SPICE is
often a quick way to analyze the performance of the OPA847
in its intended application. This is particularly true for video
and RF amplifier circuits where parasitic capacitance and
inductance can play a major role in circuit performance. A
SPICE model for the OPA847 is available through the TI web
site (www.ti.com). These models do a good job of predicting
small-signal AC and transient performance under a wide
variety of operating conditions. They do not do as well in
predicting the harmonic distortion characteristics. These
models do not attempt to distinguish between the package
types in their small-signal AC performance.
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO MINIMIZE NOISE
The OPA847 provides a very low input noise voltage while
requiring a low 18.1mA of quiescent current. To take full
advantage of this low input noise, careful attention to the other
possible noise contributors is required. See Figure 12 for the
op amp noise analysis model with all the noise terms included.
In this model, all the noise terms are taken to be noise voltage
or current density terms in either nV/
Hz
or pA/
Hz
.
The total output spot noise voltage is computed as the
square root of the squared contributing terms to the output
noise power. This computation adds all the contributing noise
powers at the output by superposition, then takes the square
OPA847
16
SBOS251C
www.ti.com
practice, this only holds true when the phase margin ap-
proaches 90, as it does in high-gain configurations. At low
gains (increased feedback factors), most high-speed ampli-
fiers exhibit a more complex response with lower phase
margin. The OPA847 is compensated to give a maximally flat
2nd-order Butterworth closed-loop response at a noninverting
gain of +20 (see Figure 1). This results in a typical gain of
+20 bandwidth of 350MHz, far exceeding that predicted by
dividing the 3900MHz GBP by 20. Increasing the gain causes
the phase margin to approach 90 and the bandwidth to more
closely approach the predicted value of (GBP/NG). At a gain
of +50, the OPA847 very nearly matches the 78MHz band-
width predicted using the simple formula and the typical GBP
of 3900MHz.
Inverting operation offers some interesting opportunities to
increase the available GBP. When the source impedance is
matched by the gain resistor (see Figure 2), the signal gain
is (1 + R
F
/R
G
), while the noise gain for bandwidth purposes
is (1 + R
F
/2R
G
). This cuts the noise gain almost in half,
increasing the minimum operating gain for inverting opera-
tion under these condition to 22 and the equivalent gain
bandwidth product to > 7.8GHz.
DRIVING CAPACITIVE LOADS
One of the most demanding, and yet very common, load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC, including additional
external capacitance that may be recommended to improve
ADC linearity. A high-speed, high open-loop gain amplifier
like the OPA847 can be very susceptible to decreased
stability and may give closed-loop response peaking when a
capacitive load is placed directly on the output pin. When the
amplifier's open-loop output resistance is considered, this
capacitive load introduces an additional pole in the signal
path that can decrease the phase margin. Several external
solutions to this problem are suggested. When the primary
considerations are frequency response flatness, pulse re-
sponse fidelity, and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This does not
eliminate the pole from the loop response, but rather shifts it
and adds a zero at a higher frequency. The additional zero
acts to cancel the phase lag from the capacitive load pole,
thus increasing the phase margin and improving stability.
The Typical Characteristics help the designer pick a recom-
mended R
S
versus capacitive load. The resulting frequency
response curves show a flat response for several selected
capacitive loads and recommended R
S
combinations. Para-
sitic capacitive loads greater than 2pF can begin to degrade
the performance of the OPA847. Long PC board traces,
unmatched cables, and connections to multiple devices can
easily cause this value to be exceeded. Always consider this
effect carefully and add the recommended series resistor as
close as possible to the OPA847 output pin (see the Board
Layout section).
root to get back to a spot noise voltage. Equation 9 shows
the general form for this output noise voltage using the terms
illustrated in Figure 11.
(9)
E
O
= (E
2
NI
+ (I
BN
R
S
)
2
+ 4kTR
S
)NG
2
+ (I
BI
R
F
)
2
+ 4kTR
F
NG
Dividing this expression by the noise gain (NG = 1 + R
F
/R
G
)
gives the equivalent input referred spot noise voltage at the
noninverting input, as shown in Equation 10.
(10)
(
)
NG
kTR
4
NG
R
I
kTR
4
R
I
E
E
F
2
F
BI
S
2
S
BN
2
NI
N
+
+
+
+
=
Putting high resistor values into Equation 10 can quickly
dominate the total equivalent input referred noise. A 45
source impedance on the noninverting input adds a Johnson
voltage noise term equal to the amplifier's voltage noise by
itself. As a simplifying constraint, set R
G
= R
S
in Equation 10
and assume an R
S
/2 source impedance at the noninverting
input, where R
S
is the signal source impedance and another
matching R
S
to ground is at the noninverting input. This
results in Equation 11, where NG > 12 is assumed to further
simplify the expression.
(
)
+
+
=
2
R
3
kT
4
R
I
4
5
E
E
S
2
S
B
2
NI
N
(11)
Evaluating this expression for R
S
= 50
gives a total equiva-
lent input noise of 1.4nV/
Hz
. Note that at these higher
gains, the simplified input referred spot noise expression of
Equation 11 does not include the gain. This is a good
approximation for NG > 12, as is typically required by stability
considerations.
FREQUENCY RESPONSE CONTROL
Voltage-feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the Gain Bandwidth Product
(GBP) shown in the Electrical Characteristics. Ideally, divid-
ing GBP by the noninverting signal gain (also called the
Noise Gain, or NG) predicts the closed-loop bandwidth. In
FIGURE 12. Op Amp Noise Analysis Model.
4kT
R
G
R
G
R
F
R
S
OPA847
I
BI
E
O
I
BN
4kT = 1.6E 20J
at 290
K
E
RS
E
NI
4kTR
S
4kTR
F
OPA847
17
SBOS251C
www.ti.com
The criterion for setting the R
S
resistor is a maximum band-
width, flat frequency response at the load. For the OPA847
operating in a gain of +20, the frequency response at the
output pin is very flat to begin with, allowing relatively small
values of R
S
to be used for low capacitive loads. As the
signal gain is increased, the unloaded phase margin also
increases. Driving capacitive loads at higher gains requires
lower R
S
values than those shown for a gain of +20.
DISTORTION PERFORMANCE
The OPA847 is capable of delivering an exceptionally low
distortion signal at high frequencies over a wide range of
gains. The distortion plots in the Typical Characteristics show
the typical distortion under a wide variety of conditions. Most
of these plots are limited to a 110dB dynamic range. The
OPA847's distortion driving a 200
load does not rise above
90dBc until either the signal level exceeds 2.0V
PP
and/or
the fundamental frequency exceeds 5MHz. Distortion in the
audio band is < 130dBc.
Generally, until the fundamental signal reaches very high
frequencies or powers, the 2nd-harmonic dominates the dis-
tortion with a negligible 3rd-harmonic component. Focusing
then on the 2nd-harmonic, increasing the load impedance
improves distortion directly. Remember that the total load
includes the feedback network--in the noninverting configura-
tion this is the sum of R
F
+ R
G
, while in the inverting
configuration this is only R
F
(see Figure 2). Increasing the
output voltage swing increases harmonic distortion directly. A
6dB increase in output swing generally increases the 2nd-
harmonic 12dB and the 3rd-harmonic 18dB. Increasing the
signal gain also increases the 2nd-harmonic distortion. Finally,
the distortion increases as the fundamental frequency in-
creases due to the rolloff in the loop gain with frequency.
Conversely, the distortion improves going to lower frequencies
down to the dominant open-loop pole at approximately 80kHz.
The OPA847 has an extremely low 3rd-order harmonic
distortion. This also gives a high 2-tone 3rd-order
intermodulation intercept, as shown in the Typical Character-
istics. This intercept curve is defined at the 50
load when
driven through a 50
matching resistor to allow direct
comparisons to R
F
devices. This matching network attenu-
ates the voltage swing from the output pin to the load by 6dB.
If the OPA847 drives directly into the input of a high-
impedance device, such as an ADC, this 6dB attenuation is
not taken. Under these conditions, the intercept as reported
in the Typical Characteristics increases by a minimum of
6dBm. The intercept is used to predict the intermodulation
spurious power levels for two closely spaced frequencies. If
the two test frequencies, f
1
and f
2
, are specified in terms of
average and delta frequency, f
O
= (f
1
+ f
2
)/2 and
F
=
|f
2
f
1
| /2,
the two 3rd-order, close-in spurious tones appear at f
O
3
F
.
The difference between the two equal test-tone power levels
and these intermodulation spurious power levels is given by
dBc = 2(IM3 P
O
), where IM3 is the intercept taken from the
Typical Characteristics and P
O
is the power level in dBm at
the 50
load for one of the two closely spaced test frequen-
cies. For instance, at 30MHz, the OPA847 at a gain of +20
has an intercept of 34dBm at a matched 50
load.
If the full envelope of the two frequencies needs to be 2V
PP
,
this requires each tone to be 4dBm. The 3rd-order
intermodulation spurious tones will then be 2(34 4) =
60dBc below the test-tone power level (56dBm). If this
same 2V
PP
2-tone envelope is delivered directly into the
input of an ADC without the matching loss or the loading of
the 50
network, the intercept would increase to at least
40dBm. With the same signal and gain conditions, but now
driving directly into a light load, the spurious tones will then
be at least 2(40 4) = 72dBc below the 4dBm test-tone
power levels centered on 30MHz. Tests have shown that
they are in fact much lower due to the lighter loading
presented by most ADCs.
DC ACCURACY AND OFFSET CONTROL
The OPA847 can provide excellent DC signal accuracy due
to its high open-loop gain, high common-mode rejection, high
power-supply rejection, and low input offset voltage and bias
current offset errors. To take full advantage of its low 0.5mV
input offset voltage, careful attention to the input bias current
cancellation is also required. The low-noise input stage for
the OPA847 has a relatively high input bias current (19A
typical into the pins), but with a very close match between the
two input currents--typically 100nA input offset current.
Figures 13 and 14 show typical distributions of input offset
voltage and current for the OPA847.
FIGURE 13. Input Offset Voltage Distribution in V.
1200
1000
800
600
400
200
0
V
Count
< 600
< 540
< 480
< 420
< 360
< 300
< 240
< 180
< 120
< 60
0
< 60
< 120
< 180
< 240
< 300
< 360
< 420
< 480
< 540
< 600
> 600
Mean = 48
V
Standard Deviation = 110
V
Total Count = 4040
FIGURE 14. Input Offset Current Distribution in nA.
900
800
700
600
500
400
300
200
100
0
nA
Count
< 600
< 540
< 480
< 420
< 360
< 300
< 240
< 180
< 120
< 60
0
< 60
< 120
< 180
< 240
< 300
< 360
< 420
< 480
< 540
< 600
> 600
Mean = 50nA
Standard Deviation = 120nA
Total Count = 4040
OPA847
18
SBOS251C
www.ti.com
The total output offset voltage can be considerably reduced
by matching the source impedances looking out of the two
inputs. For example, one way to add bias current cancella-
tion to the circuit of Figure 1 is to insert a 12.1
series resistor
into the noninverting input from the 50
terminating resistor.
When the 50
source resistor is DC coupled, this increases
the source impedance for the noninverting input bias current
to 37.1
. Since this is now equal to the impedance looking
out of the inverting input (R
F
|| R
G
) for Figure 1, the circuit
cancels the gains for the bias currents to the output, leaving
only the offset current times the feedback resistor as a
residual DC error term at the output. Using the 750
feedback resistor, this output error is now less than
0.85A 750
= 640V over the full temperature range for
the circuit of Figure 1, with a 12.1
resistor added as de-
scribed. The output DC offset is then dominated by the
input offset voltage multiplied by the signal gain. For the
circuit of Figure 1, this is a worst-case output DC offset of
0.6mV 20 = 12mV over the full temperature range.
A fine-scale output offset null, or DC operating point adjust-
ment, is sometimes required. Numerous techniques are
available for introducing a DC offset control into an op amp
circuit. Most of these techniques eventually reduce to setting
up a DC current through the feedback resistor. One key
consideration to selecting a technique is to ensure that it has
a minimal impact on the desired signal path frequency
response. If the signal path is intended to be noninverting,
the offset control is best applied as an inverting summing
signal to avoid interaction with the signal source. If the signal
path is intended to be inverting, applying the offset control to
the noninverting input can be considered. For a DC-coupled
inverting input signal, this DC offset signal sets up a DC
current back into the source that must be considered. An
offset adjustment placed on the inverting op amp input can
also change the noise gain and frequency response flatness.
Figure 15 shows one example of an offset adjustment for a
DC-coupled signal path that has minimum impact on the
signal frequency response.
In this case, the input is brought into an inverting gain resistor
with the DC adjustment as an additional current summed
into the inverting node. The resistor values setting this offset
adjustment are much larger than the signal path resistors.
This ensures that this adjustment has minimal impact on the
loop gain and, hence, the frequency response.
POWER SHUTDOWN OPERATION
The OPA847 provides an optional power shutdown feature
that can be used to reduce system power. If the V
DIS
control
pin is left unconnected, the OPA847 operates normally. This
shutdown is intended only as a power saving feature. For-
ward path isolation is very good for small signals. Large
signal isolation is not ensured. Using this feature to multiplex
two or more outputs together is not recommended. Large
signals applied to the shutdown output stages can turn on
parasitic devices, degrading signal linearity for the desired
channel.
Turn-on time is very quick from the shutdown condition,
typically < 60ns. Turn-off time is strongly dependent on the
external circuit configuration, but is typically 200ns for the
circuit of Figure 1. Using the OPA847 with higher external
resistor values, such has high-gain transimpedance circuits,
slows the shutdown time since the time constants for the
internal nodes to discharge are longer.
To shutdown, the control pin must be asserted low. This logic
control is referenced to the positive supply, as shown in the
simplified circuit of Figure 16.
FIGURE 15. DC-Coupled, Inverting Gain of 20 with Output
Offset Adjustment.
R
F
1k
200mV Output Adjustment
Power-supply decoupling
not shown.
5k
5k
48
0.1
F
R
G
50
V
I
20k
100
0.1
F
5V
+5V
OPA847
+5V
5V
V
CC
V
EE
V
O
= = 20V/V
V
O
V
I
R
F
R
G
FIGURE 16. Simplified Shutdown Control Circuit.
17k
120k
8k
I
S
Control
V
S
+V
S
V
DIS
Q1
In normal operation, base current to Q1 is provided through
the 120k
resistor, while the emitter current through the 8k
resistor sets up a voltage drop that is inadequate to turn on
the two diodes in Q1's emitter. As V
DIS
is pulled low,
additional current is pulled through the 8k
resistor, even-
tually turning on these two diodes (
180A). At this point,
any further current pulled out of V
DIS
goes through those
diodes holding the emitter-base voltage of Q1 at approxi-
mately 0V. This shuts off the collector current out of Q1,
turning the amplifier off. The supply current in the shutdown
mode is only that required to operate the circuit of Figure 16.
OPA847
19
SBOS251C
www.ti.com
The shutdown feature for the OPA847 is a positive-supply
referenced, current-controlled interface. Open-collector (or
drain) interfaces are most effective, as long as the controlling
logic can sustain the resulting voltage (in open mode) that
appears at the V
DIS
pin. The V
DIS
pin voltage is one diode
below the positive supply voltage applied to the OPA847 if the
logic voltage is open. For voltage output logic interfaces, the
on/off voltage levels described in the Electrical Characteristics
apply only for a +5V supply. An open-drain interface is
recommended for a shutdown operation using a higher
positive supply and/or logic families with inadequate high-
level voltage swings.
THERMAL ANALYSIS
The OPA847 does not require heatsinking or airflow in most
applications. Maximum desired junction temperature sets the
maximum allowed internal power dissipation, as described
here. In no case should the maximum junction temperature
be allowed to exceed 150C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
JA
.
The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and additional power dissipated in the
output stage (P
DL
) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. P
DL
depends on the required
output signal and load but would, for a grounded resistive
load, be at a maximum when the output is fixed at a voltage
equal to half either supply voltage (for equal bipolar sup-
plies). Under this worst-case condition, P
DL
= V
S
2
/(4 R
L
),
where R
L
includes feedback network loading. This is the
absolute highest power that can be dissipated for a given R
L
.
All actual applications dissipate less power in the output
stage.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an
OPA847IDBV (SOT23-6 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85C and driving a grounded 100
load. Maximum inter-
nal power is:
P
D
= 10V 18.9mA + 5
2
/(4(100
|| 789
)) = 259mW
Maximum T
J
= +85C + (0.26W 150C/W) = 124C
All actual applications will operate at a lower junction tem-
perature than the 124C computed above. Compute your
actual output stage power to get an accurate estimate of
maximum junction temperature, or use the results shown
here as an absolute maximum.
BOARD LAYOUT
Achieving optimum performance with a high-frequency am-
plifier like the OPA847 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output and
inverting input pins can cause instability: on the noninverting
input, it can react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted capaci-
tance, create a window around the signal I/O pins in all of the
ground and power planes around these pins. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.
b) Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1F decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections should always be decoupled with these capaci-
tors. Larger (2.2F to 6.8F) decoupling capacitors, effective
at lower frequencies, should also be used on the main supply
pins. These can be placed somewhat further from the device
and can be shared among several devices in the same area
of the PC board.
c) Careful selection and placement of external compo-
nents preserves the high-frequency performance of the
OPA847. Use resistors that have low reactance at high
frequencies. Surface-mount resistors work best and allow a
tighter overall layout. Metal film and carbon composition
axially leaded resistors can also provide good high-fre-
quency performance. Again, keep their leads and PC board
trace length as short as possible. Never use wirewound type
resistors in a high-frequency application. Since the output pin
and inverting input pin are the most sensitive to parasitic
capacitance, always position the feedback and series output
resistor, if any, as close as possible to the output pin. Other
network components, such as noninverting input termination
resistors, should also be placed close to the package. Where
double-side component mounting is allowed, place the feed-
back resistor directly under the package on the other side of
the board between the output and inverting input pins. Even
with a low parasitic capacitance shunting the external resis-
tors, excessively high resistor values can create significant
time constants that can degrade performance. Good axial
metal film or surface-mount resistors have approximately
0.2pF in shunt with the resistor. For resistor values > 2.0k
,
this parasitic capacitance can add a pole and/or zero below
400MHz that can effect circuit operation. Keep resistor val-
ues as low as possible, consistent with load driving consid-
erations. It has been suggested here that a good starting
point for design would be to set R
G
to 39.2
. Doing this
automatically keeps the resistor noise terms low, and mini-
mizes the effect of their parasitic capacitance. Transimped-
ance applications can use much higher resistor values. The
compensation techniques described in this data sheet allow
excellent frequency response control, even with very high
feedback resistor values.
d) Connections to other wideband devices on the board
can be made with short, direct traces or through onboard
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R
S
from the
OPA847
20
SBOS251C
www.ti.com
plot of Recommended R
S
vs Capacitive Load. Low parasitic
capacitive loads (< 4pF) may not need an R
S
, since the
OPA847 is nominally compensated to operate with a 2pF
parasitic load. Higher parasitic capacitive loads without an
R
S
are allowed as the signal gain increases from +20V/V
(increasing the unloaded phase margin). If a long trace is
required, and the 6dB signal loss intrinsic to a doubly-
terminated transmission line is acceptable, implement a
matched impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50
environ-
ment is normally not necessary onboard and, in fact, a higher
impedance environment improves distortion, as shown in the
distortion versus load plots. With a characteristic board trace
impedance defined based on board material and trace di-
mensions, a matching series resistor into the trace from the
output of the OPA847 is used, as well as a terminating shunt
resistor at the input of the destination device. Remember
also that the terminating impedance is the parallel combina-
tion of the shunt resistor and the input impedance of the
destination device; this total effective impedance should be
set to match the trace impedance. If the 6dB attenuation of
a doubly-terminated transmission line is unacceptable, a
long trace can be series-terminated at the source-end only.
Treat the trace as a capacitive load in this case and set the
series resistor value as shown in the plot of Recommended
R
S
vs Capacitive Load. This does not preserve signal integ-
rity as well as a doubly-terminated line. If the input imped-
ance of the destination device is low, there will be some
signal attenuation due to the voltage divider formed by the
series output into the terminating impedance.
e) Socketing a high-speed part like the OPA847 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an ex-
tremely troublesome parasitic network that can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OPA847
onto the board.
INPUT AND ESD PROTECTION
The OPA847 is built using a very high-speed complementary
bipolar process. The internal junction breakdown voltages are
relatively low for these very small geometry devices. These
breakdowns are reflected in the Absolute Maximum Ratings
table. All device pins are protected with internal ESD protec-
tion diodes to the power supplies, as shown in Figure 17.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with 15V supply parts
driving into the OPA847), current limiting series resistors
should be added into the two inputs. Keep these resistor
values as low as possible, since high values degrade both
noise performance and frequency response.
FIGURE 17. Internal ESD Protection.
External
Pin
+V
CC
V
CC
Internal
Circuitry
OPA847
21
SBOS251C
www.ti.com
PACKAGE DRAWINGS
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN
(4,80)
0.189
0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1
4
8
5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0
8
Gage Plane
A
0.004 (0,10)
0.010 (0,25)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
OPA847
22
SBOS251C
www.ti.com
PACKAGE DRAWINGS
(Cont.)
DBV (R-PDSO-G6)
PLASTIC SMALL-OUTLINE
0,10
M
0,20
0,95
0 8
0,25
0,55
0,35
Gage Plane
0,15 NOM
4073253-5/G 01/02
2,60
3,00
0,50
0,25
1,50
1,70
4
6
3
1
2,80
3,00
1,45
0,95
0,05 MIN
Seating Plane
6X
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Leads 1, 2, 3 may be wider than leads 4, 5, 6 for package orientation.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright
2003, Texas Instruments Incorporated
PDF 
ZIP