Serial

Input

I/F

Mode

Control

I/F

8X Oversampling

Digital Filter with

Function

Controller

Crystal/OSC

XTI

SCK

XTO

CLKO

CC1

AGND1

DGND

Enhanced
Multi-level

Delta-Sigma

Modulator

OUT

CC2

AGND2L

EXTL

Open Drain

DAC

Low-pass

Filter

Low-pass

Filter

BPZ-Cont.

OUT

EXTR

ZERO

DAC

MC/DM1

ML/IIS

LRCIN

DIN

BCKIN

CS/IWO

MD/DM0

MODE

MUTE

RST

Power Supply

24-Bit, 96kHz Sampling

CMOS Delta-Sigma Stereo Audio

DIGITAL-TO-ANALOG CONVERTER

49%

FPO

International Airport Industrial Park · Mailing Address: PO Box 11400, Tucson, AZ 85734 · Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 · Tel: (520) 746-1111 · Twx: 910-952-1111

Internet: http://www.burr-brown.com/ · FAXLine: (800) 548-6133 (US/Canada Only) · Cable: BBRCORP · Telex: 066-6491 · FAX: (520) 889-1510 · Immediate Product Info: (800) 548-6132

PCM1716

DESCRIPTION

The PCM1716 is designed for Mid to High grade
Digital Audio applications which achieve 96kHz sam-
pling rates with 24-bit audio data. PCM1716 uses a
newly developed, enhanced multi-level delta-sigma
modulator architecture that improves audio dynamic
performance and reduces jitter sensitivity in actual
applications.

The internal digital filter operates at 8x over sampling
at a 96kHz sampling rate, with two kinds of roll-off
performances that can be selected: sharp roll-off, or
slow roll-off, as required for specific applications.

PCM1716 is suitable for Mid to High grade audio
applications such as CD, DVD-Audio, and Music
Instruments, since the device has superior audio
dynamic performance, 24-bit resolution and 96kHz
sampling.

FEATURES

ENHANCED MULTI-LEVEL DELTA-SIGMA DAC

SAMPLING FREQUENCY (f

): 16kHz - 96kHz

INPUT AUDIO DATA WORD:
16-, 20-, 24-Bit

HIGH PERFORMANCE:
THD+N: 96dB

Dynamic Range: 106dB

SNR: 106dB

Analog Output Range: 0.62 x V

(Vp-p)

8x OVERSAMPLING DIGITAL FILTER:
Stop Band Attenuation: 82dB
Passband Ripple:

0.002dB

Slow Roll Off

MULTI FUNCTIONS:
Digital De-emphasis

L/R Independent Digital Attenuation
Soft Mute
Zero Detect Mute
Zero Flag
Chip Select
Reversible Output Phase

+5V SINGLE SUPPLY OPERATION

SMALL 28-LEAD SSOP PACKAGE

PDS-1415C

Printed in U.S.A. August, 1998

PCM1716

PCM1716

SPECIFICATIONS

All specifications at +25

C, +V

= +V

= +5V, f

= 44.1kHz, and 24-bit input data, SYSCLK = 384f

, unless otherwise noted.

PCM1716

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

RESOLUTION

Bits

DATA FORMAT
Audio Data Interface Format

Standard/I

Data Bit Length

16/20/24 Selectable

Audio Data Format

MSB First, 2's Comp

Sampling Frequency (f

)

kHz

System Clock Frequency

(1)

256/384/512/768f

DIGITAL INPUT/OUTPUT LOGIC LEVEL
Input Logic Level

2.0

0.8

Output Logic Level (CLKO) V

= 2mA

4.5

= 4mA

0.5

CLKO PERFORMANCE

(2)

Output Rise Time

20 ~ 80% V

, 10pF

5.5

Output Fall Time

80 ~ 20% V

, 10pF

Output Duty Cycle

10pF Load

DYNAMIC PERFORMANCE

(3)

(24-Bit Data)

THD+N

= 0dB

= 44.1kHz

= 96kHz

= 60dB

= 44.1kHz

Dynamic Range

=44.1kHz EIAJ A-weighted

106

= 96kHz A-weighted

103

Signal-to-Noise Ratio

(4)

=44.1kHz EIAJ A-weighted

106

= 96kHz A-weighted

103

Channel Separation

= 44.1kHz

102

= 96kHz

101

DYNAMIC PERFORMANCE

(3)

(16-Bit Data)

THD+N

= 0dB

= 44.1kHz

= 96kHz

Dynamic Range

= 44.1kHz EIAJ A-weighted

= 96kHz A-weighted

DC ACCURACY
Gain Error

1.0

3.0

% of FSR

Gain Mismatch: Channel-to-Channel

1.0

3.0

% of FSR

Bipolar Zero Error

= 0.5V

at Bipolar Zero

ANALOG OUTPUT
Output Voltage

Full Scale (0dB)

0.62 V

Vp-p

Center Voltage

0.5 V

Load Impedance

AC Load

DIGITAL FILTER PERFORMANCE
Filter Characteristics 1
(Sharp Roll-Off)
Passband

0.002dB

0.454f

3dB

0.490f

Stopband

0.546f

Passband Ripple

0.002

Stopband Attenuation

Stop Band = 0.546f

Stop Band = 0.567f

Filter Characteristics 2
(Slow Roll-Off)
Passband

0.002dB

0.274f

3dB

0.454f

Stopband

0.732f

Passband Ripple

0.002

Stopband Attenuation

Stopband = 0.732f

Delay Time

30/f

sec

De-emphasis Error

0.1

INTERNAL ANALOG FILTER
3dB Bandwidth

100

kHz

Passband Response

f = 20kHz

0.16

POWER SUPPLY REQUIREMENTS
Voltage Range

DD,

4.5

5.5

VDC

Supply Current: I

= 44.1kHz

= 96kHz

Power Dissipation

= 44.1kHz

160

225

= 96kHz

225

TEMPERATURE RANGE
Operation

+85

Storage

+100

NOTES: (1) Refer section of system clock. (2) External buffer is recommended. (3) Dynamic performance specs are tested with 20kHz low pass filter and THD+N
specs are tested with 30kHz LPF, 400Hz HPF, Average Mode. (4) SNR is tested at internally infinity zero detection off.

PCM1716

PIN

NAME

I/O

DESCRIPTION

LRCIN

Left and Right Clock Input. This clock is equal to
the sampling rate - f

(1)

DIN

Serial Audio Data Input

(1)

BCKIN

Bit Clock Input for Serial Audio Data.

(1)

CLKO

OUT

Buffered Output of Oscillator. Equivalent to
System Clock.

XTI

Oscillator Input (External Clock Input)

XTO

OUT

Oscillator Output

DGND

Digital Ground

Digital Power +5V

Analog Power +5V

AGND2R

Analog Ground

EXTR

OUT

Rch, Common Pin of Analog Output Amp

No Connection

OUT

Rch, Analog Voltage Output of Audio Signal

AGND1

Analog Ground

Analog Power +5V

OUT

Lch, Analog Voltage Output of Audio Signal

No Connection

EXTL

OUT

Lch, Common Pin of Analog Output Amp

AGND2L

Analog Ground

Analog Power +5V

ZERO

OUT

Zero Data Flag

RST

Reset. When this pin is low, the DF and
modulators are held in reset.

(2)

CS/IWO

Chip Select/Input Format Selection. When this
pin is low, the Mode Control is effective.

(3)

MODE

Mode Control Select. (H: Software, L: Hardware)

(2)

MUTE

Mute Control

MD/DM0

Mode Control, DATA/De-emphasis Selection 1

(2)

MC/DM1

Mode Control, BCK/De-emphasis Selection 2

(2)

ML/I

Mode Control, WDCK/Input Format Selection

(2)

NOTES: (1) Pins 1, 2, 3; Schmitt Trigger input. (2) Pins 22, 24, 25, 26, 27,
28; Schmitt Trigger input with pull-up resister. (3) Pin 23; Schmitt Trigger
input with pull-down resister.

PIN ASSIGNMENTS

PIN CONFIGURATION

LRCIN

DIN

BCKIN

CLKO

XTI

XTO

DGND

AGND2R

EXTR

OUT

AGND1

ML/IIS

MC/DM1

MD/DM0

MUTE

MODE

CS/IWO

RST

ZERO

AGND2L

EXTL

OUT

PCM1716E

PACKAGE DRAWING

PRODUCT

PACKAGE

NUMBER

(1)

PCM1716E

28-Pin SSOP

324

NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.

PACKAGE INFORMATION

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

Power Supply Voltage ...................................................................... +6.5V
+V

to +V

Difference ...................................................................

0.1V

Input Logic Voltage .................................................. 0.3V to (V

+ 0.3V)

Input Current (except power supply) ...............................................

10mA

Power Dissipation .......................................................................... 400mW
Operating Temperature Range ......................................... 25

C to +85

Storage Temperature ...................................................... 55

C to +125

Lead Temperature (soldering, 5s) ................................................. +260

ABSOLUTE MAXIMUM RATINGS

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

PCM1716

60dB OUTPUT SPECTRUM

(f = 1kHz, f

= 44.1kHz, 24-Bit Data)

Frequency (Hz)

Amplitude (dB)

100

110

120

130

140

150

60dB OUTPUT SPECTRUM

(f = 1kHz, f

= 44.1kHz, 16-Bit Data)

Frequency (Hz)

Amplitude (dB)

100

110

120

130

140

150

TYPICAL PERFORMANCE CURVES

All specifications at +25

C, +V

= +V

= +5V, f

= 44.1kHz, and 24-bit input data, SYSCLK = 384f

, unless otherwise noted.

THD+N vs SAMPLING FREQUENCY

= V

= 5V, 24-Bit)

Sampling Frequency f

(kHz)

THD+N at F/S (dB)

100

103

44.1

256fs

384fs

DYNAMIC RANGE vs SAMPLING FREQUENCY

= V

= 5V, 24-Bit)

Sampling Frequency f

(kHz)

Dynamic Range (A-weighted) (dB)

110

108

106

104

102

100

44.1

256/384f

THD+N vs LEVEL

= 44.1kHz)

Amplitude (dB)

THD+N (%)

0.1

0.010

0.001

THD+N (dB)

100

16-Bit

24-Bit

SNR vs SAMPLING FREQUENCY

= V

= 5V, 24-Bit)

Sampling Frequency f

(kHz)

SNR (A-weighted) (dB)

110

108

106

104

102

100

44.1

256/384f

PCM1716

0.5

1.5

2.5

3.5

100

120

140

Amplitude (dB)

OVERALL FREQUENCY CHARACTERISTIC

(Slow Roll-Off)

Frequency (x f

)

0.5

1.5

2.5

3.5

100

120

140

160

Amplitude (dB)

OVERALL FREQUENCY CHARACTERISTIC

(Sharp Roll-Off)

Frequency (x f

)

TYPICAL PERFORMANCE CURVES

(CONT)

0.1

0.2

0.3

0.4

0.5

0.6

Amplitude (dB)

FREQUENCY CHARACTERISTIC

(Slow Roll-Off)

Frequency (x f

)

0.1

0.2

0.3

0.4

0.5

0.003

0.002

0.001

0.002

0.003

Amplitude (dB)

PASSBAND RIPPLE CHARACTERISTIC

(Sharp Roll-Off)

Frequency (x f

)

DE-EMPHASIS FREQUENCY RESPONSE (f

= 32kHz)

Frequency (kHz)

2
4
6
8

Level (dB)

DE-EMPHASIS FREQUENCY RESPONSE (f

= 48kHz)

Frequency (kHz)

2
4
6
8

Level (dB)

DE-EMPHASIS FREQUENCY RESPONSE (f

= 44.1kHz)

Frequency (kHz)

2
4
6
8

Level (dB)

DE-EMPHASIS ERROR (f

= 32kHz)

Frequency (kHz)

0.5
0.3
0.1

0.1
0.3
0.5

0.5
0.3
0.1

0.1
0.3
0.5

0.5
0.3
0.1

0.1
0.3
0.5

Level (dB)

DE-EMPHASIS ERR0R (f

= 48kHz)

Frequency (kHz)

Level (dB)

DE-EMPHASIS ERROR (f

= 44.1kHz)

Frequency (kHz)

Level (dB)

PCM1716

SYSTEM CLOCK

The system clock for PCM1716 must be either 256f

, 384f

512f

or 768f

, where f

is the audio sampling frequency

(typically 32kHz, 44.1kHz, 48kHz, or 96kHz). But 768f

96kHz is not accepted.

The system clock can be either a crystal oscillator placed
between XTI (pin 5) and XTO (pin 6), or an external clock
input to XTI. If an external system clock is used, XTO is
open (floating). Figure 1 illustrates the typical system clock
connections.

PCM1716 has a system clock detection circuit which auto-
matically senses if the system clock is operating at 256f

768f

. The system clock should be synchronized with LRCIN

(pin 1) clock. LRCIN (left-right clock) operates at the sam-
pling frequency f

. In the event these clocks are not synchro-

nized, PCM1716 can compensate for the phase difference
internally. If the phase difference between left-right and
system clocks is greater than 6-bit clocks (BCKIN), the
synchronization is performed internally. While the synchro-
nization is processing, the analog output is forced to a DC
level at bipolar zero. The synchronization typically occurs in
less than 1 cycle of LRCIN.

SYSTEM CLOCK FREQUENCY - MHz

SAMPLING RATE FREQUENCY (f

) - LRCIN

256f

384f

512f

768f

32kHz

8.1920

12.2880

16.3840

24.5760

44.1kHz

11.2896

16.9340

22.5792

33.8688

(1)

48kHz

12.2880

18.4320

24.5760

36.8640

(1)

96kHz

24.5760

36.8640

(1)

49.1520

(1)

NOTE: (1) The Internal Crystal oscillator frequency cannot be larger than 24.576MHz.

TABLE I. Typical System Clock Frequency.

Typical input system clock frequencies to the PCM1716 are
shown in Table I, also, external input clock timing require-
ments are shown in Figure 2.

FIGURE 1. System Clock Connection.

FIGURE 2. XTI Clock Timing.

SCKH

System Clock Pulse Width High t

SCKIH

: 7ns MIN

System Clock Pulse Width Low t

SCKIL

: 7ns MIN

SCKL

2.0V

0.8V

"H"

"L"

XTI

DATA INTERFACE FORMATS

Digital audio data is interfaced to PCM1716 on pins 1, 2,
and 3, LRCIN (left-right clock), DIN (data input) and
BCKIN (bit clock). PCM1716 can accept both standard, I

and left justified data formats.

Figure 3 illustrates acceptable input data formats. Figure 4
shows required timing specification for digital audio data.

Reset

PCM1716 has both internal power-on reset circuit and the
RST pin (pin 22) which accepts an external forced reset by
RST = LOW. For internal power on reset, initialize (reset) is
done automatically at power on V

>2.2V (typ). During

internal reset = LOW, the output of the DAC is invalid and
the analog outputs are forced to V

/2. Figure 5 illustrates

the timing of the internal power on reset.

PCM1716 accepts an external forced reset when RST = L.
When RST = L, the output of the DAC is invalid and the
analog outputs are forced to V

/2 after internal initialization

(1024 system clocks count after RST = H.) Figure 6 illustrates
the timing of the RST pin.

Zero Out (pin 21)

If the input data is continuously zero for 65536 cycles of
BCK, an internal FET is switched to "ON". The drain of the
internal FET is the zero-pin, it will enable "wired-or" with
external circuit. This zero detect function is available in both
software mode and hardware mode.

System Clock

(256/384/

512/768f

)

Externl Clock Input

CLKO

XTI

XTO

PCM1716

System Clock

Buffer Out

Crystal Resonator Oscillation

CLKO

XTI

XTO

PCM1716

XTAL

: 10pF ~ 30pF

Buffer

PCM1716

1/f

L_ch

R_ch

MSB

LSB

LRCIN (pin 1)

BCKIN (pin 3)

(1) 16-Bit Right Justified

DIN (pin 2)

MSB

LSB

MSB

LSB

(2) 20-Bit Right Justified

DIN (pin 2)

MSB

LSB

MSB

LSB

(3) 24-Bit Right Justified

DIN (pin 2)

(4) 24-Bit Left Justified

DIN (pin 2)

MSB

LSB

MSB

LSB

MSB

LSB

1/f

L_ch

R_ch

MSB

LSB

LRCIN (pin 1)

BCKIN (pin 3)

(5) 16-Bit I

DIN (pin 2)

MSB

LSB

MSB

LSB

(6) 24-Bit I

DIN (pin 2)

MSB

LSB

FIGURE 3. Audio Data Input Formats.

LRCKIN

BCKIN

DIN

1.4V

BCH

BCL

BCKIN Pulse Cycle Time

BCKIN Pulse Width High

BCKIN Pulse Width Low

BCKIN Rising Edge to LRCIN Edge

LRCIN Edge to BCKIN Rising Edge

DIN Set-up Time

DIN Hold Time

: t

BCY

: t

BCH

: t

BCL

: t

: 100ns (min)

: 50ns (min)

: 30ns (min)

BCY

FIGURE 4. Audio Data Input Timing Specification.

PCM1716

1024 system (XTI) clocks

Reset

Reset Removal

XTI Clock

Internal Reset

RST

(1)

NOTE: (1) t

RST

= 20ns min.

1024 system (= XTI) clocks

Reset

Reset Removal

= V

Internal Reset

XTI Clock

FIGURE 5. Internal Power-On Reset Timing.

FUNCTIONAL DESCRIPTION

PCM1716 has several built-in functions including digital
attenuation, digital de-emphasis, input data format selection,
and others. These functions are software controlled. PCM1716
can be operated in two different modes, software mode or
hardware mode. Software mode is a three-wire interface
using pin 28 (ML), 27 (MC), and 26 (MD).

PCM1716 can also be operated in hardware mode, where
static control signals are used on pin 28 (115, pin 27 (DM1),
pin 26 (DM0) and pin 23 (IWO).

This basic operation mode as software or hardware can be
selected by pin 24 (MODE) as shown in Table II.

MODE (pin 24) = H

Software Mode

MODE (pin 24) = L

Hardware Mode

TABLE II. Mode Control.

Table III indicates which functions are selectable within the
users chosen mode. All of the functions shown are selectable
within the software mode, but only de-emphasis control, soft
mute and input data format may be selected when using
PCM1716 in the hardware mode.

SOFTWARE

HARDWARE

FUNCTION

(Mode = H)

(Mode = L)

Input Data Format Selection

Input Data Bit Selection

Input LRCIN Polarity Selection

De-emphasis Control

Mute

Attenuation

Infinity Zero Mute Control

DAC Operation Control

Slow Roll-Off Selection

Output Phase Selection

CLKO Output Selection

NOTE: O = Selectable, X: Not Selectable.

TABLE III. Mode Control, Selectable Functions.

HARDWARE MODE (MODE = L)

In hardware mode, the following function can be selected.

De-emphasis control

De-emphasis control can be selected by DM1 (pin 27) and
DM0 (pin 26)

FIGURE 6. External Forced Reset Timing.

PCM1716

Input Audio Data Format

Input data format can be selected by I

S (pin 28) and IWO

(pin 23)

DM1 (Pin 27)

DM0 (Pin 26)

DE-EMPHASIS

OFF

48kHz

44.1kHz

32kHz

TABLE IV. De-emphasis Control.

S (Pin 28)

IWO (Pin 23)

DATA FORMAT

16-Bit Data Word, Normal, Right Justified

20-Bit Data Word, Normal, Right Justified

16-Bit Data Word, I

S Format

24-Bit Data Word, I

S Format

TABLE V. Data Format Control.

SOFT MUTE

Soft Mute function can be controlled by MUTE (pin 25)

SOFTWARE MODE (MODE = H)

PCM1716's special functions at software mode is shown in
Table VI. These functions are controlled using a ML, MC,
MD serial control signal.

MUTE (Pin 25)

SOFT MUTE

Mute ON

Mute OFF (Normal Operation)

FUNCTION

DEFAULT MODE

Input Audio Data Format Selection

Standard Format
Left Justified

Standard Format

S Format

Input Audio Data Bit Selection

16-Bit

20-Bit
24-Bit

Input LRCIN Polarity Selection

Lch/Rch = High/Low

Lch/Rch = Low/High

De-emphasis Control

OFF

Soft Mute Control

OFF

Attenuation Control

Lch, Rch Individually

0dB, Individual

Lch, Rch Common

Infinite Zero Mute Control

Not Operated

DAC Operation Control

Operated

Sampling Rate Selection for De-emphasis

Standard Frequency
44.1kHz

44.1kHz

48kHz
32kHz

Slow Roll-Off Selection

Not Selected

(Sharp Roll-Off)

Output Phase Selection

Not Inverted

CLK0 Output Selection

Input Frequency

TABLE VI. Selectable Functions and Default.

PROGRAM REGISTER BIT MAPPING

PCM1716's special functions are controlled using four pro-
gram registers which are 16 bits long. These registers are all
loaded using MD. After the 16 data bits are clocked in, ML
is used to latch in the data to the appropriate register. Table
VII shows the complete mapping of the four registers and
Figure 7 illustrates the serial interface timing.

MAPPING OF PROGRAM REGISTERS

B15

B14

B13

B12

B11

B10

MODE0

res

LDL

AL7

AL6

AL5

AL4

AL3

AL2

AL1

AL0

MODE1

res

LDR

AR7

AR6

AR5

AR4

AR3

AR2

AR1

AR0

MODE2

res

IW1

IW0

OPE

DEM

MUT

MODE3

res

IZD

SF1

SF0

CK0

REV

SR0

ATC

LRP

FIGURE 7. Three-Wire Serial Interface.

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

ML (pin 28)

MC (pin 27)

MD (pin 26)

PCM1716

REGISTER

BIT

NAME

DESCRIPTION

AL (7:0)

DAC Attenuation Data for Lch

LDL

Attenuation Data Load Control for Lch

A (1:0)

res

Reserved, should be "L"

AR (7:0)

DAC Attenuation Data for Rch

LDR

Attenuation Data Load Control for Rch

A (1:0)

res

Reserved, should be "L"

MUT

Left and Right DACs Soft Mute Control

DEM

De-emphasis Control

OPE

Left and Right DACs Operation Control

IW (1:0)

Input Audio Data Bit and Format Select

res

Reserved

A (1:0)

res

Reserved, should be "L"

Audio Data Format Select

LRP

Polarity of LRCIN Select

ATC

Attenuator Control

SRO

Slow Roll-Off Select

REV

Output Phase Select

CKO

CLKO Output Select

SF (1:0)

Sampling Rate Select

IZD

Internal Zero Detection Circuit Control

A (1:0)

res

Reserved, should be "L"

TABLE VII. Register Functions

REGISTER 0 (A1 = 0, A0 = 0)

B15 B14 B13 B12 B11 B10 B9 B8

B7 B6

B4 B3

B1 B0

res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0

Register 0 is used to control left channel attenuation. Bits
0 - 7 (AL0 - AL7) are used to determine the attenuation
level. The level of attenuation is given by:

ATT = 0.5 x (data-255) (dB)

FFh = 0dB

FEh = 0.5dB

:
:

01h = 127.5dB

00h =

(= Mute)

ATTENUATION DATA LOAD CONTROL

Bit 8 (LDL) is used to control the loading of attenuation data
in B0:B7. When LDL is set to 0, attenuation data will be
loaded into AL0:AL7, but it will not affect the attenuation
level until LDL is set to 1. LDR in Register 1 has the same
function for right channel attenuation.

REGISTER 1 (A1 = 0, A0 = 1)

B15 B14 B13 B12 B11 B10 B9 B8

B7 B6

B4 B3

B1 B0

res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0

Register 1 is used to control right channel attenuation. As
in Register 1, bits 0 - 7 (AR0 - AR7) control the level of
attenuation.

Register 2 is used to control soft mute, de-emphasis, opera-
tion enable, input resolution, and input audio data bit and
format.

REGISTER 2 (A1 = 1, A0 = 0)

B15 B14 B13 B12 B11 B10 B9 B8

B7 B6

B4 B3

res res res res res A1 A0 res

res res res IW1 IWO OPE DEM MUTE

when OPE (B2) is "HIGH", the output of the DAC will be
forced to bipolar zero, irrespective of any input data.

IWO (B3), IW1 (B4) and I

S (B0) of Register 3

These resisters, IWO, IW1, I

S determine the input data

word and input data format as shown below.

IW1

IW0

Audio Interface

16-Bit Standard (Right-Justified)

20-Bit Standard (Right-Justified)

24-Bit Standard (Right-Justified)

24-Bit Left-Justified (MSB First)

16-Bit I

24-Bit I

Reserved

REGISTER 3 (A1 = 1, A0 = 1)

B15 B14 B13 B12 B11 B10 B9 B8

B7 B6

B4 B3

res res res res res A1 A0 IZD

SF1 SF0 CKO REV SRO ATC LRP I

REGISTER 3 (A1 = 1, A0 = 1)

Register 3 is used to control input data format and polarity,
attenuation channel control, system clock frequency, sam-
pling frequency, infinite zero detection, output phase,
CLKO output, and slow roll-off.

Bit 8 is used to control the infinite zero detection function
(IZD).

When IZD is "LOW", the zero detect circuit is off. Under
this condition, no automatic muting will occur if the input
is continuously zero. When IZD is "HIGH", the zero detect
feature is enabled. If the input data is continuously zero for
65, 536 cycles of BCKIN, the output will be immediately

MUT (B0)

MUT = L

Soft Mute OFF

MUT = H

Soft Mute ON

OPE (B2)

OPE = L

Normal Operation

OPE = H

DAC Operation OFF

DEM (B1)

DEM = L

De-emphasis OFF

DEM = H

De-emphasis ON

PCM1716

forced to a bipolar zero state (V

/ 2). The zero detection

feature is used to avoid noise which may occur when the
input is DC. When the output is forced to bipolar zero,
there may be an audible click. PCM1716 allows the zero
detect feature to be disabled so the user can implement an
external muting circuit.

SRO (B3) is roll-off performance of digital filter selection.

SRO = L

Sharp Roll-Off

SRO = H

Slow Roll-Off

ATC (B2) is used as an attenuation control. When bit 3 is
set HIGH, the attenuation data on Register 0 is used for
both channels, and the data in Register 1 is ignored. When
bit 3 is LOW, each channel has separate attenuation data.

ATC = L

Ch Individual ATT Control

ATC = H

Common ATT Control

Bits 0 (I

S) and 1 (LRP) are used to control the input data

format. A "LOW" on bit 0 sets the format to (MSB-first,
right-justified Japanese format) and a "HIGH" sets the
format to I

S (Philips serial data protocol). Bit 1 (LRP) is

used to select the polarity of LRCIN (sample rate clock).
When bit 1 is "LOW", left channel data is assumed when
LRCIN is in a "HIGH" phase and right channel data is
assumed when LRCIN is in a "LOW" phase. When bit 1 is
"HIGH", the polarity assumption is reversed.

LRP = L

H/Lch

LRP = H

L/Lch

FIGURE 8. Program Register Input Timing.

IZD (B8)

B8 = L

Zero Detect Mute OFF

B8 = H

Zero Detect Mute ON

Bits 6 (SF0) and 7 (SF1) are used to select the sampling
frequency for De-emphasis.

SF1

SF0

Sampling Rate

Reserved

48kHz

44.1kHz

32kHz

CKO (B5) is output frequency control at CLKO pin, can be
selected as Buffer (1/1) or half rate of input frequency
(1/2).

CKO = L

Buffer Out of XTi Clock

CKO = H

Half (1/2) Frequency Out of XTi Clock

REF (B4) is output analog signal phase control.

REV = L

Normal Output

REV = H

Inverted Output

1.4V

MLH

MCH

MCL

MDS

MCY

MLS

MLL

MHH

1.4V

CSML

MLCS

MDH

LSB

MC Pulse Cycle Time

MC Pulse Width LOW

MC Pulse Width HIGH

MD Hold Time

MD Set-up Time

ML Low Level Time

ML High Level Time

ML Hold Time

ML Set-up Time

CS Low to ML Low Time

(2)

ML High to CS High Time

(2)

NOTE: (1) System Clock Cycle. (2) CS Should be changed during ML = H.

: t

MCY

: t

MCL

: t

MCH

: t

MDH

: t

MDS

: t

MLL

: t

MHH

: t

MLH

: t

MLS

: t

CSML

: t

MLCS

: 100ns (min)

: 40ns (min)

: 40ns (min) + 1SYSCLK

(1)

(min)

: 40ns (min) + 1SYSCLK

(1)

(min)

: 40ns (min)

: 10ns (min)

PCM1716

THEORY OF OPERATION

The delta-sigma section of PCM1716 is based on a 8-level
amplitude quantizer and a 4th-order noise shaper. This
section converts the oversampled input data to 8-level delta-
sigma format.

This newly developed, "Enhanced Multi-level Delta-Sigma"
architecture achieves high-grade audio dynamic performance
and sound quality.

A block diagram of the 8-level delta-sigma modulator is
shown in Figure 9. This 8-level delta-sigma modulator has

the advantage of stability and clock jitter sensitivity over the
typical one-bit (2 level) delta-sigma modulator.

The combined oversampling rate of the delta-sigma modu-
lator and the internal 8-times interpolation filter is 64f

for

all system clock ratios (256/384/512/768f

The theoretical quantization noise performance of the
8-level delta-sigma modulator is shown in Figure 10. This
enhanced multi-level delta-sigma architecture also has ad-
vantages for input clock jitter sensitivity due to the multi-
level quantizer, simulated jitter sensitivity is shown in
Figure 11.

8-Level Quantizer

FIGURE 9. 8-Level Delta-Sigma Modulator.

100

120

140

160

180

Amplitude (dB)

Frequency (f

)

FIGURE 10. Quantization Noise Spectrum.

FIGURE 11. Jitter Sensitivity.

100

200

300

400

500

600

125

120

115

110

105

100

Dynamic Range (dB)

Jitter (ps)

CLOCK JITTER

PCM1716

APPLICATION
CONSIDERATIONS

DELAY TIME

There is a finite delay time in delta-sigma converters. In A/D
converters, this is commonly referred to as latency. For a
delta-sigma D/A converter, delay time is determined by the
order number of the FIR filter stage, and the chosen sampling
rate. The following equation expresses the delay time of
PCM1716:

= 30

1/f

For f

= 44.1kHz, T

= 30/44.1kHz = 680

Applications using data from a disc or tape source, such as
CD audio, DVD audio, Video CD, DAT, Minidisc, etc.,
generally are not affected by delay time. For some profes-
sional applications such as broadcast audio for studios, it is
important for total delay time to be less than 2ms.

OUTPUT FILTERING

For testing purposes all dynamic tests are done on the
PCM1716 using a 20kHz low pass filter. This filter limits
the measured bandwidth for THD+N, etc. to 20kHz. Failure
to use such a filter will result in higher THD+N and lower
SNR and Dynamic Range readings than are found in the
specifications. The low pass filter removes out of band
noise. Although it is not audible, it may affect dynamic
specification numbers.

The performance of the internal low pass filter from DC to
40kHz is shown in Figure 12. The higher frequency roll-off
of the filter is shown in Figure 13. If the user's application
has the PCM1716 driving a wideband amplifier, it is recom-
mended to use an external low pass filter.

BYPASSING POWER SUPPLIES

The power supplies should be bypassed as close as possible
to the unit. Refer to Figure 15 for optimal values of bypass
capacitors.

POWER SUPPLY
CONNECTIONS

PCM1716 has three power supply connections: digital (V

and analog (V

). Each connection also has a separate

ground. If the power supplies turn on at different times, there
is a possibility of a latch-up condition. To avoid this condi-
tion, it is recommended to have a common connection
between the digital and analog power supplies. If separate
supplies are used without a common connection, the delta
between the two supplies during ramp-up time must be less
than 0.1V.

An application circuit to avoid a latch-up condition is shown
in Figure 14.

FIGURE 12. Low Pass Filter Response.

100

10k

100k

0.5

Level (dB)

Log Frequency (Hz)

FIGURE 13. Low Pass Filter Response.

100

10k

100k

10M

100

Level (dB)

Log Frequency (Hz)

FIGURE 14. Latch-Up Prevention Circuit.

DGND

AGND

Digital

Power Supply

Analog

Power Supply

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: PCM1716