2006 California Micro Devices Corp. All rights reserved.
03/15/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.cmd.com
1
CM1230
PRELIMINARY
2, 4 and 8-Channel Low Capacitance ESD Protection Array
Features
2, 4 and 8 channels of ESD protection
Provides
ESD protection to IEC61000-4-2 Level 4
8kV contact discharge
15kV air discharge
Low loading capacitance of 0.8pF typical
Minimal capacitance change with temperature and
voltage
Channel I/O to GND capacitance difference of
0.02pF typical is ideal for differential signals
Channel I/O to I/O capacitance 0.15pF typical
Zener diode protects supply rail and eliminates the
need for external by-pass capacitors
Each I/O pin can withstand over 1000 ESD strikes
Available in 4, 6 and 10 bump Chip Scale Pack-
ages (CSP)
OptiGuard
TM
coated for improved reliability at
assembly
Lead-free version available
Applications
LCD and Camera data lines in wireless handsets
that use high-speed serial interfaces.
I/O port protection for mobile handsets, notebook
computers, DSCs, MP3 players, PDAs, etc. includ-
ing USB, 1394 and Serial ATA
Wireless handsets
Handheld PCs/PDAs
LCD and camera modules
Product Description
The CM1230 is a family of 2, 4 and 8 channel, very low
capacitance ESD protection diode arrays in CSP form
factor. This device is ideal for protecting systems with
high data and clock rates or for circuits that require low
capacitive loading. Each channel consists of a pair of
ESD diodes that act as clamp diodes that steer positive
or negative ESD current pulses to either the positive or
negative supply rail. A zener diode is integrated into
the array between the positive and negative supply
rails. The V
CC
rail is thus protected from ESD strikes
and eliminates the need for a bypass capacitor to
absorb positive ESD strikes to ground. Each channel
of the CM1230 can safely dissipate ESD strikes of
8kV, meeting the Level 4 requirement of the
IEC61000-4-2 international standard for contact dis-
charges as well as
15kV air discharges per the
IEC61000-4-2 specification. Using the MIL-STD-883
(Method 3015) specification for Human Body Model
(HBM) ESD, the pins are protected for contact dis-
charges at greater than
15kV.
This device is particularly well-suited for next genera-
tion wireless handsets that implement high-speed
serial interface solutions for the LCD display and cam-
era interfaces. In these wireless handset designs, a
tolerance above 1.5pF cannot be tolerated due to the
high data rates that are transferred between the base-
band chipset and the LCD driver/controller ICs
because a higher capacitive loading will cause the rise
and fall times to slow which in turn hampers the func-
tionality of circuit and operation of the wireless hand-
set.
The CM1230 incorporates OptiGuard
TM
which results
in improved reliability at assembly. The CM1230 is
available in a space-saving, low profile Chip Scale
Package with optional lead-free finishing.
Electrical Schematic
CH1
V
P
V
N
CM1230-04CS/CP
CH4
CH2
CH3
CH1
V
P
V
N
CM1230-02CS/CP
CH2
CH3
CH6
CH4
CH5
CH1
CM1230-08CS/CP
CH8
CH2
CH7
V
P
V
N
2006 California Micro Devices Corp. All rights reserved.
2
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.cmd.com
03/15/06
CM1230
PRELIMINARY
Ordering Information
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Note 2: Lead-free devices are specified by using a "
+
" character for the top side orientation mark.
2
1
B
A
L308
Orientation
Marking
(see note 2)
4
5
3
B5
B4
A4
A5
B3
B2
A2
B1
A1
A3
Orientation
Marking
A1
2
1
B
A
L30
Orientation
Marking
(see note 2)
3
B3
A3
B2
B1
A1
A2
Orientation
Marking
A1
2
1
B
A
L
Orientation
Marking
(see note 2)
PACKAGE / PINOUT DIAGRAMS
Notes:
B2
B1
A1
A2
Orientation
Marking
A1
CM1230-02
TOP VIEW
BOTTOM VIEW
(Bumps Down View)
(Bumps Up View)
4-Bump CSP Package
2) Lead-free devices are specified by using a "+" character for the top side orientation mark.
1) These drawings are not to scale.
CM1230-04
6-Bump CSP Package
CM1230-08
10-Bump CSP Package
PART NUMBERING INFORMATION
Standard Finish
Lead-free Finish
2
# of Channels
Bumps
Package
Ordering Part
Number
1
Part Marking
Ordering Part
Number
1
Part Marking
2
4
CSP-4
CM1230-02CS
L
CM1230-02CP
L
4
6
CSP-6
CM1230-04CS
L30
CM1230-04CP
L30
8
10
CSP-10
CM1230-08CS
L308
CM1230-08CP
L308
2006 California Micro Devices Corp. All rights reserved.
03/15/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.cmd.com
3
CM1230
PRELIMINARY
Pin Descriptions
PIN DESCRIPTIONS
PIN DESCRIPTIONS (CONT'D)
2-CHANNEL, 4-BUMP CSP
8-CHANNEL, 10-BUMP CSP
PIN NAME
TYPE
DESCRIPTION
PIN NAME
TYPE
DESCRIPTION
A1
V
N
GND
Negative voltage supply rail
A1
CH1
I/O
ESD Channel
B1
CH2
I/O
ESD Channel
B1
CH2
I/O
ESD Channel
A2
CH1
I/O
ESD Channel
A2
CH3
I/O
ESD Channel
B2
V
P
PWR
Positive voltage supply rail
B2
CH4
I/O
ESD Channel
4-CHANNEL, 6-BUMP CSP
A3
V
P
PWR
Positive voltage supply rail
PIN NAME
TYPE
DESCRIPTION
B3
V
N
GND
Negative voltage supply rail
A1
CH1
I/O
ESD Channel
A4
CH5
I/O
ESD Channel
B1
CH2
I/O
ESD Channel
B4
CH6
I/O
ESD Channel
A2
V
P
PWR
Positive voltage supply rail
A5
CH7
I/O
ESD Channel
B2
V
N
GND
Negative voltage supply rail
B5
CH8
I/O
ESD Channel
A3
CH3
I/O
ESD Channel
B3
CH4
I/O
ESD Channel
2006 California Micro Devices Corp. All rights reserved.
4
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.cmd.com
03/15/06
CM1230
PRELIMINARY
Specifications
Note 1:
All parameters specified at T
A
= -40C to +85C unless otherwise noted.
Note 2:
These parameters guaranteed by design and characterization.
Note 3:
Human Body Model per MIL-STD-883, Method 3015, C
Discharge
= 100pF, R
Discharge
= 1.5K
, V
P
= 3.3V, V
N
grounded.
Note 4:
Standard IEC 61000-4-2 with C
Discharge
= 150pF, R
Discharge
= 330
, V
P
= 3.3V, V
N
grounded.
Note 5:
These measurements performed with no external capacitor on V
P
.
Note 6:
Measured under pulsed conditions, pulse width = 0.7ms, maximum current = 1.5A.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNITS
Operating Supply Voltage (V
P
- V
N
)
6.0
V
Operating Temperature Range
-40 to +85
C
Storage Temperature Range
-65 to +150
C
DC Voltage at any channel input
(V
N
- 0.5) to (V
P
+ 0.5)
V
STANDARD OPERATING CONDITIONS
PARAMETER
RATING
UNITS
Operating Temperature Range
-40 to +85
C
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 1)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
P
Operating Supply Voltage (V
P
-V
N
)
3.3
5.5
V
I
P
Operating Supply Current
(V
P
-V
N
)=3.3V
8.0
A
V
F
Diode Forward Voltage
Top Diode
Bottom Diode
I
F
= 8mA; T
A
=25C
0.60
0.60
0.80
0.80
0.95
0.95
V
V
I
LEAK
Channel Leakage Current
T
A
=25C; V
P
=5V, V
N
=0V,
V
IN
= 0V to 5V
0.1
1.0
A
C
IN
Channel Input Capacitance
At 1 MHz, V
P
=3.3V, V
N
=0V,
V
IN
=1.65V; Note 2 applies
0.8
1.20
pF
C
IN
Channel Input Capacitance Matching
At 1 MHz, V
P
=3.3V, V
N
=0V,
V
IN
=1.65V; Note 2 applies
0.02
pF
C
MUTUAL
Mutual Capacitance between signal
pin and adjacent signal pin
At 1 MHz, V
P
=3.3V, V
N
=0V,
V
IN
=1.65V; Note 2 applies
0.15
pF
V
ESD
In-system ESD Protection
Peak Discharge Voltage at any
channel input, in system
a) Contact discharge per
IEC 61000-4-2 standard
b) Human Body Model, MIL-
STD-883, Method 3015
Notes 2, 4 & 5; T
A
=25C
Notes 2, 3 & 5; T
A
=25C
8
15
kV
kV
V
CL
Channel Clamp Voltage
Positive Transients
Negative Transients
T
A
=25C, I
PP
= 1A, t
P
= 8/20
S;
Notes 2, & 5
+9.8
-1.8
V
V
R
DYN
Dynamic Resistance
Positive Transients
Negative Transients
I
PP
= 1A, t
P
= 8/20
S
Any I/O pin to Ground; Note 2 and 5
0.76
0.56
2006 California Micro Devices Corp. All rights reserved.
03/15/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.cmd.com
5
CM1230
PRELIMINARY
Performance Information
Input Channel Capacitance Performance Curves
0.60
0.65
0.70
0.75
0.80
0.85
0.90
-50
-25
0
25
50
75
100
Temperature ['C]
C
a
pa
c
i
t
a
nc
e
[
pF]
0V DC Input Bias
1.65 DC Input Bias
Typical Variation of C
IN
vs. V
IN
(f=1MHz, V
P
= 3.3V, V
N
= 0V, 0.1
F chip capacitor between V
P
and V
N,
T
A
=
25C)
Typical Variation of C
IN
vs. Temp
(f=1MHz, V
IN
=30mV, V
P
= 3.3V, V
N
= 0V,
0.1
F chip capacitor between V
P
and V
N
)
0.000
0.200
0.400
0.600
0.800
1.000
1.200
1.400
1.600
1.800
2.000
0
0.5
1
1.5
2
2.5
3
Bias Voltage (V)
C
a
pa
c
i
t
a
nc
e
(
pF)
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