2006 California Micro Devices Corp. All rights reserved.
02/21/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.cmd.com
1
CM2006
PRELIMINARY
VGA Port Companion Circuit For Monitors
Features
Includes ESD protection, level-shifting, buffering
and sync impedance matching
VESA VSIS Version 1 Revision 2 Compatible Inter-
face
Supports Optional NAVI Signalling requirements
7 channels of ESD protection for all VGA port con-
nector pins meeting IEC-61000-4-2 Level 4 ESD
requirements (
8kV contact discharge)
Very low loading capacitance from ESD protection
diodes on VIDEO lines, 3pF maximum
Schmitt triggered input buffers for HSYNC and
VSYNC lines
Bi-directional level shifting N-channel FETs pro-
vided for DDC_CLK & DDC_DATA channels
Backdrive protection on all lines
Compact 16-lead QSOP package
Applications
VGA and DVI-I ports in:
- Monitors
- Set Top Boxes
Product Description
The CM2006 connects between the VGA or DVI-I port
connector and the internal analog or digital flat panel
controller logic. The CM2006 incorporates ESD protec-
tion for all signals, level shifting for the DDC signals
and buffering for the SYNC signals. ESD protection for
the video, DDC and SYNC lines is implemented with
low-capacitance current steering diodes.
All connector interface pins are designed to safely han-
dle the high current spikes specified by IEC-61000-4-2
Level 4 (
8kV contact discharge). The ESD protection
for the DDC, SYNC and VIDEO signal pins is designed
to prevent "back current" when the device is powered
down while connected to a video source that is pow-
ered up.
Separate positive supply rails are provided for the
VIDEO / SYNC signals and DDC signals to facilitate
interfacing with low voltage video controller ICs and
microcontrollers to provide design flexibility in multi-
supply-voltage environments.
Two Schmitt-Triggered non-inverting buffers redrive
and condition the HSYNC and VSYNC signals from the
video Connector (SYNC1, SYNC2). These buffers
accept VESA VSIS compliant TTL input signals and
convert them to CMOS output levels that swing
between Ground and V
CC
.
(cont'd next page)
Simplified Electrical Schematic
VIDEO_1
VIDEO_2
VIDEO_3
GND
SYNC_OUT2
GND
V
CC_DDC
V
CC
SYNC_OUT1
SYNC_IN2
SYNC_IN1
DDC_IN2
DDC_IN1
R
T
3
4
5
6
9
12
13
15
1
8
14
16
DDC_OUT2
DDC_OUT1
11
10
BYP
R
T
7
ENABLE
2
2006 California Micro Devices Corp. All rights reserved.
2
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.cmd.com
02/21/06
CM2006
PRELIMINARY
Product Description (cont'd)
Two N-channel MOSFETs provide the level shifting
function required when the DDC controller or EDID
EEPROM is operated at a lower supply voltage than
the monitor. The gate terminals for these MOSFETS
(V
CC_DDC
) should be connected to the supply rail (typi-
cally 3.3V, 2.5V etc.) that supplies power to the trans-
ceivers of the DDC controller.
PIN DESCRIPTIONS
LEAD(s)
NAME
DESCRIPTION
1
V
CC
This is a supply input for the SYNC_1 and SYNC_2 level shifters, video protection and the
DDC circuits.
2
ENABLE
Active high enable. Disables the Sync buffer outputs when low.
3
VIDEO_1
Video signal ESD protection channel. This pin is typically tied one of the video lines between
the controller device and the video connector.
4
VIDEO_2
Video signal ESD protection channel. This pin is typically tied one of the video lines between
the controller device and the video connector.
5
VIDEO_3
Video signal ESD protection channel. This pin is typically tied one of the video lines between
the controller device and the video connector.
6
GND
Ground reference supply pin.
7
V
CC_DDC
This is an isolated supply input for the DDC_1 and DDC_2 level-shifting N-FET gates.
8
BYP
An external 0.22uF bypass capacitor is required on this pin.
9
DDC_IN1
DDC signal input. Connects to the video connector side of one of the DDC lines.signal output.
10
DDC_OUT1
DDC signal output. Connects to the monitor DDC logic.
11
DDC_OUT
DDC signal output. Connects to the monitor DDC logic.
12
DDC_IN2
DDC signal input. Connects to the video connector side of one of the DDC lines
13
SYNC_IN1
Sync signal buffer input. Connects to the video connector side of one of the sync lines.
14
SYNC_OUT1
Sync signal buffer output. Connects to the monitor SYNC logic.
15
SYNC_IN2
Sync signal buffer input. Connects to the video connector side of one of the sync lines.
16
SYNC_OUT2
Sync signal buffer output. Connects to the monitor SYNC logic.
PACKAGE / PINOUT DIAGRAM
Note: This drawing is not to scale.
Top View
16 Pin QSOP
1
2
3
4
14
13
12
11
5
6
7
10
9
8
15
16
SYNC_OUT2
SYNC_IN2
SYNC_OUT1
SYNC_IN1
DDC_IN2
DDC_OUT2
DDC_OUT1
V
CC
ENABLE
VIDEO_1
VIDEO_2
VIDEO_3
GND
V
CC_DDC
DDC_IN1
BYP
2006 California Micro Devices Corp. All rights reserved.
02/21/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.cmd.com
3
CM2006
PRELIMINARY
Ordering Information
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
PART NUMBERING INFORMATION
Pins
Package
Standard Finish
Lead-free Finish
Ordering Part
Number
1
Part Marking
Ordering Part
Number
1
Part Marking
16
QSOP
CM2006-02QS
CM2006-02QS
CM2006-02QR
CM2006-02QR
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNITS
V
CC_DDC
and
V
CC
Supply Voltage Inputs
[GND - 0.5] to +6.0
V
DC Voltage at Inputs
VIDEO_1, VIDEO_2, VIDEO_3
DDC_IN1, DDC_IN2
DDC_OUT1, DDC_OUT2
SYNC_IN1, SYNC_IN2, ENABLE
[GND - 0.5] to [V
CC
+ 0.5]
[GND - 0.5] to 6.0
[GND - 0.5] to 6.0
[GND - 0.5] to [V
CC
+ 0.5]
V
V
V
V
Operating Temperature Range
-40 to +85
C
Storage Temperature Range
-40 to +150
C
Package Power Rating (T
A
=25C)
500
mW
STANDARD OPERATING CONDITIONS
PARAMETER
RATING
UNITS
Operating Temperature Range
-40 to +85
C
V
CC
5
V
2006 California Micro Devices Corp. All rights reserved.
4
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.cmd.com
02/21/06
CM2006
PRELIMINARY
Specifications
Note 1: All parameters specified over standard operating conditions unless otherwise noted
Note 2: These parameters apply only to the SYNC drivers. Note that R
OUT
= R
T
+ R
BUFFER
.
Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. BYP and V
CC
must be bypassed to
GND via a low impedance ground plane with a 0.22
F, low inductance, chip ceramic capacitor at each supply pin. ESD
pulse is applied between the applicable pins and GND. ESD pulses can be positive or negative with respect to GND. Appli-
cable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_IN1, SYNC_IN2, DDC_IN1 and DDC_IN2. All pins are ESD pro-
tected to the industry standard
2kV Human Body Model (MIL-STD-883, Method 3015).
Note 4: This parameter is guaranteed by design and characterization.
Note 5: This specification applies to the SYNC_OUT pins only.
Note 6: Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_IN1, SYNC_IN2, DDC_IN1 and DDC_IN2.
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 1)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
I
CC_DDC
V
CC_DDC
Supply Current
V
CC_DDC
= 5.0V
10
A
I
CC
V
CC
Supply Current
V
CC
= 5V; SYNC inputs at GND or V
CC
;
SYNC outputs unloaded
1
mA
V
CC
= 5V; SYNC inputs at 3.0V;
SYNC outputs unloaded
2.0
mA
V
F
ESD Diode Forward Voltage
I
F
= 10mA
1.0
V
V
IH
Logic High Input Voltage
V
CC
= 5.0V; Note 2
2.0
V
V
IL
Logic Low Input Voltage
V
CC
= 5.0V; Note 2
0.5
V
V
HYS
Hysteresis Voltage
V
CC
= 5.0V; Note 2
400
mV
V
OH
Logic High Output Voltage
I
OH
= 0mA, V
CC
= 5.0V; Note 2
4.0
V
V
OL
Logic Low Output Voltage
I
OL
= 0mA, V
CC
= 5.0V; Note 2
0.15
V
R
OUT
SYNC Driver Output Resistance
V
CC
= 5.0V; SYNC Inputs at GND or 3.0V
7
15
24
I
IN
Input Current
VIDEO Inputs
V
CC
= 5.0V; V
IN
= V
CC
or GND
10
A
SYNC_IN1, SYNC_IN2 Inputs
V
CC
= 5.0V; V
IN
= V
CC
or GND
10
A
I
OFF
Level Shifting N-MOSFET "OFF" State
Leakage Current
(V
CC_DDC
- V
DDC_IN
)
< 0.4V; V
DDC_OUT
= V
CC_DDC
10
A
(V
CC_DDC
- V
DDC_OUT
)
< 0.4V; V
DDC_IN
= V
CC_DDC
10
A
I
BACKDRIVE
Current conducted from input pins when Vcc
is powered down.
V
CC
< V
INPUT_PIN ;
Note 6
10
A
V
ON
Voltage Drop Across Level-shifting
N-MOSFET when "ON"
V
CC_DDC
= 2.5V; V
S
= GND; I
DS
= 3mA;
0.18
V
C
IN_VID
VIDEO Input Capacitance
V
CC
= 5.0V; V
IN
= 2.5V; f
= 1MHz; Note 4
3
pF
V
CC
= 2.5V; V
IN
= 1.25V; f
= 1MHz; Note 4
3.5
pF
t
PLH
SYNC Driver L => H Propagation Delay
C
L
= 50pF; V
CC
= 5.0V; Input t
R
and t
F
< 5ns
12
ns
t
PHL
SYNC Driver H => L Propagation Delay
C
L
= 50pF; V
CC
= 5.0V; Input t
R
and t
F
< 5ns
12
ns
t
R,
t
F
SYNC Driver Output Rise & Fall Times
C
L
= 50pF; V
CC
= 5.0V; Input t
R
and t
F
< 5ns
3
ns
V
ESD1
ESD Withstand Voltage, Sync_out pins only V
CC
= 5V; Notes 3, 4, & 5
2
kV
V
ESD
ESD Withstand Voltage
V
CC
= 5V; Notes 3, 4, & 6
8
kV
2006 California Micro Devices Corp. All rights reserved.
02/21/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.cmd.com
5
CM2006
PRELIMINARY
Application Information
Figure 1. Typical Application Connection Diagram
NOTES
1
The CM2006 should be placed as close to the VGA or DVI-I connector as possible.
2
The ESD protection channels VIDEO_1, VIDEO_2, VIDEO_3 may be used interchangeably between the R, G, B signals.
3
If differential video signal routing is used, the RED, BLUE, and GREEN signal lines should be terminated with external 37.5
ohm resistors.
4
"VF" are external video filters for the RGB signals.
5
Supply bypass capacitors C1 and C2 must be placed immediately adjacent to the corresponding Vcc pins. Connections to
the Vcc pins and ground plane must be made with minimal length copper traces (preferably less than 5mm) for best ESD
protection.
6
The bypass capacitor for the BYP pin has been omitted in this diagram. This results in a reduction in the maximum ESD
withstand voltage at the DDC_OUT pins from
8kV to 2kV. If 8kV ESD protection is required, a 0.22
F ceramic bypass
capacitor should be connected between BYP and ground.
7
The SYNC buffers may be used interchangeably between HSYNC and VSYNC.
8
The EMI filters at the SYNC_OUT and DDC_OUT pins (C5 to C12, and Ferrite Beads FB1 to FB4) are for reference only.
The component values and filter configuration may be changed to suit the application.
9
The DDC level shifters DDC_IN, DDC_OUT, may be used interchangeably between DDCA_CLK and DDCA_DATA.
10 R1, R2 are optional. They may be used, if required, to pull the DDC_CLK and DDC_DATA lines to VCC_5V when no mon-
itor is connected to the VGA connector. If used, it should be noted that "back current" may flow between the DDC pins and
VCC_5V via these resistors when VCC_5V is powered down.
DDC_OUT2
DDC_IN1
DDC_IN2
RED_VIDEO
Video Port
DDC_CLK
DDC_DATA
BLUE_VIDEO
GREEN_VIDEO
VCC_5V
DDCA_CLK
DDCA_DATA
RED
GREEN
BLUE
CM2006
V
CC
VIDEO_1
VIDEO_2
VIDEO_3
FB4
C11
C12
FB3
C9
C10
FB2
C7
C8
FB1
C5
C6
Optional EMI Filters
75
75
75
SYNC_OUT1
SYNC_OUT2
DDC_OUT1
VSYNC
HSYNC
Connector
V
CC_DDC
VF**
VF**
VF**
** VIDEO Filters.
SYNC_IN1
SYNC_IN2
VSYNC
HSYNC
V
CC_GPIO
0.22uF
0.22uF
BYP
R
R
ENABLE
2006 California Micro Devices Corp. All rights reserved.
6
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.cmd.com
02/21/06
CM2006
PRELIMINARY
Mechanical Details
QSOP Mechanical Specifications
CM2006 devices are packaged in 16-pin QSOP pack-
ages. Dimensions are presented below.
For complete information on the QSOP-16 package,
see the California Micro Devices QSOP Package Infor-
mation document.
* This is an approximate number which may vary.
Package Dimensions for QSOP-16
PACKAGE DIMENSIONS
Package
QSOP (JEDEC name is SSOP)
Pins
16
Dimensions
Millimeters
Inches
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
B
0.20
0.30
0.008
0.012
C
0.18
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.81
3.98
0.150
0.157
e
0.64 BSC
0.025 BSC
H
5.79
6.19
0.228
0.244
L
0.40
1.27
0.016
0.050
# per tube
100 pcs*
# per tape
and reel
2500 pcs
Controlling dimension: inches
Mechanical Package Diagrams
E
D
H
TOP VIEW
L
END VIEW
C
e
B
A
A1
SEATING
PLANE
SIDE VIEW
5
6
7
8
1
2
3
4
12 11 10 9
16 15 14 13
Pin 1 Marking
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