05/08/06

490 N. McCarthy Blvd., Milpitas, CA 95035-5112

Tel: 408.263.3214

Fax: 408.263.7846

www.cmd.com

CM3202

PRELIMINARY

Features

Two linear regulators
-Maximum 2A current from V

DDQ

-Source and sink up to 2A V

current

1.7V to 2.8V adjustable V

DDQ

output voltage

500mV typical V

DDQ

dropout voltage at 2A

tracking at 50% of V

DDQ

Excellent load and line regulation, low noise

Fast transient response

Meet JEDEC DDR-I and DDR-II memory power spec.

Linear regulator design requires no inductors and has
low external component count

Integrated power MOSFETs

Dual purpose ADJ/Shutdown pin

Built-in over-current limit with short-circuit foldback and
thermal shutdown for V

DDQ

and V

Fast transient response

5mA quiescent current

TDFN-8 and SOIC-8 packages for high performance
thermal dissipation and easy PC board layout

Optional RoHS Compliant Lead-free packaging

Applications

DDR memory and active termination buses

Desktop Computers, Servers

Residential and Enterprise Gateways

DSL Modems

Routers and Switchers

DVD recorders

3D AGP cards

LCD TV and STB

Product Description

he CM3202 is a dual-output low noise linear regulator

designed to meet SSTL-2 and SSTL-3 specifications
for DDR-SDRAM V

DDQ

supply and termination voltage

supply. With integrated power MOSFET's, the

CM3202 can source up to 2A of V

DDQ

current, and

source or sink up to 2A V

current. The typical drop-

out voltage for V

DDQ

is 500 mV at 2A load current.

The CM3202 provides fast response to transient load
changes. Load regulation is excellent, less than 1%,
from no load to full load. It also has built-in over-current
limits and thermal shutdown at 170

The CM3202 is packaged in an easy-to-use TDFN-8
and SOIC-8. Low thermal resistance (55

/W) allows it

to withstand 1.55W

(1)

dissipation at 85

ambient. It

can operate over the industrial ambient temperature
range of 40

to 85

Note

(1)

If TDFN-8 is mounted on a double-sided printed circuit board with
two square inches of copper area, it can to withstand 2W dissipation
at 85°C ambient then.

Typical Application

DL0

VDDQ

C hip

S et

DLn

DDR

Memory

REF

845

887

VDDQ

RT0

RTn

220u

3.3V

1.25V, 2.5A

S/D

4.7u

ADJSD

GND

VDDQ

VTT

VIN

CM3202

REF

GND

VIN

VDDQ

220u

4.7u

VTT

DDR V

DDQ

and Termination Voltage Regulator

490 N. McCarthy Blvd., Milpitas, CA 95035-5112

Tel: 408.263.3214

Fax: 408.263.7846

www.cmd.com

05/08/06

CM3202

PRELIMINARY

Ordering Information

Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.

Specifications

PACKAGE / PINOUT DIAGRAM

8-Lead TDFN Package

8-Lead SOIC Package

CM3202-00DE

GND

DDQ

ADJSD

GND

TOP VIEW

GND

PAD

Pin 1

Marking

TOP VIEW

Note: This drawing is not to scale.

DDQ

ADJSD

GND

CM3202-00SM

PART NUMBERING INFORMATION

Pins

Package

Lead-free Finish

Ordering Part Number

Part Marking

TDFN

CM3202-00DE

CM3202

SOIC

CM3202-00SM

CM3202

ABSOLUTE MAXIMUM RATINGS

PARAMETER

RATING

UNITS

VIN to GND

[GND - 0.3] to +6.0

Pin Voltages

DDQ

to GND

ADJSD to GND

[GND - 0.3] to +6.0
[GND - 0.3] to +6.0

V
V

Storage Temperature Range

-65 to +150

°C

Operating Temperature Range

-40 to +85

°C

Lead Temperature (Soldering, 10s)

300

°C

Package Pinout

05/08/06

490 N. McCarthy Blvd., Milpitas, CA 95035-5112

Tel: 408.263.3214

Fax: 408.263.7846

www.cmd.com

CM3202

PRELIMINARY

ELECTRICAL OPERATING CHARACTERISTICS

(SEE NOTE 1)

= 3.3V, typical values are at T

= 25°C (unless otherwise specified)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

VIN

Supply Voltage Range

3.3

3.6

UVLO

Under-voltage Lockout

All outputs are no load

2.5

UVLO Hysterisis

200

Quiescent Current

DDQ

= 0V, V

= 0V,

ADJSD = 3.3V (shutdown)

200

DDQ

= 2.5V, V

= 1.25V, (no load)

DDQ

Regulator

Output Current Limit

OUT

= 2.5V

2.8

REF

Reference Voltage

1.235

1.250

1.265

BIAS

Input Bias Current (I

ADJ

)

VADJSD = V

REF

200

R LOAD

Load Regulation

= 10mA to 2A

R LINE

Line Regulation

= 3.15V to 3.5V, I

= 10mA

DROPOUT

Dropout Voltage

= 3.15V, I

= 2A

500

Regulator

Output Current Limit (Source)

OUT

= 1.25V

2.8

Output Current Limit (Sink)

OUT

= 1.25V

2.8

R VTTLOAD

Load Regulation

= 0A to 2A

= 0A to -2A

Over Temperature Protection

Thermal Shutdown Temperature

170

°C

Thermal Shutdown Hysteresis

°C

Specifications (cont'd)

490 N. McCarthy Blvd., Milpitas, CA 95035-5112

Tel: 408.263.3214

Fax: 408.263.7846

www.cmd.com

05/08/06

CM3202

PRELIMINARY

VDDQ Dropout vs. IDDQ

IDDQ (A)

Dropout

Voltage

(mV)

VTT vs. VDDQ

0.75

0.85

0.95

1.05

1.15

1.25

1.35

1.45

1.55

1.65

1.5

1.75

2.25

2.5

2.75

3.25

VDDQ (V)

(
V)

Vin

VDDQ

VTT

1ms/div

1V/div

UVLO

Startup into Full Load

VDDQ vs.

Temperature

2.49

2.495

2.505

2.51

-40 -20

Temperatur

(V)

VDDQ vs. Load Current

VDDQ

(V)

IDDQ (A)

Ta=25 oC
Vin=3.3V

Ta=25 oC

Typical Operating Characteristics

490 N. McCarthy Blvd., Milpitas, CA 95035-5112

Tel: 408.263.3214

Fax: 408.263.7846

www.cmd.com

05/08/06

CM3202

PRELIMINARY

Pin Descriptions

PIN DESCRIPTIONS

PIN(S)

TDFN 8

PIN(S)

SOIC 8

NAME

DESCRIPTION

1, 2

Input voltage pin, typically 3.3V from the silver box.

2, 4

regulator output voltage pin, which is preset to 50% of V

DDQ

5, 6

4, 5

GND

Ground pin. The back tab is also ground and serves as the package
heatsink. It should be soldered to the circuit board copper to remove
excess heat from the IC.

ADJSD

This pin is for V

DDQ

output voltage Adjustment. The V

DDQ

output voltage is

set using an external resistor divider connected to ADJSD. The output
voltage is determined by the following formula

where R1 is the ground-side resistor and R2 is the upper resistor of the
divider. Connect these resistors to the V

DDQ

output at the point of

regulation.

In addition, functions as a Shutdown pin. Apply a voltage higher than V

0.6V to this pin to simultaneously shutdown both V

DDQ

and V

outputs.

The outputs are restored when the voltage is lowered below V

-0.6V. A

low-leakage diode in series with the Shutdown signal is recommended to
avoid interference with the voltage adjustment setting.

7, 8

DDQ

regulator output voltage pin.

DDQ

1.25V

R1 R2

---------------------

Pin Description

05/08/06

490 N. McCarthy Blvd., Milpitas, CA 95035-5112

Tel: 408.263.3214

Fax: 408.263.7846

www.cmd.com

CM3202

PRELIMINARY

Application Information

Powering DDR Memory

Double-Data-Rate (DDR) memory has provided a huge
step in performance for personal computers, servers
and graphic systems. As is apparent in its name, DDR
operates at double the data rate of earlier RAM, with
two memory accesses per cycle versus one. DDR
SDRAM's transmit data at both the rising falling edges
of the memory bus clock.

DDR's use of Stub Series Terminated Logic (SSTL)
topology improves noise immunity and power-supply
rejection, while reducing power dissipation. To achieve
this performance improvement, DDR requires more
complex power management architecture than previ-
ous RAM technology.

Unlike the conventional DRAM technology, DDR
SDRAM uses differential inputs and a reference volt-
age for all interface signals. This increases the data
bus bandwidth, and lowers the system power con-
sumption. Power consumption is reduced by lower
operating voltage, a lower signal voltage swing associ-
ated with Stub Series Terminated Logic (SSTL_2) and
by the use of a termination voltage, V

. SSTL_2 is an

industry standard, defined in JEDEC document
JESD8-9. SSTL_2 maintains high-speed data bus sig-
nal integrity by reducing transmission reflections.
JEDEC further defines the DDR SDRAM specification
in JESD79C.

DDR memory requires three tightly regulated voltages:
V

DDQ

, V

, and V

REF

(see

Figure 1

). In a typical

SSTL_2 receiver, the higher current V

DDQ

supply volt-

age is normally 2.5V with a tolerance of ±200

mV. The

active bus termination voltage, V

, is half of V

DDQ

REF

is a reference voltage that tracks half of V

DDQ

, ±

1%, and is compared with the V

terminated signal at

the receiver. V

must be within ±40

mV of V

REF

1.22V

CM3202

Application Information (cont'd)

490 N. McCarthy Blvd., Milpitas, CA 95035-5112

Tel: 408.263.3214

Fax: 408.263.7846

www.cmd.com

05/08/06

CM3202

PRELIMINARY

Figure 1. Typical DDR terminations, Class II

The V

power requirement is proportional to the num-

ber of data lines and the resistance of the termination
resistor, but does not vary with memory size.

In a typi-

cal DDR data bus system each data line termination
may momentarily consume 16.2

mA to achieve the

405

mV minimum over V

needed at the receiver:

A typical 64 Mbyte SSTL-2 memory system, with 128
terminated lines, has a worst-case maximum V

sup-

ply current up to ± 2.07A. However, a DDR memory
system is dynamic, and the theoretical peak currents
only occur for short durations, if they ever occur at all.
These high current peaks can be handled by the V

external capacitor. In a real memory system, the con-
tinuous average V

current level in normal operation

is less than ± 200 mA.

The V

DDQ

power supply, in addition to supplying cur-

rent to the memory banks, could also supply current to
controllers and other circuitry. The current level typi-
cally stays within a range of 0.5A to 1A, with peaks up
to 2A or more, depending on memory size and the
computing operations being performed.

The tight tracking requirements and the need for V

sink, as well as source, current provide unique chal-
lenges for powering DDR SDRAM.

CM3202 Regulator

The CM3202 dual output linear regulator provides all of
the power requirements of DDR memory by combining
two linear regulators into a single TDFN-8 or SOIC-8
package. V

DDQ

regulator can supply up to 2A current,

and the two-quadrant V

termination regulator has

current sink and source capability to ±2A. The V

DDQ

linear regulator uses a PMOS pass element for a very
low dropout voltage, typically 500mV at a 2A output.
The output voltage of V

DDQ

can be set by an external

voltage divider. The second output, V

, is regulated at

DDQ

/2 by an internal resistor divider. The V

regula-

tor can source, as well as sink, up to 2A current. The
CM3202 is designed for optimal operation from a nom-
inal 3.3VDC bus, but can work with VIN as high as 5V.
When operating at higher VIN voltages, attention must
be given to the increased package power dissipation
and proportionally increased heat generation.

REF

is typically routed to inputs with high impedance,

such as a comparator, with little current draw. An ade-
quate V

REF

can be created with a simple voltage

divider of precision, matched resistors from V

DDQ

ground. A small ceramic bypass capacitor can also be
added for improved noise performance.

Input and Output Capacitors

The CM3202 requires that at least a 220

F electrolytic

capacitor be located near the V

pin for stability and to

maintain the input bus voltage during load transients.
An additional 4.7

F ceramic capacitor between the V

and the GND, located as close as possible to those
pins, is recommended to ensure stability.

A minimum of a 220

F electrolytic capacitor is recom-

mended for the V

DDQ

output. An additional 4.7

ceramic capacitor between the V

DDQ

and GND, located

very close to those pins, is recommended.

A minimum of a 220

F, electrolytic capacitor is recom-

mended for the V

output. This capacitor should have

low ESR to achieve best output transient response. SP
or OSCON capacitors provide low ESR at high fre-
quency, and thus are a good choice. In addition, place
a 4.7

F ceramic capacitor between the V

pin and

GND, located very close to those pins. The total ESR
must be low enough to keep the transient within the
V

window of 40mV during the transition for source to

sink. An average current step of ± 0.5A requires:

Both outputs will remain stable and in regulation even
during light or no load conditions.

Transmitter

VDDQ

VTT (=VDDQ/2) VDDQ

Receiver

Rs = 25

Line

Rt = 25

VREF (=VDDQ/2)

terminaton

405mV

Rt 25

(

)

----------------------

16.2mA

ESR

40mV

---------------

40m

Application Info (cont'd)

05/08/06

490 N. McCarthy Blvd., Milpitas, CA 95035-5112

Tel: 408.263.3214

Fax: 408.263.7846

www.cmd.com

CM3202

PRELIMINARY

Adjusting V

DDQ

Output Voltage

The CM3202 internal bandgap reference is set at
1.25V. The V

DDQ

voltage is adjustable by using a resis-

tor divider, R1 and R2:

where V

ADJ

= 1.25V (±

1%). For best regulator stability,

we recommend that R1 and R2 not exceed 10k

each.

Shutdown

ADJSD also serves as a shutdown pin. When this is
pulled high, > (V

- 0.6V), the V

DDQ

output is turned

off and both source and sink MOSFET's of the V

reg-

ulator are set to a high impedance state. During shut-
down, the quiescent current is reduced to less than
3mA, independent of output load.

It is recommended that a 1N914 or equivalent low leak-
age diode be placed between ADJSD Pin and an
external shutdown signal to prevent interference with
the ADJ pin's normal operation. When the diode anode
is pulled low, or left open, the CM3202 is again
enabled.

Current Limit, Foldback and Over-temperature Pro-
tection

The CM3202 features internal current limiting with ther-
mal protection. During normal operation, V

DDQ

limits

the output current to approximately 2A and V

limits

the output current to approximately ±2A. When V

current limiting into a hard short circuit, the output cur-
rent folds back to a lower level, about 1A, until the over-
current condition ends. While current limiting is
designed to prevent gross device failure, care should
be taken not to exceed the power dissipation ratings of
the package. If the junction temperature of the device
exceeds 170

°C (typical), the thermal protection cir-

cuitry triggers and shuts down both outputs. Once the
junction temperature has cooled to below about
120

°C, the CM3202 returns to normal operation.

Thermal Considerations

Typical Thermal Characteristics

The overall junction to ambient thermal resistance
(

) for device power dissipation (P

) primarily con-

sists of two paths in the series. The first path is the
junction to the case (

) which is defined by the pack-

age style and the second path is case to ambient (

)

thermal resistance which is dependent on board layout.
The final operating junction temperature for any condi-
tion can be estimated by the following thermal equa-
tion:

When a CM3202 is mounted on a double-sided printed
circuit board with two square inches of copper allo-
cated for "heat spreading," the

is approximately

42.5

°C/Watt for the CM3202-00DE (TDFN-8) and

°C/Watt for CM3202-00SM (SOIC-8). Based on the

over temperature limit of 170°C with an ambient of
85°C, the available power of the package will be:

PCB Layout Considerations

TheCM3202 has a heat spreader attached to the bot-
tom of the TDFN-8 package in order for the heat to be
transferred more easily from the package to the PCB.
The heat spreader is a copper pad of dimensions just
smaller than the package itself. By positioning the
matching pad on the PCB top layer to connect to the
spreader during the manufacturing, the heat will be
transferred between the two pads. See the

Figure 2

the CM3202-00DE (TDFN-8) and CM3202-00SM
(SOIC-8) show the recommended PCB layout. Please
be noted that there are six vias in the SOIC-8 package
(four vias in the TDFN-8 package) on either side to
allow the heat to dissipate into the ground and power
planes on the inner layers of the PCB. Vias can be
placed underneath the chip, but this can be resulted in

DDQ

ADJ

R1 R2

---------------------

JUNC

AMB

(

)

(

)

AMB

(

)

/ W

42.5

170

D(TDFN8)

/ W

170

D(SOIC8)

Application Info (cont'd)

05/08/06

490 N. McCarthy Blvd., Milpitas, CA 95035-5112

Tel: 408.263.3214

Fax: 408.263.7846

www.cmd.com

CM3202

PRELIMINARY

blocking of the solder. The ground and power planes
need to be at least 2 square inches of copper by the
vias. It also helps dissipation if the chip is positioned
away from the edge of the PCB, and not near other
heat-dissipating devices. A good thermal link from the
PCB pad to the rest of the PCB will assure the best

heat transfer from the CM3202-00DE (TDFN-8) to
ambient,

, of approximately 42.5

°C/W, or

approximately 85 °C/W for the CM3202-00SM (SOIC-
8).

Figure 2. Thermal Layout

Top View

Bottom Layer

Ground Plane

Top Layer Copper

Connects to Heat Spreader

Pin Solder Mask

Thermal PAD

Solder Mask

Vias (0.3mm Diameter)

(TDFN-8 Package)

Bottom Layer

Ground Plane

Top Layer Copper

Connects to Heat Spreader

Top View

Pin Solder Mask

Vias (0.3mm Diameter)

Note: This drawing is not to scale

(SOIC-8 Package)

Application Info (cont'd)

05/08/06

490 N. McCarthy Blvd., Milpitas, CA 95035-5112

Tel: 408.263.3214

Fax: 408.263.7846

www.cmd.com

CM3202

PRELIMINARY

TDFN-08 Mechanical Specifications

The CM3202-00DE is supplied in an 8-lead, 0.65mm
pitch TDFN package. Dimensions are presented below.

This package is compliant with JEDEC standard MO-229, variation

VEEC-1 with exception of the "D2", "E2" and "b" dimensions as
called out in the table above.

Package Dimensions for 8-Lead TDFN

PACKAGE DIMENSIONS

Package

TDFN

JEDEC

No.

MO-229 (Var. WEEC-1)

Leads

Dim.

Millimeters

Inches

Min

Nom

Max

Min

Nom

Max

0.70

0.75

0.80

0.028

0.030

0.031

0.00

0.02

0.05

0.000

0.001

0.002

0.45

0.55

0.65

0.018

0.022

0.026

0.20

0.008

0.25

0.30

0.35

0.010

0.012

0.014

3.00

0.118

1.90

2.00

2.10

0.075

0.079

0.083

3.00

0.118

1.60

1.70

1.80

0.063

0.067

0.071

0.65

0.026

0.20

0.008

0.20

0.30

0.45

0.008

0.012

0.018

# per

tape and

reel

3000 pieces

Controlling dimension: millimeters

Mechanical Package Diagrams

BOTTOM VIEW

0.10 C

0.08 C

SIDE VIEW

TOP VIEW

0.10

C A B

GND PAD

Pin 1

Marking

C0.25

Mechanical Details

05/08/06

490 N. McCarthy Blvd., Milpitas, CA 95035-5112

Tel: 408.263.3214

Fax: 408.263.7846

www.cmd.com

CM3202

PRELIMINARY

SOIC-8 Mechanical Specifications

Dimensions for CM3202-00SM devices packaged in 8-
lead SOIC packages with an intagrated heatslug are
presented below.

* This is an approximate number which may vary.

Centered on package centerline.

Package Dimensions for SOIC-8

PACKAGE DIMENSIONS

Package

SOIC-8

Leads

Dimensions

Millimeters

Inches

Min

Max

Min

Max

1.30

1.62

0.051

0.064

0.03

0.10

0.001

0.004

0.33

0.51

0.013

0.020

0.18

0.25

0.007

0.010

4.83

5.00

0.190

0.197

3.81

3.99

0.150

0.157

1.27 BSC

0.050 BSC

5.79

6.20

0.228

0.244

0.41

1.27

0.016

0.050

# per tube

100 pieces*

# per tape

and reel

2500 pieces

Controlling dimension: inches

Mechanical Package Diagrams

TOP VIEW

END VIEW

SEATING

PLANE

SIDE VIEW

Pin 1
Marking

Mechanical Details (cont'd)

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