2001, 2002 California Micro Devices Corp. All rights reserved.
12/31/2001
1
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
CM88L70/70C
CALIFORNIA MICRO DEVICES
CMOS Integrated DTM. Receiver, 3V Version
Features
2.7V to 3.6V operating range
Full DTMF receiver
Less than 18mW power consumption
Industrial temperature range
Uses quartz crystal or ceramic resonators
Adjustable acquisition and release times
18-pin DIP, 20-pin QSOP, 18-pin SOIC,
20-pin PLCC, 20-pin TSSOP
CM88L70
Power down mode
Inhibit mode
Buffered oscillator output (OSC 3) to
drive other devices
Product Description
The CAMD CM88L70/70C provides full DTMF receiver
capability by integrating both the band-split filter and
digital decoder functions into a single 18-pin DIP,
SOIC, or 20-pin PLCC, TSSOP, or QSOP package. The
CM88L70/70C is manufactured using state-of-the-art
CMOS process technology for low power consumption
(35mW, MAX.) and precise data handling. The filter
section uses a switched capacitor technique for both
high and low group filters and dial tone rejection. The
Applications
PCMCIA
Portable TAD
Mobile radio
Remote control
Remote data entry
Call limiting
Telephone answering systems
Paging systems
C1581000
CM88L70/70C decoder uses digital counting techniques
for the detection and decoding of all 16 DTMF tone pairs
into a 4-bit code. This DTMF receiver minimizes external
component count by providing an on-chip differential
input amplifier, clock generator, and a latched three-state
interface bus. The on-chip clock generator requires only
a low cost TV crystal or ceramic resonator as an external
component.
Block Diagram
DIGITAL
DETECTION
ALGORITHM
ZERO
CROSSING DETECTORS
CODE
CONVERTER
AND
LATCH
+
V
DD
IN+
IN
BIAS
CIRCUIT
V
SS
CHIP
REF
CHP
BIAS
CHP
POWER
V
REF
StD
STEERING
LOGIC
PD
DIAL
TONE
FILTER
HIGH
GROUP
FILTER
LOW
GROUP
FILTER
+
INH
TOE
Q1
ESt
St
GT
OSC 1
OSC 2
OSC 3
TO ALL
CHIP
CLOCKS
St/GT
Q2
Q3
Q4
GS
2001, 2002 California Micro Devices Corp. All rights reserved.
12/31/2001
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
2
CM88L70/70C
CALIFORNIA MICRO DEVICES
Absolute Maximum Ratings: (Note 1)
This device contains input protection
against damage due to high static
voltages or electric fields; however,
precautions should be taken to avoid
application of voltages higher than the
maximum rating.
Notes:
1. Exceeding these ratings may cause
permanent damage, functional
operation under these conditions is
not implied.
DC Characteristics: All voltages referenced to V
SS
, V
DD
= 3V +20% or 10%, T
A
= 40C to +85C unless otherwise noted.
Operating Characteristics: All voltages referenced to V
SS
, V
DD
= 3V + 20% / 10%, T
A
= 40C to +85C unless otherwise noted.
Gain Setting Amplifier
Absolute Maximum Ratings
Symbol Parameter
Value
V
DD
Power
Supply
Voltage (V
DD
/V
SS
)
6V MAX
Vt
Voltage on any Pin
V
SS
0.3V to V
DD
+ 0.3V
I
t
Current on any Pin
10mA MAX
T
S
Storage Temperature
65C to 150C
DC Characteristics
Symbol
Parameter
Test Conditions
MIN
TYP
MAX
UNIT
V
DD
Operating Supply Voltage
V
2.7
3.0
3.6
V
I
DD
Operating Supply Current
3.0
5.0
mA
I
DDS
Standby Supply Current
PD = V
DD
5.0
10
A
V
IL
Low Level Input Voltage
V
DD
= 3V
1
V
V
IH
High Level Input Voltage
V
DD
= 3V
2.0
V
I
IH/
L
IL
Input Leakage Current
V
IN
= V
SS
or V
DD
(Note 1)
0.1 A
I
SO
Pull Up (Source) Current on TOE
TOE = 0V
12
2 A
I
PD
Pull down (sink) Current PD
PD = 3V
1
45
A
I
INH
Pull down (sink) Current INH
IHN = 3V
1
45
A
R
IN
Input Impedance, (IN+, IN) @
1KHz
10
M
V
Tst
Steering Threshold Voltage
1.5
V
V
OL
Low Level Output Voltage
I
OL
= 1mA
0.1
0.4
V
V
OH
High Level Output Voltage
I
OH
= 400A
2.4
2.6
V
I
OH
Output High (Source) Current
V
OUT
= 2.5V V
DD
= 2.7V
1
mA
V
REF
Output
Voltage
V
REF
No Load
1.5 V
R
OR
Output
Resistance
10
k
Operating Characteristics
Symbol
Parameter
Test Conditions
MIN
TYP
MAX
UNIT
I
IN
Input
Leakage Current
V
SS
< V
IN
< V
DD
100
nA
R
IN
Input
Resistance
10
M
V
OS
Input Offset Voltage
15
25
mV
PSRR
Power Supply Rejection
1 KHz (Note 12)
50
60
dB
CMRR
Common Mode Rejection
3V < V
IN
< 3V
40
60
dB
A
VOL
DC Open Loop Voltage Gain
32
65
dB
fc
Open Loop Unity Gain Bandwidth
0.3
1
MHz
V
O
Output
Voltage
Swing
R
L
100
KW to V
SS
2.2
V
P-P
C
L
Tolerable Capacitive Load (GS)
100
pF
R
L
Tolerable Resistive Load (GS)
K
Vcm
Common Mode Range (No Load)
No Load
5
1.5
V
P-P
2001, 2002 California Micro Devices Corp. All rights reserved.
12/31/2001
3
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
CM88L70/70C
CALIFORNIA MICRO DEVICES
9. Referenced to lowest level frequency component
in DTMF signal.
10. Minimum signal acceptance level is measured with
specified maximum frequency deviation.
11. Input pins defined as IN+, IN, and TOE.
12. External voltage source used to bias V
REF
.
13. This parameter also applies to a third tone injected onto
the power supply.
14. Referenced to Figure 1. Input DTMF tone level
at 28dBm.
15. Times shown are obtained with circuit in
Figure 1 (User adjustable).
AC Characteristics
Parameter
Notes
MIN
TYP
MAX
UNIT
Valid Input Signal Levels
1, 2, 3, 4, 5, 8
36
6.4
dBm
(each tone of composite signal)
12.3
370
mV
RMS
Positive Twist Accept
6
dB
Negative
Twist
Accept
6
dB
Freq. Deviation Aceept Limit
2, 3, 5, 8, 10
1.5%2Hz
Norm.
Freq. Deviation Reject Limit
2, 3, 5
3.5%
Norm.
Third Tone Tolerance
2, 3, 4, 5, 8, 9, 13, 14
16 dB
Noise Tolerance
2, 3, 4, 5, 6, 8, 9
12 dB
Dial Tone Tolerance
2, 3, 4,5, 7, 8, 9
22
dB
t
DP
Tone Present Detection Time
Refer to Timing Diagram
5
8
14
ms
t
DA
Tone Absent Dectection Time
Refer to Timing Diagram
0.5
3
8.5
ms
t
REC
MIN Tone Duration Accept
15
40
ms
MAX Tone Duration Reject
15
20
ms
t
ID
MIN Interdigit Pause Accept
15
40
ms
t
DO
MAX Interdigit Pause Reject
15
20
s
t
PQ
Propagation Delay (St to Q)
TOE = V
DD
13
s
t
PS
t
D
Propagation Delay (St to StD)
TOE = V
DD
8
s
t
QS
t
D
Output Data Set Up (Q to StD)
TOE = V
DD
3.4
s
t
PTE
Propagation Delay (TOE to Q)
Enable R
L
= 10K
200
ns
t
PTD
Disable
C
L
= 50pf
500
ns
f
CLK
Crystal/Clock
Frequency
3.5759
3.5795 3.5831 MHz
C
LO
Clock Ouput (OSC 2)
Capacitive Load
30
pF
Notes:
1. dBm = decibels above or below a reference power
of 1 mW into a 600
load.
2. Digit sequence consists of all 16 DTMF tones.
3. Tone duration = 40ms. Tone pause = 40ms.
4. Nominal DTMF frequencies are used.
5. Both tones in the composite signal have
an equal amplitude.
6. Bandwidth limited (0 to 3KHz) Gaussian Noise.
7. The precise dial tone frequencies are
(350Hz and 440Hz) 2%.
8. For an error rate of better than 1 in 10,000
AC Characteristics: All voltages referenced to V
SS
, V
DD
= 3V + 20% / 10%, T
A
= 40C to +85C, f
CLK
= 3.579545 MHz using the
test circuit in Figure 1 unless otherwise noted.
2001, 2002 California Micro Devices Corp. All rights reserved.
12/31/2001
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
4
CM88L70/70C
CALIFORNIA MICRO DEVICES
Explanation of Events
A. Tone bursts detected, tone duration invalid, outputs
not updated.
B. Tone #n detected, tone duration valid, tone decoded
and latched in outputs.
C. End of tone #n detected, tone absent duration valid,
outputs remain latched until next valid tone.
D. Outputs switched to high impedance state.
E. Tone #n + 1 detected, tone duration valid, tone
decoded and latched in outputs (currently high
impedance).
F. Acceptable dropout of tone #n + 1, tone absent
duration invalid, outputs remain latched.
G. End of tone #n + 1 detected, tone absent duration
valid, outputs remain latched until next valid tone.
Explanation of Symbols
V
IN
DTMF composite input signal.
ESt
Early Steering Output. Indicates detection
of valid tone frequencies.
St/GT
Steering input/guard time output. Drives
external RC timing circuit.
Q1-Q4
4-bit decoded tone output.
StD
Delayed Steering Output. Indicates that
valid frequencies have been present/absent
for the required guard time, thus constituting
a valid signal.
TOE
Tone Output Enable (input). A low level
shifts Q1-Q4 to its high impedance state.
t
REC
Maximum DTMF signal duration not
detected as valid.
t
REC
Minimum DTMF signal duration required
for valid recognition.
t
ID
Minimum time between valid DTMF signals.
t
DO
Maximum allowable drop-out during valid
DTMF signal.
t
DP
Time to detect the presence of valid
DTMF signals.
t
DA
Time to detect the absence of valid
DTMF signals.
t
GTP
Guard time, tone present.
t
GTA
Guard time, tone absent.
Timing Diagram
EVENTS
INTERDIGIT PAUSE
A
TOE
St/Gt
ESt
V
IN
DECODED TONE # N+1
TONE # N
TONE # N+1
TONE # N+1
DECODED TONE # N
HIGH IMPEDANCE
DECODED TONE # n+1
VTSt
tPTE
StD
OUTPUT
DATA
OUTPUTS
Q1-Q4
tPTD
tQStD
tPStD
tGTA
tGTP
tPQ
tDP
tREC
tREC
tDO TONE DROPOUT
tID
tDA
B
C
E
F
G
D
2001, 2002 California Micro Devices Corp. All rights reserved.
12/31/2001
5
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
CM88L70/70C
CALIFORNIA MICRO DEVICES
Functional Description
The CAMD CM88L70/70C DTMF Integrated Receiver
provides the design engineer with not only low power
consumption, but high performance in a small 18-pin
DIP, SOIC, or 20-pin PLCC, TSSOP, or QSOP package
configuration. The CM88L70/70C's internal architecture
consists of a bandsplit filter section which separates the
high and low tones of the received pair, followed by a
digital decode (counting) section which verifies both the
frequency and duration of the received tones before
passing the resultant 4-bit code to the output bus.
Filter Section
Separation of the low-group and high-group tones is
achieved by applying the dual-tone signal to the inputs of
two 9
th
-order switched capacitor bandpass filters. The
bandwidths of these filters correspond to the bands
enclosing the low-group and high-group tones (See
Figure 3). The filter section also incorporates notches at
350Hz and 440Hz which provides excellent dial tone
rejection. Each filter output is followed by a single order
switched capacitor section which smooths the signals
prior to limiting. Signal limiting is performed by high-gain
comparators. These comparators are provided with a
hysteresis to prevent detection of unwanted low-level
signals and noise. The outputs of the comparators
provide full-rail logic swings at the frequencies of the
incoming tones.
Decoder Section
The CM88L70/70C decoder uses a digital counting
technique to determine the frequencies of the limited
tones and to verify that these tones correspond to
standard DTMF frequencies. A complex averaging
algorithm is used to protect against tone simulation by
extraneous signals (such as voice) while providing
tolerance to small frequency variations. The averaging
algorithm has been developed to ensure an optimum
combination of immunity to "talk-off" and tolerance to the
presence of interfering signals (third tones) and noise.
When the detector recognizes the simultaneous pres-
ence of two valid tones (known as "signal condition"), it
raises the "Early Steering" flag (ESt). Any subsequent
loss of signal condition will cause ESt to fall.
Steering Circuit
Before the registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred to as
"character-recognition-condition"). This check is per-
formed by an external RC time constant driven by E
St
. A
logic high on ESt causes V
C
(See Figure 4) to rise as the
capacitor discharges. Providing signal condition is
maintained (ESt remains high) for the validation period
(t
GTP
), V
C
reaches the threshold (V
TSt
) of the steering logic
to register the tone pair, thus latching its corresponding
4-bit code (See Figure 2) into the output latch. At this
point, the GT output is activated and drives VC to V
DD
.
GT continues to drive high as long as ESt remains high,
signaling that a received tone pair has been registered.
The contents of the output latch are made available on
the 4-bit output bus by raising the three-state control
input (TOE) to a logic high. The steering circuit works in
reverse to validate the interdigit pause between signals.
Thus, as well as rejecting signals too short to be consid-
ered valid, the receiver will tolerate signal interruptions
(drop outs) too short to be considered a valid pause.
This capability together with the capability of selecting
the steering time constants externally, allows the de-
signer to tailor performance to meet a wide variety of
system requirements.
Guard Time Adjustment
In situations which do not require independent selection
of receive and pause, the simple steering circuit of
Figure 4 is applicable. Component values are chosen
according to the following formula:
t
REC
= t
DP
+ t
GTP
t
GTP
= 0.67 RC
The value of t
DP
is a parameter of the device and t
REC
is
the minimum signal duration to be recognized by the
receiver. A value for C of 0.1uF is recommended for most
applications, leaving R to be selected by the designer.
For example, a suitable value of R for a t
REC
of 40ms
would be 300K. A typical circuit using this steering
configuration is shown in Figure 1. The timing require-
ments for most telecommunication applications are
satisfied with this circuit. Different steering arrangements
may be used to select independently the guardtimes for
tone-present (t
GTP
) and tone absent (t
GTA
). This may be
necessary to meet system specifications which place
both accept and reject limits on both tone duration and
interdigit pause.
Guard time adjustment also allows the designer to tailor
system parameters such as talk-off and noise immunity.
Increasing t
REC
improves talk-off performance, since it
reduces the probability that tones simulated by speech
will maintain signal condition for long enough to be
registered. On the other hand, a relatively short t
REC
with
a long t
DO
would be appropriate for extremely noisy
environments where fast acquisition time and immunity
to drop-outs would be requirements. Design information
for guard time adjustment is shown in Figure 5.
Input Configuration
The input arrangement of the CM88L70/70C provides a
differential input operational amplifier as well as a bias
source (V
REF
) which is used to bias the inputs at mid-rail.
Provision is made for connection of a feedback resistor
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