12/18/2001

215 Topaz Street, Milpitas, California 95035

Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com

CM8870/70C

CALIFORNIA MICRO DEVICES

CMOS Integrated DTMF Receiver

Features

· Full DTMF receiver

· Less than 35mW power consumption

· Industrial temperature range

· Uses quartz crystal or ceramic resonators

· Adjustable acquisition and release times

· 18-pin DIP, 18-pin DIP EIAJ, 18-pin SOIC, 20-pin

PLCC

· CM8870C

-- Power down mode

-- Inhibit mode

-- Buffered OSC3 output (PLCC package only)

· CM8870C is fully compatible with CM8870 for 18-pin

devices by grounding pin 5 and pin 6.

Product Description

The CAMD CM8870/70C provides full DTMF receiver
capability by integrating both the band-split filter and
digital decoder functions into a single 18-pin DIP, SOIC,
or 20-pin PLCC package. The CM8870/70C is manufac-
tured using state-of-the-art CMOS process technology
for low power consumption (35mW, MAX) and precise
data handling. The filter section uses a switched capaci-
tor technique for both high and low group filters and dial

Applications

· PABX

· Central office

· Mobile radio

· Remote control

· Remote data entry

· Call limiting

· Telephone answering systems

· Paging systems

C1581000

tone rejection. The CM8870/70C decoder uses digital
counting techniques for the detection and decoding of all
16 DTMF tone pairs into a 4-bit code. This DTMF
receiver minimizes external component count by provid-
ing an on-chip differential input amplifier, clock genera-
tor, and a latched three-state interface bus. The on-chip
clock generator requires only a low cost TV crystal or
ceramic resonator as an external component.

Block Diagram

DIGITAL

DETECTION

ALGORITHM

ZERO

CROSSING DETECTORS

CODE

CONVERTER

AND

LATCH

IN+

IN

BIAS

CIRCUIT

CHIP

REF

CHP

BIAS

CHP

POWER

REF

StD

STEERING

LOGIC

DIAL

TONE

FILTER

HIGH

GROUP

FILTER

LOW

GROUP

FILTER

INH

TOE

ESt

OSC 1

OSC 2

OSC 3

TO ALL

CHIP

CLOCKS

St/GT

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CM8870/70C

CALIFORNIA MICRO DEVICES

Absolute Maximum Ratings

Symbol Parameter

Value

Power

Supply

Voltage (V

)

6V MAX

Vdc

Voltage on any Pin

0.3V to V

+ 0.3V

Current on any Pin

10mA MAX

Operating Temperature

40°C to 85°C

Storage Temperature

65°C to 150°C

Absolute Maximum Ratings: (Note 1)

This device contains input protection
against damage due to high static
voltages or electric fields; however,
precautions should be taken to avoid
application of voltages higher than the
maximum rating.
Notes:
1. Exceeding these ratings may cause

permanent damage, functional
operation under these conditions is
not implied.

DC Characteristics

Symbol

Parameter

Test Conditions

MIN

TYP

MAX

UNIT

Operating Supply Voltage

4.75

5.25

Operating Supply Current

3.0

7.0

DDQ

Standby Supply Current

PD = V

µA

Power Consumption

f = 3.579 MHz; V

= 5V

Low Level Input Voltage

= 5V

1.5

High Level Input Voltage

= 5V

3.5

IH/

Input Leakage Current

= V

(Note 1)

0.1

µA

Pull Up (Source) Current on TOE

TOE = 0V, V

= 5V

6.5

µA

Input Impedance, (IN+, IN) @

1KHz

Tst

Steering Threshold Voltage

= 5V

2.2

2.5

Low Level Output Voltage

= 5V, No Load

0.03

High Level Output Voltage

= 5V, No Load

4.97

Output Low (Sink) Current

OUT

= 0.4V

1.0

2.5

Output High (Source) Current

OUT

= 4.6V

0.4

0.8

REF

Output

Voltage

REF

= 5.0V, No Load

2.4 2.7 V

Output

Resistance

DC Characteristics: All voltages referenced to V

, V

= 5V ±5%, T

= 40°C to 85°C unless otherwise noted.

Operating Characteristics

Symbol

Parameter

Test Conditions

MIN

TYP

MAX

UNIT

Input

Leakage Current

< V

±100

Input

Resistance

Input Offset Voltage

±25

PSRR

Power Supply Rejection

1 KHz (Note 12)

CMRR

Common Mode Rejection

3V < V

< 3V

VOL

DC Open Loop Voltage Gain

Open Loop Unity Gain Bandwidth

0.3

MHz

Output

Voltage

Swing

100

KW to V

4 V

P-P

Maximum Capacitive Load (GS)

100

Maximum Resistive Load (GS)

Vcm

Common Mode Range (No Load)

No Load

2.5

P-P

Operating Characteristics: All voltages referenced to V

, V

= 5V ±5%, T

= 40°C to 85°C unless otherwise noted.

Gain Setting Amplifier

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CM8870/70C

CALIFORNIA MICRO DEVICES

AC Characteristics

Parameter

Notes

MIN

TYP

MAX

UNIT

Valid Input Signal Levels

1, 2, 3, 4, 5, 8

dBm

(each tone of composite signal)

27.5

869

RMS

Positive Twist Accept

2, 3, 4, 8

Negative

Twist

Freq. Deviation Aceept Limit

2, 3, 5, 8, 10

1.5%±2Hz

Norm.

Freq. Deviation Reject Limit

2, 3, 5

±3.5%

Norm.

Third Tone Tolerance

2, 3, 4, 5, 8, 9, 13, 14

16 dB

Noise Tolerance

2, 3, 4, 5, 6, 8, 9

12 dB

Dial Tone Tolerance

2, 3, 4,5, 7, 8, 9

Tone Present Detection Time

Refer to Timing Diagram

Tone Absent Dectection Time

Refer to Timing Diagram

0.5

8.5

REC

MIN Tone Duration Accept

MAX Tone Duration Reject

MIN Interdigit Pause Accept

MAX Interdigit Pause Reject

µs

Propagation Delay (St to Q)

TOE = V

µs

Propagation Delay (St to StD)

TOE = V

µs

Output Data Set Up (Q to StD)

TOE = V

3.4

µs

PTE

Propagation Delay (TOE to Q)

Enable R

= 10K

PTD

Disable

= 50pf

300

CLK

Crystal/Clock

Frequency

3.5759

3.5795 3.5831 MHz

Clock Ouput (OSC 2)

Capacitive Load

AC Characteristics: All voltages referenced to V

, V

= 5.0V ±5%, T

= 40°C to +85°C, f

CLK

= 3.579545 MHz

using test circuit in Figure 1 unless otherwise noted.

Notes:

1. dBm = decibels above or below a reference power

of 1mW into a 600

load.

2. Digit sequence consists of all 16 DTMF tones.
3. Tone duration = 40ms. Tone pause = 40ms.
4. Nominal DTMF frequencies are used.
5. Both tones in the composite signal have

an equal amplitude.

6. Bandwidth limited (0 to 3KHz) Gaussian Noise.
7. The precise dial tone frequencies are

(350Hz and 440Hz) ±2%.

8. For an error rate of better than 1 in 10,000

9. Referenced to lowest level frequency component

in DTMF signal.

10. Minimum signal acceptance level is measured with

specified maximum frequency deviation.

11. Input pins defined as IN+, IN, and TOE.
12. External voltage source used to bias V

REF

13. This parameter also applies to a third tone injected onto

the power supply.

14. Referenced to Figure 1. Input DTMF tone level

at 28dBm.

15. Times shown are obtained with circuit in

Figure 1 (User adjustable).

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CM8870/70C

CALIFORNIA MICRO DEVICES

EVENTS

INTERDIGIT PAUSE

TOE

St/Gt

ESt

DECODED TONE # N+1

TONE # N

TONE # N+1

DECODED TONE # N

HIGH IMPEDANCE

DECODED TONE # n+1

VTSt

tPTE

StD

OUTPUT

DATA

OUTPUTS

Q1-Q4

tPTD

tQStD

tPStD

tGTA

tGTP

tPQ

tDP

tREC

tDO TONE DROPOUT

tID

tDA

Explanation of Events

A. Tone bursts detected, tone duration invalid, outputs

not updated.

B. Tone #n detected, tone duration valid, tone decoded

and latched in outputs.

C. End of tone #n detected, tone absent duration valid,

outputs remain latched until next valid tone.

D. Outputs switched to high impedance state.

E. Tone #n + 1 detected, tone duration valid, tone

decoded and latched in outputs (currently high
impedance).

F. Acceptable dropout of tone #n + 1, tone absent

duration invalid, outputs remain latched.

G. End of tone #n + 1 detected, tone absent duration

valid, outputs remain latched until next valid tone.

Explanation of Symbols

DTMF composite input signal.

ESt

Early Steering Output. Indicates detection
of valid tone frequencies.

St/GT

Steering input/guard time output. Drives
external RC timing circuit.

Q1-Q4

4-bit decoded tone output.

StD

Delayed Steering Output. Indicates that
valid frequencies have been present/absent
for the required guard time, thus constituting

a valid signal.

TOE

Tone Output Enable (input). A low level
shifts Q1-Q4 to its high impedance state.

REC

Maximum DTMF signal duration not
detected as valid.

REC

Minimum DTMF signal duration required

for valid recognition.

Minimum time between valid DTMF signals.

Maximum allowable drop-out during valid
DTMF signal.

Time to detect the presence of valid
DTMF signals.

Time to detect the absence of valid
DTMF signals.

GTP

Guard time, tone present.

GTA

Guard time, tone absent.

Timing Diagram

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CM8870/70C

CALIFORNIA MICRO DEVICES

Functional Description

The CAMD CM8870/70C DTMF Integrated Receiver
provides the design engineer with not only low power
consumption, but high performance in a small 18-pin
DIP, SOIC, or 20-pin PLCC package configuration. The
CM8870/70C's internal architecture consists of a
band-split filter section which separates the high and low
tones of the received pair, followed by a digital decode
(counting) section which verifies both the frequency and
duration of the received tones before passing the
resultant 4-bit code to the output bus.

Filter Section

Separation of the low-group and high-group tones is
achieved by applying the dual-tone signal to the inputs of
two 9

-order switched capacitor bandpass filters. The

bandwidths of these filters correspond to the bands
enclosing the low-group and high-group tones (See
Figure 3). The filter section also incorporates notches at
350Hz and 440Hz which provides excellent dial tone
rejection. Each filter output is followed by a single order
switched capacitor section which smooths the signals
prior to limiting. Signal limiting is performed by high-gain
comparators. These comparators are provided with a
hysteresis to prevent detection of unwanted low-level
signals and noise. The outputs of the comparators
provide full-rail logic swings at the frequencies of the
incoming tones.

Decoder Section

The CM8870/70C decoder uses a digital counting
technique to determine the frequencies of the limited
tones and to verify that these tones correspond to
standard DTMF frequencies. A complex averaging
algorithm is used to protect against tone simulation by
extraneous signals (such as voice) while providing
tolerance to small frequency variations. The averaging
algorithm has been developed to ensure an optimum
combination of immunity to "talk-off" and tolerance to the
presence of interfering signals (third tones) and noise.
When the detector recognizes the simultaneous pres-
ence of two valid tones (known as "signal condition"), it
raises the "Early Steering" flag (ESt). Any subsequent
loss of signal condition will cause ESt to fall.

Steering Circuit

Before the registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred to as
"character-recognition-condition"). This check is per-
formed by an external RC time constant driven by E

. A

logic high on ESt causes V

(See Figure 4) to rise as the

capacitor discharges. Providing signal condition is
maintained (ESt remains high) for the validation period

GTP

), V

reaches the threshold (V

TSt

) of the steering logic

to register the tone pair, thus latching its corresponding
4-bit code (See Figure 2) into the output latch. At this
point, the GT output is activated and drives VC to V

GT continues to drive high as long as ESt remains high,
signaling that a received tone pair has been registered.
The contents of the output latch are made available on
the 4-bit output bus by raising the three-state control
input (TOE) to a logic high. The steering circuit works in
reverse to validate the interdigit pause between signals.
Thus, as well as rejecting signals too short to be consid-
ered valid, the receiver will tolerate signal interruptions
(drop outs) too short to be considered a valid pause.
This capability together with the capability of selecting
the steering time constants externally, allows the de-
signer to tailor performance to meet a wide variety of
system requirements.

Guard Time Adjustment

In situations which do not require independent selection
of receive and pause, the simple steering circuit of
Figure 4 is applicable. Component values are chosen
according to the following formula:

REC

= t

+ t

GTP

= 0.67 RC

The value of t

is a parameter of the device and t

REC

the minimum signal duration to be recognized by the
receiver. A value for C of 0.1µF is recommended for
most applications, leaving R to be selected by the
designer. For example, a suitable value of R for a t

REC

40ms would be 300K. A typical circuit using this steering
configuration is shown in Figure 1. The timing require-
ments for most telecommunication applications are
satisfied with this circuit. Different steering arrange-
ments may be used to select independently the
guard-times for tone-present (t

GTP

) and tone absent (t

GTA

This may be necessary to meet system specifications
which place both accept and reject limits on both tone
duration and interdigit pause.

Guard time adjustment also allows the designer to tailor
system parameters such as talk-off and noise immunity.
Increasing t

REC

improves talk-off performance, since it

reduces the probability that tones simulated by speech
will maintain signal condition for long enough to be
registered. On the other hand, a relatively short t

REC

with

a long t

would be appropriate for extremely noisy

environments where fast acquisition time and immunity
to drop-outs would be requirements. Design information
for guard time adjustment is shown in Figure 5.

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CM8870/70C

CALIFORNIA MICRO DEVICES

Input Configuration

The input arrangement of the CM8870/70C provides a
differential input operational amplifier as well as a bias
source (V

REF

) which is used to bias the inputs at mid-rail.

Provision is made for connection of a feedback resistor to
the op-amp output (GS) for adjustment of gain.

In a single-ended configuration, the input pins are con-
nected as shown in Figure 1, with the op-amp connected
for unity gain and VREF biasing the input at ½ V

. Figure

6 shows the differential configuration, which permits the
adjustment of gain with the feedback resistor R5.

Clock Circuit

The internal clock circuit is completed with the addition
of a standard television color burst crystal or ceramic
resonator having a resonant frequency of
3.579545MHz. The CM8870C in a PLCC package has a
buffered oscillator output (OSC3) that can be used to
drive clock inputs of other devices such as a micropro-
cessor or other CM887X's as shown in Figure 7. Mul-
tiple CM8870/70Cs can be connected as shown in figure
8 such that only one crystal or resonator is required.

Pin Function

Name

Function

Discription

IN+

Non-inverting input

Connection to the front-end differential amplifier

Inverting input

Connection to the front-end differential amplifier

Gain select

Gives access to output of front-end differential amplifier for connection

of feedback resistor.

REF

Reference output Voltage

May be used to bias the inputs at mid-rail.

(nominally V

/2)

INH

Inhibits detection of tones

Represents keys A, B, C, and D

OSC3

Digital buffered oscillator output

Power down

Logic high powers down the device and inhibits the oscillator.

OSC1

Clock input

3.579545MHz crystal connected between these pins

completes internal oscillator

OSC2

Clock output

3.579545MHz crystal connected between these pins

completes internal oscillator

Negative power supply

Normally connected to OV

TOE

Three-state output enable (Input) Logic high enables the outputs Q1-Q4. Internal pull-up.

Three-state ouputs

When enabled by TOE, provides the code corresponding to the last valid

tone pair received. (See Figure 2).

StD

Delayed Steering output

Presents a logic high when a received tone pair has been registered and the

output latch is updated. Returns to logic low shen the voltage on St/GT

falls below V

TSt

ESt

Early steering output

Presents logic high immediately when the digital algorithm detects a

recongnizable tone pair (signal condition). Any momentary loss of signal

condition will cause ESt to return to a logic low.

St/Gt

Steering input/guard

A voltage greater than V

TSt

detected at St causes the device to register

time output (bidirectional)

the dectected tone pair. The GT output acts to reset the external steering

time constrant, and its state is a function of ESt and the voltage on St.

(See Figure 2).

Positve power supply

Internal connection

Must be tied to V

(for 8870 configuration only).

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CM8870/70C

CALIFORNIA MICRO DEVICES

Figure 1. Single Ended Input Configuration

Functional Diode Table

LOW

HIGH

KEY

TOW

697

1209

697

1336

697

1477 3 H 0 0 1 1

770

1209

770

1336

770

1477

852

1209

852

1336 8

H 1 0 0 0

852

1477

941

1336

941

1209

941

1477

697

1633

770

1633

852

1633

941

1633

- ANY

L Z Z Z Z

L Logic Low, H = Logic, Z = High Impedance

Figure 2. Functional Decode Table

IN+

0.1µF

3.58

MHz

100K

300K

CM8870

IN

St/GT

ESt

REF

StD

INH

OSC 1

OSC 2

TOE

IN+

0.1µF

All resistors are ±1% tolerance.
All capacitors are ±5% tolerance.

3.58

MHz

100K

300K

CM8870C

IN

St/GT

ESt

REF

StD

INH

OSC 1

OSC 2

TOE

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CM8870/70C

CALIFORNIA MICRO DEVICES

TST

tGTA = (RC) In

St/GT

ESt

StD

DD 

TST

tGTP = (RC) In

Figure 4. Basic Steering Circuit

TST

tGTA = (R

C) In

1 +

TST

tGTP = (R

C) In

(A.) Decreasing tGTA (tGTP > tGTA)

St/GT

ESt

TST

tGTA = (R

C) In

+ R

VDD

 V

TST

tGTP = (R

C) In

(B.) Decreasing tGTP (tGTP < tGTA)

St/GT

ESt

Figure 5. Guard Time Adjustment

X Y

AB C D

FREQUENCY Hz

PRECISE DIAL TONES

DTMF TONES

TTENU

TION dB

E F

X = 350Hz
y = 440Hz

A = 607Hz

E = 1209Hz

B = 770Hz

F = 1336Hz

C = 852Hz

G = 1477Hz

D = 841Hz

H = 1633Hz

Figure 3. Typical Filter Characteristic

IN+

IN

CM8870

C1 = C2 = 10nF
R1 = R4 = R4 =100 K

R2 = 60K

, R3 = 37.5K

All resistors are 1% tolerance.
All capacitors are 5% tolerance.

(Xxxx) = 2

R2 +

VOLTAGE GAIN (Av diff) =

IMPUT IMPEDANCE

R3 =

R2R5

R2 + R5

DIFFERENTIAL INPUT AMPLIFIER

REF

R5
R1

Figure 6. Differential Input Configuration

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CM8870/70C

CALIFORNIA MICRO DEVICES

Figure 7. CM8870C Crystal Connection

(PLCC Package Only)

OSC1 OSC2 OSC3

Clock input of other devices

30pF

OSC1 of other CM887X's

OSC1 OSC2

3.58MHz

30pF

OSC1 OSC2

Figure 8. CM8870/70C Crystal Connection

Pin Assignments

IN+

IN

REF

IC*

OSC 1

OSC 2

St/GT

ESt

StD

TOE

CM8870

IN+

IN

REF

INH

IC*

OSC 1

OSC 2

St/GT

ESt

StD

TOE

CM8870C

REF

IC*

OSC 1

OSC 2

St/GT

ESt

StD

CM8870

REF

OSC 3

OSC 1

OSC 2

St/GT

ESt

StD

CM8870C

P Plastic DIP (18)

F Plastic SOP

EIAJ (18)

S SPIC (18)

P Plastic DIP (18)

F Plastic SOP

EIAJ (18)

S SOIC (18)

PE PLCC (20)

Connected to V

PE PLCC (20)

Ordering Information

CM8870

CM8870C

Product Identification Number

Example:

Package

P -- Plastic Dip (18)

F -- Plastic SOP EIAJ (18)

PE -- PLCC (20)

S -- SOIC (18)

Temperature/Processing

None -- 0°C to 70°C, ±5% P.S. Tol.

-- 40°C to 85°C, ±5% P.S. Tol.

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