1999 California Micro Devices Corp. All rights reserved.
1
11/99
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
PAC DN002
CALIFORNIA MICRO DEVICES
Diode Forward DC Current
(Note 1)
20mA
Storage Temperature
-65
C to 150
C
Operating Temperature Range
-20C to 85C
DC Voltage at any Channel Input V
N
-0.5V to V
P
+0.5V
Note 1: Only one diode conducting at a time.
17 CHANNEL ESD PROTECTION ARRAY
Features
17-channel ESD protection
8kV contact discharge ESD protection per
IEC 61000-4-2
15kV ESD protection (HBM)
Low loading capacitance, 5.5pF typ.
20-pin SOIC or QSOP package
Product Description
The PAC DN002 is a diode array designed to provide 17 channels of ESD protection for electronic components or
sub-systems. Each channel consists of a pair of diodes which steers the ESD current pulse either to the positive (V
P
) or
negative (V
N
) supply. The PAC DN002 will protect against ESD pulses up to 15KV Human Body Model.
This device is particularly well-suited to provide additional ESD protection for parallel printer ports. It exhibits low
loading capacitance for all signal lines.
Applications
Parallel printer port protection
ESD protection for sensitive
electronic equipment
Drop-in replacement for PDN 002
SCHEMATIC CONFIGURATION
Note 2: From I/O pins to V
P
or V
N
only. V
P
bypassed to V
N
with 0.2
F ceramic capacitor.
Note 3: Human Body Model per MIL-STD-883, Method 3015, C
Discharge
=100pF, R
Discharge
=1.5K
, V
P
=12V, V
N
=GND.
Note 4: This parameter is guaranteed by characterization.
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1
P/Active and PAC are trademarks of California Micro Devices.
ABSOLUTE MAXIMUM RATINGS
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1
1999 California Micro Devices Corp. All rights reserved.
11/99
PAC DN002
2
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
CALIFORNIA MICRO DEVICES
N
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When placing an order please specify desired shipping: Tubes or Tape & Reel.
Application Information
See also California Micro Devices Application note AP209, Design Considerations for ESD protection.
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize
parasitic series inductances to the Supply and Ground rails. Refer to Figure 1, which illustrates the case of a positive
ESD pulse applied between an input channel and Chassis Ground. The parasitic series inductance back to the power
supply is represented by L
1
. The voltage V
Z
on the line being protected is:
V
Z
= Forward voltage drop of D
1
+ L
1
x d(I
esd
)/dt + V
Supply
where I
esd
is the ESD current pulse, and V
Supply
is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC 61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1nS. Here d(I
esd
)/dt can be
approximated by I
esd
/t, or 30/(1x10
-9
). So just 10nH of series inductance (L
1
) will lead to a 300V increment in V
Z
!
Figure 1
Typical variation of C
IN
with V
IN
(V
P
= 12V, V
N
= 0V, 0.1F chip capacitor between V
P
& V
N
)
Input Capacitance vs. Input Voltage
2
3
4
5
6
7
8
9
10
11
12
0
2
4
6
8
10
12
Input Voltage (V)
Input Capacitance (pF
)
1999 California Micro Devices Corp. All rights reserved.
3
11/99
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
PAC DN002
CALIFORNIA MICRO DEVICES
Similarly for negative ESD pulses, parasitic series inductance from the V
N
pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies
exhibit a much higher output impedance to fast transient current spikes. In the V
Z
equation above, the V
Supply
term, in
reality, is given by (V
DC
+ I
esd
x R
out
), where V
DC
and R
out
are the nominal supply DC output voltage and effective output
impedance of the power supply respectively. As an example, a R
out
of 1 ohm would result in a 10V increment in V
Z
for a
peak I
esd
of 10A.
To mitigate these effects, a high frequency bypass capacitor should be connected between the V
P
pin of the ESD Protection
Array and the ground plane. The value of this bypass capacitor should be chosen such that it will absorb the charge
transferred by the ESD pulse with minimal change in V
P
. Typically a value in the 0.1 F to 0.2 F range is adequate for
IEC-61000-4-2 level 4 contact discharge protection (8KV). For higher ESD voltages, the bypass capacitor should be
increased accordingly. Ceramic chip capacitors mounted with short printed circuit board traces are good choices for this
application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics. For extra protection,
connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series inductance
inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the maximum supply
voltage.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V
P
pin of the
Protection Array as possible, with minimum PCB trace lengths to the power supply and ground planes to minimize stray
series inductance.
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