1999 California Micro Devices Corp. All rights reserved.
11/98
1
CALIFORNIA MICRO DEVICES
PAC DN017
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
Diode Forward DC Current
(Note 1)
40mA
Storage Temperature
-65
C to 150
C
Operating Temperature Range
-20C to 85C
DC Voltage at any Channel Input V
N
-0.5V to V
P
+0.5V
Note 1: Only one diode conducting at a time.
18 CHANNEL ESD PROTECTION ARRAY WITH ZENER SUPPLY CLAMP
Features
18-channel ESD protection
Integral Zener diode clamp to suppress
supply rail transients
15KV ESD protection (HBM)
15KV contact discharge ESD protection
per IEC 61000-4-2
Low loading capacitance, 7 pF typ.
24-pin QSOP package
Product Description
The PAC DN017 is a diode array designed to provide 18 channels of ESD protection for electronic components or
sub-systems. Each channel consists of a pair of diodes which steers the ESD current pulse either to the positive (V
P
) or
negative (V
N
) supply. In addition, there is an integral Zener diode between
V
P
and
V
N
to supress any voltage
disturbance due to these ESD pulses. The PAC DN017 will protect against ESD pulses up to 15 KV Human Body
Model, and 15KV contact discharge per International Standard IEC 61000-4-2.
Applications
Parallel printer port protection
ESD protection for sensitive
electronic equipment.
ABSOLUTE MAXIMUM RATINGS
SCHEMATIC CONFIGURATION
C0631199
Note 2: From I/O pins to V
P
or V
N
only. Bypass opacitor between V
P
and V
N
is not required. However, a 0.2 F ceramic chip capacitor
bypassing V
P
to V
N
is recommended if the lowest possible channel clamp voltage is desired.
Note 3: Human Body Model per MIL-STD-883, Method 3015, C
Discharge
=100pF, R
Discharge
=1.5K
, V
P
=5.0V, V
N
=GND.
Note 4: This parameter is guaranteed by characterization.
Note 5: Standard IEC 61000-4-2 with C
Discharge
=150pF, and R
Discharge
=330
, V
P
=5V, V
N
=GND.
P/Active
is a registered trademark and PAC is a trademark of California Micro Devices.
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1
This device is particularly well-suited to provide additional ESD protection for parallel printer ports. It exhibits low
loading capacitance for all signal lines.
1999 California Micro Devices Corp. All rights reserved.
11/98
2
CALIFORNIA MICRO DEVICES
PAC DN017
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
Application Information
See also California Micro Devices Application note AP209, Design Considerations for ESD protection.
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances to the Supply and Ground rails. Refer to Figure 1, which illustrates the case of a positive ESD pulse
applied between an input channel and Chassis Ground. The parasitic series inductance back to the power supply is
represented by L
1
. The voltage V
Z
on the line being protected is:
V
Z
= Forward voltage drop of D
1
+ L
1
x d(I
esd
)/dt + V
Supply
where I
esd
is the ESD current pulse, and V
Supply
is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per
the IEC 61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1nS. Here d(I
esd
)/dt can be
approximated by I
esd
/t, or 30/(1x10
-9
). So just 10nH of series inductance (L
1
) will lead to a 300V increment in V
Z
!
Figure 1
Input Capacitance vs. Input Voltage
C
IN
(pF)
V
IN
When placing an order please specify desired shipping: Tubes or Tape & Reel.
Typical variation of C
IN
with V
IN
(V
P
= 5V, V
N
= 0V, 0.1F chip capacitor between V
P
& V
N
)
T
S
R
A
D
N
A
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4
2
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S
Q
Q
7
1
0
N
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C
A
P
1999 California Micro Devices Corp. All rights reserved.
11/98
3
CALIFORNIA MICRO DEVICES
PAC DN017
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
Similarly for negative ESD pulses, parasitic series inductance from the V
N
pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies
exhibit a much higher output impedance to fast transient current spikes. In the V
Z
equation above, the V
Supply
term, in
reality, is given by (V
DC
+ I
esd
x R
out
), where V
DC
and R
out
are the nominal supply DC output voltage and effective output
impedance of the power supply respectively. As an example, a R
out
of 1 ohm would result in a 10V increment in V
Z
for a
peak I
esd
of 10A.
To mitigate these effects, a Zener diode has been integrated into this Protection Array between V
P
and V
N
. This Zener
diode clamps the maximum voltage of V
P
relative to V
N
at the breakdown voltage of the Zener diode. Although not strictly
necessary, it is recommended that V
P
be bypassed to the ground plane with a high frequency bypass capacitor. This will
lower the channel clamp voltage, and is especially effective when V
P
is much lower than the Zener breakdown voltage.
The value of this bypass capacitor should be chosen such that it will absorb the charge transferred by the ESD pulse with
minimal change in V
P
. Typically a value in the 0.1 F to 0.2 F range is adequate for IEC-61000-4-2 level 4 contact
discharge protection (8KV). For higher ESD voltages, the bypass capacitor should be increased accordingly. Ceramic chip
capacitors mounted with short printed circuit board traces are good choices for this application. Electrolytic capacitors
should be avoided as they have poor high frequency characteristics.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V
P
pin of the
Protection Array as possible, with minimum PCB trace lengths to the power supply and ground planes to minimize stray
series inductance.
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