2000 California Micro Devices Corp. All rights reserved.
6/19/2000
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
1
CALIFORNIA MICRO DEVICES
CALIFORNIA MICRO DEVICES
CALIFORNIA MICRO DEVICES
CALIFORNIA MICRO DEVICES
CALIFORNIA MICRO DEVICES
PACDN1408C
PACDN2408C
ESD PROTECTION ARRAY, 8 CHANNEL, CHIP SCALE PACKAGE
Features
8 transient voltage suppressors in a single chip
scale wafer level package.
Compact Chip Scale Package (CSP) format
saves board space and ease layout in space
critical applications compared to discrete
solutions and traditional wire bonded packages.
In-system Electro Static Discharge (ESD)
protection to 20kV contact discharge per
IEC 61000-4-2 international standard.
PACDN2408C features back-to-back zener
protection for AC signals.
Product Description
The PACDN1408C and PACDN2408C are transient
voltage suppressor arrays that provide a very high
level of protection for sensitive electronic components
that may be subjected to ESD. The back-to-back zener
connections of the PACDN2408C provides ESD
protection in cases where nodes with AC signals are
present.
These devices are designed and characterized to
safely dissipate ESD strikes at levels well beyond the
maximum requirements set forth in the IEC 61000-4-2
international standard (Level 4, 8kV contact dis-
Applications
ESD protection of cellular phones, PDA, internet
appliances and PC ports.
Protection of interface ports or IC pins which are
exposed to high levels of ESD.
PACDN2408C can be used for ESD protection of
set-top box R,L,V ports.
C1130600
charge). All I/Os are rated at 20kV using the IEC
61000-4-2 contact discharge method. Using the MIL-
STD-883D (Method 3015) specification for Human
Body Model (HBM) ESD, all pins are protected for
contact discharges to greater than 30kV.
The Chip Scale Package format of these devices
enable extremely small footprints that are necessary in
portable electronics such as cellular phones, PDAs,
internet appliances and PCs. The large solder bumps
allow for standard attachment to laminate boards
without the use of underfill.
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SCHEMATIC DIAGRAMS
A1 A2
A3 A4 A5
B1 B2 B3 B4 B5
PACDN1408C
A1 A2
A3 A4 A5
B1 B2 B3 B4 B5
PACDN2408C
2000 California Micro Devices Corp. All rights reserved.
6/19/2000
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
2
CALIFORNIA MICRO DEVICES
CALIFORNIA MICRO DEVICES
CALIFORNIA MICRO DEVICES
CALIFORNIA MICRO DEVICES
CALIFORNIA MICRO DEVICES
PACDN1408C
PACDN2408C
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* ESD applied between channel pin and common, one at a time. All other channels are open. This parameter is guaranteed by
design and characterization.
* ESD applied between channel pin and ground, one at a time. All other channels are open. All GND pins grounded. This
parameter is guaranteed by design and characterization.
`GND' in this document refers to the lower supply voltage.
2000 California Micro Devices Corp. All rights reserved.
6/19/2000
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
3
CALIFORNIA MICRO DEVICES
CALIFORNIA MICRO DEVICES
CALIFORNIA MICRO DEVICES
CALIFORNIA MICRO DEVICES
CALIFORNIA MICRO DEVICES
PACDN1408C
PACDN2408C
Package Diagram
Pin Orientation
Both parts are symmetrical, and do not require orientation to pin-1 found in conventional semiconductors. The part
may rotated 180 without affecting operation.
3.104mm
1.
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m
1 2 3 4 5
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B
0.381mm
0.643mm
0.252mm
0.65mm
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m
0.35mm dia.
Bumps
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Typical Solder Reflow Thermal Profile (No Clean Flux)
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