DESCRIPTION
The CAT1021, CAT1022 and CAT1023 are complete
memory and supervisory solutions for microcontroller-
based systems. A 2k-bit serial EEPROM memory and a
system power supervisor with brown-out protection are
integrated together in low power CMOS technology.
Memory interface is via a 400kHz I
2
C bus.
The CAT1021 and CAT1023 provide a precision V
CC
sense circuit and two open drain outputs: one (RESET)
drives high and the other (
RESET
) drives low whenever
V
CC
falls below the reset threshold voltage. The CAT1022
has only a
RESET
output and does not have a Write
Protect input. The CAT1021 also has a Write Protect
input (WP). Write operations are disabled if WP is
connected to a logic high.
All supervisors have a 1.6 second watchdog timer circuit
that resets a system to a known state if software or a
hardware glitch halts or "hangs" the system. For the
CAT1021 and CAT1022, the watchdog timer monitors
the SDA signal. The CAT1023 has a separate watchdog
timer interrupt input pin, WDI.
CAT1021, CAT1022, CAT1023
Supervisory Circuits with I
2
C Serial 2k-bit CMOS EEPROM, Manual Reset
and Watchdog Timer
FEATURES
s
Precision power supply voltage monitor
-- 5V, 3.3V and 3V systems
-- Five threshold voltage options
s
Watchdog timer
s
Active high or low reset
-- Valid reset guaranteed at V
CC
= 1 V
s
400kHz I
2
C bus
s
2.7V to 5.5V operation
s
Low power CMOS technology
s
16-Byte page write buffer
s
Built-in inadvertent write protection
-- WP pin (CAT1021)
s
1,000,000 Program/Erase cycles
s
Manual reset input
s
100 year data retention
s
8-pin DIP, SOIC, TSSOP, MSOP or TDFN
(3 x 4.9 mm & 3 x 3 mm foot-print) packages
-- TDFN max height is 0.8mm
s
Industrial and extended temperature ranges
2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 3009, Rev. H
The power supply monitor and reset circuit protect memory
and system controllers during power up/down and against
brownout conditions. Five reset threshold voltages support
5V, 3.3V and 3V systems. If power supply voltages are out
of tolerance reset signals become active, preventing the
system microcontroller, ASIC or peripherals from operating.
Reset signals become inactive typically 200 ms after the
supply voltage exceeds the reset threshold level. With both
active high and low reset signals, interface to microcontrollers
and other ICs is simple. In addition, the
RESET
pin or a
separate input,
MR
, can be used as an input for push-button
manual reset capability.
The on-chip, 2k-bit EEPROM memory features a 16-byte
page. In addition, hardware data protection is provided by a
V
CC
sense circuit that prevents writes to memory whenever
V
CC
falls below the reset threshold or until V
CC
reaches the
reset threshold during power up.
Available packages include an 8-pin DIP and surface mount
8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin MSOP
packages. The TDFN package thickness is 0.8mm maximum.
TDFN footprint options are 3x3mm or 3x4.9mm (MSOP pad
layout).
HA
LOGEN FREE
TM
LEAD FREE
2
CAT1021, CAT1022, CAT1023
Doc. No. 3009, Rev. H
BLOCK DIAGRAM
Part Dash Minimum
Maximum
Number Threshold
Threshold
-45
4.50
4.75
-42
4.25
4.50
-30
3.00
3.15
-28
2.85
3.00
-25
2.55
2.70
Threshold Voltage Options
PIN CONFIGURATION
(Bottom View)
TDFN Package: 3mm x 4.9mm
0.8mm maximum height - (RD2, ZD2)
(Bottom View)
TDFN Package: 3mm x 3mm
0.8mm maximum height - (RD4, ZD4)
MR
VCC
RESET
SCL
SDA
RESET
WP
VSS
CAT1021
1
2
3
4
8
7
6
5
MR
VCC
NC
SCL
SDA
RESET
NC
VSS
CAT1022
1
2
3
4
8
7
6
5
MR
VCC
SCL
SDA
RESET
VSS
CAT1023
1
2
3
4
8
7
6
5
VCC
WDI
RESET
1
2
3
4
8
7
6
5
VCC
RESET
SCL
SDA
MR
RESET
WP
VSS
CAT1021
1
2
3
4
8
7
6
5
VCC
NC
SCL
SDA
MR
RESET
NC
VSS
CAT1022
1
2
3
4
8
7
6
5
CAT1023
VCC
WDI
SCL
SDA
MR
RESET
RESET
VSS
1
2
3
4
8
7
6
5
VCC
NC
SCL
SDA
MR
RESET
NC
VSS
CAT1022
1
2
3
4
8
7
6
5
VCC
WDI
SCL
SDA
MR
RESET
RESET
VSS
CAT1023
1
2
3
4
8
7
6
5
VCC
RESET
SCL
SDA
MR
RESET
WP
VSS
CAT1021
2kbit
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
EEPROM
VCC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
VSS
SDA
RESET Controller
Precision
Vcc Monitor
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
SCL
RESET
RESET
MR
WP
(CAT1021)
(CAT1021/23)
WDI
(CAT1023)
DIP Package (P, L)
SOIC Package (S, V)
TSSOP Package (U, Y)
MSOP Package (R, Z)
3
CAT1021, CAT1022, CAT1023
Doc No. 3009, Rev. H
PIN DESCRIPTION
RESET/
RESET
RESET
RESET
RESET
RESET:
RESET OUTPUTS
(RESET CAT1021/23 Only)
These are open drain pins and
RESET
can be used as a
manual reset trigger input. By forcing a reset condition on
the pin the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull-down
resistor, and the
RESET
pin must be connected through a
pull-up resistor.
SDA:
SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire-ORed with other open drain
or open collector outputs.
SCL:
SERIAL CLOCK
Serial clock input.
PIN FUNCTIONS
Pin Name
Function
NC
No Connect
RESET
Active Low Reset Input/Output
V
SS
Ground
SDA
Serial Data/Address
SCL
Clock Input
RESET
Active High Reset Output (CAT1021/23)
V
CC
Power Supply
WP
Write Protect (CAT1021 only)
MR
Manual Reset Input
WDI
Watchdog Timer Interrupt (CAT1023)
CAT102X FAMILY OVERVIEW
For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163
data sheets.
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2
OPERATING TEMPERATURE RANGE
Industrial
-40C to 85C
Extended
-40C to 125C
MR:
MR:
MR:
MR:
MR:
MANUAL RESET INPUT
Manual Reset input is a debounced input that can be
connected to an external source for Manual Reset.
Pulling the MR input low will generate a Reset condition.
Reset outputs are active while
MR
input is low and for
the reset timeout period after
MR
returns to high. The
input has an internal pull up resistor.
WP (CAT1021 Only):
WRITE PROTECT INPUT
When WP input is tied to V
SS
or left unconnected write
operations to the entire array are allowed. When tied to
V
CC
, the entire array is protected. This input has an
internal pull down resistor.
WDI (CAT1023 Only):
WATCHDOG TIMER INTERRUPT
Watchdog Timer Interrupt Input is used to reset the
watchdog timer. If a transition from high to low or low to
high does not occur every 1.6 seconds, the RESET
outputs will be driven active.
4
CAT1021, CAT1022, CAT1023
Doc. No. 3009, Rev. H
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................. 55
C to +125
C
Storage Temperature ....................... 65
C to +150
C
Voltage on any Pin with
Respect to Ground
(1)
........... 2.0 V to V
CC
+ 2.0 V
V
CC
with Respect to Ground ................ 2.0V to 7.0 V
Package Power Dissipation
Capability (T
A
= 25
C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300
C
Output Short Circuit Current
(2)
........................ 100 mA
Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Note:
(1) The minimum DC input voltage is 0.5V. During transitions,
inputs may undershoot to
2.0V for periods of less than 20 ns. Maximum DC voltage on
output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V
for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than
one output shorted at a time.
Notes:
1.
V
IL
min and V
IH
max are reference values only and are not tested.
2.
This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
DC OPERATING CHARACTERISTICS
V
CC
= 2.7V to 5.5V and over the recommended temperature conditions unless otherwise specified.
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CAT1021, CAT1022, CAT1023
Doc No. 3009, Rev. H
CAPACITANCE
T
A
= 25
C, f = 1.0 MHz, V
CC
= 5V
SymbolTest
Test Conditions
Max
Units
C
OUT
(1)
Output Capacitance
V
OUT
= 0V
8
pF
C
IN
(1)
Input Capacitance
V
IN
= 0V
6
pF
AC CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Notes:
1.
This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
2.
Test Conditions according to "AC Test Conditions" table.
3.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
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