Central
Semiconductor Corp.
TM
PROCESS
CP307
Small Signal Transistor
NPN - Silicon Darlington Transistor Chip
PRINCIPAL DEVICE TYPES
2N6426
2N6427
CMPT6427
CMPTA13
CMPTA14
CXTA14
CZTA14
MPSA13
MPSA14
Process
EPITAXIAL PLANAR
Die Size
27 x 27 MILS
Die Thickness
9.0 MILS
Base Bonding Pad Area
5.3 x 3.8 MILS
Emitter Bonding Pad Area
5.3 x 6.5 MILS
Top Side Metalization
Al - 30,000
Back Side Metalization
Au - 18,000
PROCESS DETAILS
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
BACKSIDE COLLECTOR
GEOMETRY
R3 (1-August 2002)
GROSS DIE PER 4 INCH WAFER
15,440
Central
Semiconductor Corp.
TM
Central
Semiconductor Corp.
TM
PROCESS
CP307
Typical Electrical Characteristics
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
R3 (1-August 2002)
Central
Semiconductor Corp.
TM
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