Central
Semiconductor Corp.
TM
PROCESS
CP316
Small Signal Transistor
NPN - High Voltage Transistor Chip
PRINCIPAL DEVICE TYPES
CMPT5551
CXT5551
CZT5551
2N5551
Process
EPITAXIAL PLANAR
Die Size
20 x 20 MILS
Die Thickness
9.0 MILS
Base Bonding Pad Area
4.0 x 4.0 MILS
Emitter Bonding Pad Area
4.7 x 4.7 MILS
Top Side Metalization
Al - 30,000
Back Side Metalization
Au - 18,000
PROCESS DETAILS
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
BACKSIDE COLLECTOR
GEOMETRY
R2 (1-August 2002)
GROSS DIE PER 4 INCH WAFER
29,250
Central
Semiconductor Corp.
TM
PROCESS
CP316
Typical Electrical Characteristics
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
R2 (1-August 2002)
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