Central
Semiconductor Corp.
TM
PROCESS
CP547
Power Transistor
PNP - Darlington Chip
PRINCIPAL DEVICE TYPES
MJ11011 2N6285
MJ11013 2N6286
MJ11015 2N6287
Process
EPITAXIAL BASE
Die Size
195 X 195 MILS
Die Thickness
12 MILS
Base Bonding Pad Area
29 X 29 MILS
Emitter Bonding Pad Area
61 X 35 MILS
Top Side Metalization
AI - 30,000
Back Side Metalization
Ti/Ni/Au - 6,000
PROCESS DETAILS
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
GEOMETRY
BACKSIDE COLLECTOR
R3 (1-August 2002)
GROSS DIE PER 5 INCH WAFER
290
Central
Semiconductor Corp.
TM
PROCESS
CP547
Typical Electrical Characteristics
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
R3 (1-August 2002)
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