Central
Semiconductor Corp.
TM
PROCESS
CP667
Small Signal Transistor
PNP- Saturated Switch Transistor Chip
PRINCIPAL DEVICE TYPES
2N3467
2N3468
GEOMETRY
PROCESS DETAILS
BACKSIDE COLLECTOR
R1 (1-August 2002)
Process
EPITAXIAL PLANAR
Die Size
31 x 31 MILS
Die Thickness
9.0 MILS
Base Bonding Pad Area
5.9 x 11.8 MILS
Emitter Bonding Pad Area
6.5 x 13.8 MILS
Top Side Metalization
Al - 30,000
Back Side Metalization
Au - 15,000
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
GROSS DIE PER 4 INCH WAFER
11,300
Central
Semiconductor Corp.
TM
PROCESS
CP667
Typical Electrical Characteristics
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
R1 (1-August 2002)
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