PROCESS
CP741V
Small Signal Transistors
PNP - Low VCE(SAT) Transistor Chip
PRINCIPAL DEVICE TYPES
CMLT7410
CMPT7410
CMST7410
CMUT7410
Process
Epitaxial Planar
Die Size
18 x 18 MILS
Die Thickness
7.1 MILS
Base Bonding Pad Area
3.8 x 3.8 MILS
Emitter Bonding Pad Area
3.8 x 3.8 MILS
Top Side Metalization
Al/Si - 30,000
Back Side Metalization
Au - 12,000
PROCESS DETAILS
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel:
(631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
GEOMETRY
R0 (5- January 2006)
GROSS DIE PER 5 INCH WAFER
54,330
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