Features
s
Synchronous Switching
Regulator Controller for
CPU V
CORE
s
Dual N-Channel MOSFET
Synchronous Buck Design
s
V
2
TM
Control Topology
s
200ns Transient Loop
Response
s
5-bit DAC with 1.2% Tolerance
s
Hiccup Mode Overcurrent
Protection
s
40ns Gate Rise and Fall Times
(3.3nF load)
s
65ns Adaptive FET
Non-overlap Time
s
Adaptive Voltage Positioning
s
Power-Good Output Monitors
Regulator Output
s
V
CC
Monitor Provides Under
Voltage Lockout
s
Enable Through use of the
COMP pin
Package Options
CS51311
Synchronous CPU Buck Controller
for 12V and 5V Applications
CS51311
Description
Application Diagram
V
OUT
VID0
VID1
VID2
VID3
V
CC
VID4
V
FB
COMP
C
OFF
PWRGD
Gnd
GATE(L)
GATE(H)
1
14 Lead SO Narrow
1
Pentium is a registered trademark of Intel Corporation.
A Company
V
2
is a trademark of Switch Power, Inc.
Rev. 3/11/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
The CS51311 is a synchronous dual
NFET Buck Regulator Controller. It is
designed to power the core logic of
the latest high performance CPUs. It
uses the V
2
TM
control method to
achieve the fastest possible transient
response and best overall regulation.
It incorporates many additional fea-
tures required to ensure the proper
operation and protection of the CPU
and Power system. The CS51311 pro-
vides the industry's most highly inte-
grated solution, minimizing external
component count, total solution size,
and cost.
The CS51311 is specifically designed
to power Intel's Pentium
II processor
and includes the following features:
5-bit DAC with 1.2% tolerance,
Power-Good output, over-current
hiccup mode protection, V
CC
monitor,
soft start, adaptive voltage position-
ing, adaptive FET non-overlap time,
and remote sense. The CS51311 will
operate over an 8.4V to 14V range
and is available in 14 lead narrow
body surface mount package.
680pF
GATE(H)
GATE(L)
V
FB
V
OUT
10K
1200
F/10V
x3
3.3m
1.2
H
FS70VSJ-03
FS70VSJ-03
510
0.1
F
510
1200
F/10V
x5
V
CC(CORE)
2.0V@19A
+5V
+12V
VID0
VID1
VID2
VID3
VID4
PWRGD
C
OFF
Gnd
V
CC
COMP
PWRGD
0.01
F
1
F
100
0.1
F
2
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
Absolute Maximum Ratings
Pin Symbol
Pin Name
V
MAX
V
MIN
I
SOURCE
I
SINK
CS51311
Operating Junction Temperature, T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C
Lead Temperature Soldering
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 sec. max above 183C, 230C peak
Storage Temperature Range, T
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C
ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
V
CC
IC Power Input
16V
-0.3V
N/A
1.5 APeak
200mA DC
COMP
Compensation Pin
6V
-0.3V
1mA
5mA
V
FB
, V
OUT
, V
ID0-4
Voltage Feedback Input, Output
6V
-0.3V
1mA
1mA
Voltage Sense Pin, Voltage
ID DAC Inputs
C
OFF
Off-Time Pin
6V
-0.3V
1mA
50mA
GATE(H), GATE(L) High-Side, Low-Side FET Drivers
16V
-0.3V DC
1.5APeak
1.5A Peak
200mA DC
200mA DC
PWRGD
Power-Good Output
6V
-0.3V
1mA
30mA
Gnd
Ground
0V
0V
1.5A Peak
N/A
200mA DC
1,2,3,4,5
V
IDO
V
ID4
Voltage ID DAC inputs. These pins are internally pulled up to
5.65V if left open. V
ID4
selects the DAC range. When V
ID4
is
high (logic one), the Error Amp reference range is 2.125V to
3.525V with 100mV increments. When V
ID4
is low (logic zero),
the Error amp reference voltage is 1.325V to 2.075V with 50mV
increments.
6
V
FB
Error amp inverting input, PWM comparator non-inverting
input, current limit comparator non-inverting input, PWRGD
comparator input.
7
V
OUT
Current limit comparator inverting input.
8
V
CC
Input power supply pin for the internal circuitry.
Decouple with filter capacitor to Gnd.
9
GATE(H)
High side switch FET driver pin .
10
Gnd
Ground pin.
11
GATE(L)
Low side synchronous FET driver pin.
12
PWRGD
Power-Good Output. Open collector output drives low when
V
FB
is out of regulation.
13
C
OFF
Off-Time Capacitor Pin. A capacitor from this pin to Gnd sets
the off time for the regulator
14
COMP
Error amp output. PWM comparator inverting input.
A capacitor on this pin provides error amp compensation.
Electrical Characteristics: 0C < T
A
< 70C; 0C < T
J
< 125C; 9V < V
CC
< 14V;
2.0V DAC Code (V
ID4
= V
ID3
=V
ID2
= V
ID1
= 0, V
ID0
= 1), C
GATE(H)
= C
GATE(L)
= 3.3nF, C
OFF
= 390pF; Unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3
CS51311
75C T
J
125C
25C T
J
75C
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
MIN
TYP
MAX
TOL
MIN
TYP
MAX
TOL
UNIT
1
0
0
0
0
3.483
3.525
3.567
1.2%
3.455
3.525
3.596
2.0%
V
1
0
0
0
1
3.384
3.425
3.466
1.2%
3.357
3.425
3.494
2.0%
V
1
0
0
1
0
3.285
3.325
3.365
1.2%
3.259
3.325
3.392
2.0%
V
1
0
0
1
1
3.186
3.225
3.264
1.2%
3.161
3.225
3.290
2.0%
V
1
0
1
0
0
3.087
3.125
3.163
1.2%
3.063
3.125
3.188
2.0%
V
1
0
1
0
1
2.989
3.025
3.061
1.2%
2.965
3.025
3.086
2.0%
V
1
0
1
1
0
2.890
2.925
2.960
1.2%
2.875
2.925
2.975
1.7%
V
1
0
1
1
1
2.791
2.825
2.859
1.2%
2.777
2.825
2.873
1.7%
V
1
1
0
0
0
2.692
2.725
2.758
1.2%
2.679
2.725
2.771
1.7%
V
1
1
0
0
1
2.594
2.625
2.657
1.2%
2.580
2.625
2.670
1.7%
V
1
1
0
1
0
2.495
2.525
2.555
1.2%
2.482
2.525
2.568
1.7%
V
1
1
0
1
1
2.396
2.425
2.454
1.2%
2.389
2.425
2.461
1.5%
V
1
1
1
0
0
2.297
2.325
2.353
1.2%
2.290
2.325
2.360
1.5%
V
1
1
1
0
1
2.198
2.225
2.252
1.2%
2.192
2.225
2.258
1.5%
V
1
1
1
1
0
2.099
2.125
2.151
1.2%
2.093
2.125
2.157
1.5%
V
0
0
0
0
0
2.050
2.075
2.100
1.2%
2.044
2.075
2.106
1.5%
V
0
0
0
0
1
2.001
2.025
2.049
1.2%
1.995
2.025
2.055
1.5%
V
0
0
0
1
0
1.953
1.975
1.997
1.1%
1.945
1.975
2.005
1.5%
V
0
0
0
1
1
1.904
1.925
1.946
1.1%
1.896
1.925
1.954
1.5%
V
0
0
1
0
0
1.854
1.875
1.896
1.1%
1.847
1.875
1.903
1.5%
V
0
0
1
0
1
1.805
1.825
1.845
1.1%
1.798
1.825
1.852
1.5%
V
0
0
1
1
0
1.755
1.775
1.795
1.1%
1.748
1.775
1.802
1.5%
V
0
0
1
1
1
1.706
1.725
1.744
1.1%
1.699
1.725
1.751
1.5%
V
0
1
0
0
0
1.656
1.675
1.694
1.1%
1.650
1.675
1.700
1.5%
V
0
1
0
0
1
1.607
1.625
1.643
1.1%
1.601
1.625
1.649
1.5%
V
0
1
0
1
0
1.558
1.575
1.593
1.1%
1.551
1.575
1.599
1.5%
V
0
1
0
1
1
1.508
1.525
1.542
1.1%
1.502
1.525
1.548
1.5%
V
0
1
1
0
0
1.459
1.475
1.491
1.1%
1.453
1.475
1.497
1.5%
V
0
1
1
0
1
1.409
1.425
1.441
1.1%
1.404
1.425
1.446
1.5%
V
0
1
1
1
0
1.360
1.375
1.390
1.1%
1.354
1.375
1.396
1.5%
V
0
1
1
1
1
1.310
1.325
1.340
1.1%
1.305
1.325
1.345
1.5%
V
1
1
1
1
1
1.225
1.250
1.275
2.0%
1.225
1.250
1.275
2.0%
V
s
Voltage Identification DAC
Measure V
FB
= V
COMP
, V
CC
= 12V (Note 1)
s
Error Amplifier
V
FB
Bias Current
0.2V V
FB
3.5V
-7.0
0.1
7.0
A
COMP Source Current
V
COMP
= 1.2V to 3.6V; V
FB
= 1.9 V
15
30
60
A
COMP Sink Current
V
COMP
=1.2V; V
FB
= 2.1V;
30
60
120
A
Open Loop Gain
C
COMP
= 0.1F
80
dB
Unity Gain Bandwidth
C
COMP
= 0.1F
50
kHz
PSRR @ 1kHz
C
COMP
= 0.1F
70
dB
Transconductance
32
mmho
Output Impedance
0.5
M
Electrical Characteristics: 0C < T
A
< 70C; 0C < T
J
< 125C; 9V < V
CC
< 14V;
2.0V DAC Code (V
ID4
= V
ID3
=V
ID2
= V
ID1
= 0, V
ID0
= 1), C
GATE(H)
= C
GATE(L)
= 3.3nF, C
OFF
= 390pF; Unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4
CS51311
Line Regulation
9V V
CC
14V
0.01
%/V
Input Threshold
V
ID4
, V
ID3
, V
ID2
, V
ID1
, V
ID0
1.00
1.25
2.40
V
Input Pull-up Resistance
V
ID4
, V
ID3
, V
ID2
, V
ID1
, V
ID0
25
50
100
k
Pull-up Voltage
5.48
5.65
5.82
V
s
GATE(H) and GATE(L)
High Voltage at 100mA
Measure V
CC
GATE(L)/(H)
1.2
2.1
V
Low Voltage at 100mA
Measure GATE(L)/(H)
1.0
1.5
V
Rise Time
1.6V < GATE(H)/(L) < (V
CC
2.5V)
40
80
ns
Fall Time
(V
CC
2.5V) > GATE(L)/(H) > 1.6V
40
80
ns
GATE(H) to GATE(L) Delay
GATE(H) < 2V, GATE(L) > 2V
30
65
110
ns
V
CC
= 12V
GATE(L) to GATE(H) Delay
GATE(L) < 2V, GATE(H) > 2V
30
65
110
ns
V
CC
= 12V
GATE pull-down
Resistance to Gnd (Note 2)
20
50
115
k
s
Overcurrent Protection
OVC Comparator Offset Voltage
0V V
OUT
3.5V
77
86
101
mV
Discharge Threshold Voltage
0.2
0.25
0.3
V
V
OUT
Bias Current
0.2V V
OUT
3.5V
-7.0
0.1
7.0
A
OVC Latch Discharge Current
V
COMP
= 1V
100
800
2500
A
s
PWM Comparator
PWM Comparator Offset Voltage
0V V
FB
3.5V
0.99
1.10
1.23
V
Transient Response
V
FB
= 0 to 3.5V
200
300
ns
s
C
OFF
Off-Time
1.0
1.6
2.3
s
Charge Current
V
COFF
= 1.5V
550
A
Discharge Current
V
COFF
= 1.5V
25
mA
s
Power-Good Output
PWRGD Sink Current
V
FB
= 1.7V, V
PWRGD
= 1V
0.5
4
15
mA
PWRGD Upper Threshold
% of nominal DAC code
5
8.5
12
%
PWRGD Lower Threshold
% of nominal DAC code
-12
-8.5
-5
%
PWRGD Output Low Voltage
V
FB
= 1.7V, I
PWRGD
= 500A
0.2
0.3
V
CS51311
5
Electrical Characteristics: 0C < T
A
< 70C; 0C < T
J
< 125C; 9V < V
CC
< 14V;
2.0V DAC Code (V
ID4
= V
ID3
=V
ID2
= V
ID1
= 0, V
ID0
= 1), C
GATE(H)
= C
GATE(L)
= 3.3nF, C
OFF
= 390pF; Unless otherwise stated.
+
-
+
-
+
-
V
FB
COMP
C
OFF
OFF
TIME
PWM COMP
DISCHARGE
COMP
+
-
V
OUT
V
ID0
V
ID1
V
ID2
V
ID3
V
ID4
DAC
+
-
+
-
+
-
1.1V
EA
CURRENT LIMIT
+
-
86mV
0.25V
FAULT
LATCH
R
S
Q
PWRGD
Gnd
GATE(L)
GATE(H)
V
CC
UVLO
NONOVERLAP
LOGIC
+
-
Block Diagram
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s
General Electrical Specifications
V
CC
Monitor Start Threshold
7.9
8.4
8.9
V
V
CC
Monitor Stop Threshold
7.6
8.1
8.6
V
Hysteresis
Start - Stop
0.15
0.30
0.60
V
V
CC
Supply Current
No Load on GATE(H), GATE(L)
12
20
mA
Note 1: The IC power dissipation in a typical application with V
CC
= 12V, switching frequency f
SW
= 250kHz, 50nc
MOSFETs and R
JA
= 115C/W yields an operating junction temperature rise of approximately 52C, and a junction tem-
perature of 77C with an ambient temperature of 25C.
Note 2: Guaranteed by design, not 100% tested in production.
CS51311
6
Reference
Voltage
+
C
E
+
Ramp Signal
Output
Voltage
Feedback
Error
Signal
GATE(H)
GATE(L)
Error
Amplifier
COMP
PWM
Comparator
V
FB
Figure 6: V
2
TM
Control Diagram
Typical Performance Characteristics
150
125
100
75
50
25
0
0
2000
4000
6000
8000
10000
12000
14000
16000
Falltime (ns)
Load Capacitance (pF)
V
CC
= 12V
T
A
= 25
C
0.10
0.05
0
-
0.05
-
0.10
-
0.15
-
0.20
1.325 1.375 1.425 1.475 1.525 1.575 1.625 1.675 1.725 1.775 1.825 1.875 1.925 1.975 2.025 2.075
DAC Output Voltage Setting (V)
Output Error (%)
V
CC
= 12V
T
A
= 25
C
V
ID4
= 0
Figure 4: Percent Output Error vs. DAC Output
Voltage Setting, V
ID4
= 0.
Figure 1: Gate(H) and Gate(L) Falltime vs. Load Capacitance.
Figure 2: Gate(H) and Gate(L) Risetime vs. Load Capacitance.
Figure 5: Percent Output Error vs. DAC Output
Voltage Setting, V
ID4
= 1.
150
125
100
75
50
25
0
0
2000
4000
6000
8000
10000
12000
14000
16000
Risetime (ns)
Load Capacitance (pF)
V
CC
= 12V
T
A
= 25
C
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
-
0.05
-
0.10
-
0.15
-
0.20
-
0.25
Output Error (%)
2.125 2.225 2.325 2.425 2.525 2.625 2.725 2.825 2.925 3.025 3.125 3.225 3.335 3.425 3.525
DAC Output Voltage Setting (V)
V
CC
= 12V
T
A
= 25
C
V
ID4
= 1
0.10
0.05
0
-
0.05
-
0.10
-
0.15
0
20
40
60
80
100
120
Junction Temperature (
C)
DAC Output V
oltage
Deviation (%)
V
CC
= 12V
Figure 3: DAC Output Voltage vs. Temperature,
DAC Code = 00001.
Application Information
V
2
TM
Control Method
The V
2
TM
method of control uses a ramp signal that is gen-
erated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is gen-
erated from the output voltage itself. This control scheme
differs from traditional techniques such as voltage mode,
which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
The V
2
TM
control method is illustrated in Figure 6. The out-
put voltage is used to generate both the error signal and
the ramp signal. Since the ramp signal is simply the output
Theory Of Operation
Application Information: continued
CS51311
voltage, it is affected by any change in the output regard-
less of the origin of that change. The ramp signal also con-
tains the DC portion of the output voltage, which allows
the control circuit to drive the main switch to 0% or 100%
duty cycle as required.
A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V
2
TM
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V
2
TM
control scheme has the same
advantages in line transient response.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined
only by the comparator response time and the transition
speed of the main switch. The reaction time to an output
load step has no relation to the crossover frequency of the
error signal loop, as in traditional control methods.
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal loop.
The main purpose of this "slow" feedback loop is to pro-
vide DC accuracy. Noise immunity is significantly
improved, since the error amplifier bandwidth can be rolled
off at a low frequency. Enhanced noise immunity improves
remote sensing of the output voltage, since the noise associ-
ated with long feedback traces can be effectively filtered.
Line and load regulation are drastically improved because
there are two independent voltage loops. A voltage mode
controller relies on a change in the error signal to compen-
sate for a deviation in either line or load voltage. This
change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation.
A current mode controller maintains fixed error signal
under deviation in the line voltage, since the slope of the
ramp signal changes, but still relies on a change in the error
signal for a deviation in load. The V
2
TM
method of control
maintains a fixed error signal for both line and load varia-
tion, since the ramp signal is affected by both line and load.
Constant Off-Time
To minimize transient response, the CS51311 uses a
Constant Off-Time method to control the rate of output
pulses. During normal operation, the Off-Time of the high
side switch is terminated after a fixed period, set by the
C
OFF
capacitor. Every time the V
FB
pin exceeds the COMP
pin voltage an Off-Time is initiated. To maintain regula-
tion, the V
2
TM
Control Loop varies switch On-Time. The
PWM comparator monitors the output voltage ramp, and
terminates the switch On-Time.
Constant Off-Time provides a number of advantages.
Switch duty Cycle can be adjusted from 0 to 100% on a
pulse-by pulse basis when responding to transient condi-
tions. Both 0% and 100% Duty Cycle operation can be
maintained for extended periods of time in response to
Load or Line transients.
Programmable Output
The CS51311 is designed to provide two methods for pro-
gramming the output voltage of the power supply. A five
bit on board digital to analog converter (DAC) is used to
program the output voltage within two different ranges.
The first range is 2.125V to 3.525V in 100mV steps, the sec-
ond is 1.325V to 2.075V in 50mV steps, depending on the
digital input code. If all five bits are left open, the CS51311
enters adjust mode. In adjust mode, the designer can
choose any output voltage by using resistor divider feed-
back to the V
FB
pin, as in traditional controllers. The
CS51311 is specifically designed to meet or exceed Intel's
Pentium
II specifications.
Error Amplifier
An inherent benefit of the V
2
TM
control topology is that
there is no large bandwidth requirement on the error
amplifier design. The reaction time to an output load step
has no relation to the crossover frequency, since transient
response is handled by the ramp signal loop. The main
purpose of this"slow"feedback loop is to provide DC accu-
racy. Noise immunity is significantly improved, since the
error amplifier bandwidth can be rolled off at a low fre-
quency. Enhanced noise immunity improves remote sens-
ing of the output voltage, since the noise associated with
long feedback traces can be effectively filtered. The COMP
pin is the output of the error amplifier and a capacitor to
Gnd compensates the error amplifier loop. Additionally,
through the built-in offset on the PWM Comparator non-
inverting input, the COMP pin provides the hiccup timing
for the Over-Current Protection, the soft start function that
minimizes inrush currents during regulator power-up and
switcher output enable.
Startup
The CS51311 provides a controlled startup of regulator
output voltage and features Programmable Soft Start
implemented through the Error Amp and external
Compensation Capacitor. This feature, combined with
overcurrent protection, prevents stress to the regulator
power components and overshoot of the output voltage
during startup.
As Power is applied to the regulator, the CS51311
Undervoltage Lockout circuit (UVL) monitors the ICs sup-
ply voltage (V
CC
) which is typically connected to the +12V
output of the AC-DC power supply. The UVL circuit pre-
vents the NFET gates from being activated until V
CC
exceeds the 8.4V (typ) threshold. Hysteresis of 300mV (typ)
is provided for noise immunity. The Error Amp Capacitor
connected to the COMP pin is charged by a 30A current
source. This capacitor must be charged to 1.1V (typ) so that
it exceeds the PWM comparator's offset before the V
2
TM
PWM control loop permits switching to occur.
When V
CC
has exceeded 8.4V and COMP has charged to
1.1V, the upper Gate driver (GATE(H)) is activated, turn-
ing on the upper FET. This causes current to flow through
the output inductor and into the output capacitors and
load according to the following equation:
I = (V
IN
V
OUT
)
GATE(H) and the upper NFET remain on and inductor cur-
rent ramps up until the initial pulse is terminated by either
the PWM control loop or the overcurrent protection. This
initial surge of in-rush current minimizes startup time, but
avoids overstressing of the regulator's power components.
The PWM comparator will terminate the initial pulse if the
T
L
7
CS51311
8
Application Information: continued
regulator output exceeds the voltage on the COMP pin
plus the 1.1V PWM comparator offset prior to the drop
across the current sense resistor exceeding the current limit
threshold. In this case, the PWM control loop has achieved
regulation and the initial pulse is then followed by a con-
stant off time as programmed by the C
OFF
capacitor. The
COMP capacitor will continue to slowly charge and the
regulator output voltage will follow it, less the 1.1V PWM
offset, until it achieves the voltage programmed by the
DAC's VID input. The Error Amp will then source or sink
current to the COMP cap as required to maintain the cor-
rect regulator DC output voltage. Since the rate of increase
of the COMP pin voltage is typically set much slower than
the regulator's slew capability, inrush current, output volt-
age, and duty cycle all gradually increase from zero. (See
Figures 7, 8, and 9).
Figure 7: Normal Startup (2ms/div).
Channel 1 - Regulator Output Voltage (1V/div)
Channel 2 - COMP Pin (1V/div)
Channel 3 - V
CC
(10V/div)
Channel 4 - Regulator Input Voltage (5V/div)
Figure 8: Normal Startup showing initial pulse followed by Soft Start
(20s/div).
Channel 1 - Regulator Output Voltage (1V/div)
Channel 2 Inductor Switching Node (5V/div)
Channel 3 - V
CC
(10V/div)
Channel 4 - Regulator Input Voltage (5V/div)
Figure 9: Pulse-by-Pulse Regulation during Soft Start (2s/div).
Channel 1 - Regulator Output Voltage (1V/div)
Channel 2 Inductor Switching Node (5V/div)
Channel 3 - V
CC
(10V/div)
Channel 4 - Regulator Input Voltage (5V/div)
If the voltage across the Current Sense resistor generates a
voltage difference between the V
FB
and V
OUT
pins that
exceeds the OVC Comparator Offset Voltage (86mV typi-
cal), the Fault latch is set. This causes the COMP pin to be
quickly discharged, turning off GATE(H) and the upper
NFET since the voltage on the COMP pin is now less than
the 1.1V PWM comparator offset. The Fault latch is reset
when the voltage on the COMP decreases below the
Discharge threshold voltage (0.25V typical). The COMP
capacitor will again begin to charge, and when it exceeds
the 1.1V PWM comparator offset, the regulator output will
Soft Start normally (see Figure 10).
Because the start-up circuit depends on the current sense
function, a current sense resistor should always be used.
Figure 10: Startup with COMP pre-charged to 2V (2ms/div).
Channel 1 - Regulator Output Voltage (1V/div)
Channel 2 - COMP Pin (1V/div)
Channel 3 - V
CC
(10V/div)
Channel 4 - Regulator Input Voltage (5V/div)
Soft Start @
COMP > 1.1V
OCP @
V
CC
> 8.4V
Duty Cycle = V
OUT
/ V
IN
0.27V / 3.54V = 7%
5.2%
Start-up @
V
CC
> 8.4V
Initial Pulse until V
OUT
> COMP + PWM Offset
Start-up @
V
CC
> 8.4V
Application Information: continued
233
CS51311
When driving large capacitive loads, the COMP must
charge slowly enough to avoid tripping the CS51311 over-
current protection. The following equation can be used to
ensure unconditional startup:
<
where
I
CHG
= COMP Source Current (30A typical);
C
COMP
= COMP Capacitor value (0.1F typical);
I
LIM
= Current Limit Threshold;
I
LOAD
= Load Current during startup;
C
OUT
= Total Output Capacitance.
Normal Operation
During Normal operation, Switch Off-Time is constant and
set by the C
OFF
capacitor. Switch On-Time is adjusted by
the V
2
TM
Control loop to maintain regulation. This results in
changes in regulator switching frequency, duty cycle, and
output ripple in response to changes in load and line.
Output voltage ripple will be determined by inductor rip-
ple current and the ESR of the output capacitors
Transient Response
The CS51311 V
2
TM
Control Loop's 200ns reaction time pro-
vides unprecedented transient response to changes in
input voltage or output current. Pulse-by-pulse adjustment
of duty cycle is provided to quickly ramp the inductor cur-
rent to the required level. Since the inductor current cannot
be changed instantaneously, regulation is maintained by
the output capacitor(s) during the time required to slew the
inductor current.
Overall load transient response is further improved
through a feature called "Adaptive Voltage Positioning".
This technique pre-positions the output capacitors voltage
to reduce total output voltage excursions during changes
in load.
Holding tolerance to 1% allows the error amplifiers refer-
ence voltage to be targeted +25mV high without compro-
mising DC accuracy. A "Droop Resistor", implemented
through a PC board trace, connects the Error Amps feed-
back pin (V
FB
) to the output capacitors and load and carries
the output current. With no load, there is no DC drop
across this resistor, producing an output voltage tracking
the Error amps, including the +25mV offset. When the full
load current is delivered, a 50mV drop is developed across
this resistor. This results in output voltage being offset -
25mV low.
The result of Adaptive Voltage Positioning is that addition-
al margin is provided for a load transient before reaching
the output voltage specification limits. When load current
suddenly increases from its minimum level, the output
capacitor is pre-positioned +25mV. Conversely, when load
current suddenly decreases from its maximum level, the
output capacitor is pre-positioned -25mV. For best
Transient Response, a combination of a number of high fre-
quency and bulk output capacitors are usually used.
Slope Compensation
The V
2
TM
control method uses a ramp signal, generated by
the ESR of the output capacitors, that is proportional to the
ripple current through the inductor. To maintain regulation,
the V
2
TM
control loop monitors this ramp signal, through the
PWM comparator, and terminates the switch on-time.
The stringent load transient requirements of modern
microprocessors require the output capacitors to have very
low ESR. The resulting shallow slope presented to the
PWM comparator, due to the very low ESR, can lead to
pulse width jitter and variation caused by both random or
synchronous noise.
Adding slope compensation to the control loop, avoids
erratic operation of the PWM circuit, particularly at lower
duty cycles and higher frequencies, where there is not
enough ramp signal, and provides a more stable switch-
point.
The scheme that prevents that switching noise prematurely
triggers the PWM circuit consists of adding a positive volt-
age slope to the output of the Error Amplifier (COMP pin)
during an off-time cycle.
The circuit that implements this function is shown in
Figure 11.
Figure 11: Small RC filter provides the proper voltage ramp at the
beginning of each on-time cycle.
The ramp waveform is generated through a small RC filter
that provides the proper voltage ramp at the beginning of
each on-time cycle. The resistors R1 and R2 in the circuit of
Figure 11 form a voltage divider from the GATE(L) output,
superimposing a small artificial ramp on the output of the
error amplifier. It is important that the series combination
R1/R2 is high enough in resistance not to load down and
negatively affect the slew rate on the GATE(L) pin.
Over-Current Protection
A loss-less hiccup mode current limit protection feature is
provided, requiring only the COMP capacitor to imple-
ment. The CS51311 provides overcurrent protection by
sensing the current through a "Droop" resistor, using an
internal current sense comparator. The comparator com-
pares the voltage drop through the "Droop" resistor to an
internal reference voltage of 86mV (typical).
If the voltage drop across the "Droop" resistor exceeds this
threshold, the current sense comparator allows the fault
Protection and Monitoring Features
C
COMP
R
1
To Synchronous FET
C
1
R
2
14
11
COMP
GATE(L)
CS51311
I
LIM
- I
LOAD
C
OUT
I
CHG
C
COMP
CS51311
10
Application Information: continued
latch to be set. This causes the regulator to stop switching.
During this overcurrent condition, the CS51311 stays off
for the time it takes the COMP pin capacitor to discharge
to its lower 0.25V threshold. As soon as the COMP pin
reaches 0.25V, the Fault latch is reset (no overcurrent con-
dition present) and the COMP pin is charged with a 30A
current source to a voltage 1.1V greater than the V
FB
volt-
age. Only at this point the regulator attempts to restart nor-
mally by delivering short gate pulses to both FETS. The
CS51311 will operate initially with a duty cycle whose val-
ue depends on how low the V
FB
voltage was during the
overcurrent condition (whether hiccup mode was due to
excessive current or hard short). This protection scheme
minimizes thermal stress to the regulator components,
input power supply, and PC board traces, as the overcur-
rent condition persists. Upon removal of the overload, the
fault latch is cleared, allowing normal operation to resume.
Overvoltage Protection
Overvoltage protection (OVP) is provided as result of the
normal operation of the V
2
TM
control topology and requires
no additional external components. The control loop
responds to an overvoltage condition within 200ns, caus-
ing the top MOSFET to shut off, disconnecting the regula-
tor from its input voltage. This results in a "crowbar"
action to clamp the output voltage and prevents damage to
the load. The regulator will remain in this state until the
overvoltage condition ceases or the input voltage is pulled
low. The bottom FET and board trace must be properly
designed to implement the OVP function.
Power-Good Circuit
The Power-Good pin (pin 12) is an open-collector signal
consistent with TTL DC specifications. It is externally
pulled up, and is pulled low (below 0.3V) when the regula-
tor output voltage typically exceeds 8.5% of the nominal
output voltage. Maximum output voltage deviation before
Power-Good is pulled low is 12%.
Output Enable
On/off control of the regulator outputs can be implement-
ed by pulling the COMP pins low. It is required to pull the
COMP pins below the 1.1V PWM comparator offset volt-
age in order to disable switching on the GATE drivers.
Step 1: Definition of the design specifications
In computer motherboard applications the input voltage
comes from the "silver box" power supply. 5V 5% is
used for conversion to output voltage, and 12V 5% is
used for the external NFET gate voltage and circuit bias.
The CPU V
CC(CORE)
tolerance can be affected by any or all
of the following reasons:
1) buck regulator output voltage setpoint accuracy;
2) output voltage change due to discharging or charging of
the bulk decoupling capacitors during a load current tran-
sient;
3) output voltage change due to the ESR and ESL of the
bulk and high frequency decoupling capacitors, circuit
traces, and vias;
4) output voltage ripple and noise.
Budgeting the tolerance is left up to the designer who must
take into account all of the above effects and provide a
V
CC(CORE)
that will meet the specified tolerance at the
CPU's inputs.
The designer must also ensure that the regulator compo-
nent junction temperatures are kept within the manufac-
turer's specified ratings at full load and maximum ambient
temperature. As computer motherboards become increas-
ingly complex, regulator size also becomes important, as
there is less space available for the CPU power supply.
Step 2: Selection of the Output Capacitors
These components must be selected and placed carefully to
yield optimal results. Capacitors should be chosen to pro-
vide acceptable ripple on the regulator output voltage. Key
specifications for output capacitors are their ESR
(Equivalent Series Resistance), and ESL (Equivalent Series
Inductance). For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.
In order to determine the number of output capacitors the
maximum voltage transient allowed during load transi-
tions has to be specified. The output capacitors must hold
the output voltage within these limits since the inductor
current can not change with the required slew rate. The
output capacitors must therefore have a very low ESL and
ESR.
The voltage change during the load current transient is:
V
OUT
= I
OUT
(
+ ESR +
)
,
where
I
OUT
/ t = load current slew rate;
I
OUT
= load transient;
t = load transient duration time;
ESL = Maximum allowable ESL including capacitors,
circuit traces, and vias;
ESR = Maximum allowable ESR including capacitors
and circuit traces;
t
TR
= output voltage transient response time.
The designer has to independently assign values for the
change in output voltage due to ESR, ESL, and output
capacitor discharging or charging. Empirical data indicates
that most of the output voltage change (droop or spike
depending on the load current transition) results from the
total output capacitor ESR.
The maximum allowable ESR can then be determined
according to the formula
ESR
MAX
=
,
where V
ESR
= change in output voltage due to ESR
(assigned by the designer).
Once the maximum allowable ESR is determined, the num-
ber of output capacitors can be found by using the formula
V
ESR
I
OUT
t
TR
C
OUT
ESL
t
CS51311-based V
CC(CORE)
Buck Regulator Design Procedure
Application Information: continued
CS51311
11
Number of capacitors =
,
where
ESR
CAP
= maximum ESR per capacitor (specified in
manufacturer's data sheet);
ESR
MAX
= maximum allowable ESR.
The actual output voltage deviation due to ESR can then be
verified and compared to the value assigned by the design-
er:
V
ESR
= I
OUT
ESR
MAX
Similarly, the maximum allowable ESL is calculated from
the following formula:
ESL
MAX
=
,
where
I/T = load current slew rate (as high as 20A/s);
V
ESL
= change in output voltage due to ESL.
The actual maximum allowable ESL can be determined by
using the equation:
ESL
MAX
=
,
where ESL
CAP
= maximum ESL per capacitor (it is estimat-
ed that a 10 12mm Aluminum Electrolytic capacitor has
approximately 4nH of package inductance).
The actual output voltage deviation due to the actual maxi-
mum ESL can then be verified:
V
ESL
=
.
The designer now must determine the change in output
voltage due to output capacitor discharge during the tran-
sient:
V
CAP
=
,
where
t
TR
= the output voltage transient response time
(assigned by the designer);
V
CAP
= output voltage deviation due to output capaci-
tor discharge;
I = Load step.
The total change in output voltage as a result of a load cur-
rent transient can be verified by the following formula:
V
OUT
= V
ESR
+ V
ESL
+ V
CAP
Step 3: Selection of the Duty Cycle,
Switching Frequency, Switch On-Time (T
ON
)
and Switch Off-Time (T
OFF
)
The duty cycle of a buck converter (including parasitic
losses) is given by the formula:
Duty Cycle = D =
,
where
V
OUT
= buck regulator output voltage;
V
HFET
= high side FET voltage drop due to R
DS(ON)
;
V
L
= output inductor voltage drop due to inductor wire
DC resistance;
V
DROOP
= droop (current sense) resistor voltage drop;
V
IN
= buck regulator input voltage;
V
LFET
= low side FET voltage drop due to R
DS(ON)
.
Step3a: Calculation of Switch On-Time
The switch On-Time (time during which the switching
MOSFET in a synchronous buck topology is conducting) is
determined by:
T
ON
= ,
where F
SW
= regulator switching frequency selected by the
designer.
Higher operating frequencies allow the use of smaller
inductor and capacitor values. Nevertheless, it is common
to select lower frequency operation because a higher fre-
quency results in lower efficiency due to MOSFET gate
charge losses. Additionally, the use of smaller inductors at
higher frequencies results in higher ripple current, higher
output voltage ripple, and lower efficiency at light load
currents.
Step 3b: Calculation of Switch Off-Time
The switch Off-Time (time during which the switching
MOSFET is not conducting) can be determined by:
T
OFF
=
- T
ON
,
The C
OFF
capacitor value has to be selected in order to set
the Off-Time, T
OFF
, above:
C
OFF
= ,
where
3980 is a characteristic factor of the CS51311;
D = Duty Cycle.
Step 4: Selection of the Output Inductor
The inductor should be selected based on its inductance,
current capability, and DC resistance. Increasing the induc-
tor value will decrease output voltage ripple, but degrade
transient response. There are many factors to consider in
selecting the inductor including cost, efficiency, EMI and
ease of manufacture. The inductor must be able to handle
the peak current at the switching frequency without satu-
rating, and the copper resistance in the winding should be
kept as low as possible to minimize resistive power loss.
There are a variety of materials and types of magnetic
cores that could be used for this application. Among them
are ferrites, molypermalloy cores (MPP), amorphous and
powdered iron cores. Powdered iron cores are very com-
monly used. Powdered iron cores are very suitable due to
Period (1 - D)
3980
1
F
SW
Duty Cycle
F
SW
V
OUT
+ (V
HFET
+ V
L
+ V
DROOP
)
V
IN
+ V
LFET
- V
HFET
- V
L
I t
TR
C
OUT
ESL
MAX
I
t
ESL
CAP
Number of output capacitors
V
ESL
t
I
ESR
CAP
ESR
MAX
Application Information: continued
CS51311
12
their high saturation flux density and have low loss at high
frequencies, a distributed gap and exhibit very low EMI.
The inductor value can be determined by:
L =
,
where
V
IN
= input voltage;
V
OUT
= output voltage;
t
TR
= output voltage transient response time (assigned
by the designer);
I = load transient.
The inductor ripple current can then be determined:
I
L
= ,
where
I
L
= inductor ripple current;
V
OUT
= output voltage;
T
OFF
= switch Off-Time;
L = inductor value.
The designer can now verify if the number of output
capacitors from step 2 will provide an acceptable output
voltage ripple (1% of output voltage is common). The for-
mula below is used:
I
L
= ,
Rearranging we have:
ESR
MAX
= ,
where
ESR
MAX
= maximum allowable ESR;
V
OUT
= 1% V
OUT
= maximum allowable output volt-
age ripple ( budgeted by the designer );
I
L
= inductor ripple current;
V
OUT
= output voltage.
The number of output capacitors is determined by:
Number of capacitors =
,
where ESR
CAP
= maximum ESR per capacitor (specified in
manufacturer's data sheet).
The designer must also verify that the inductor value
yields reasonable inductor peak and valley currents (the
inductor current is a triangular waveform):
I
L(PEAK)
= I
OUT
+
,
where
I
L(PEAK)
= inductor peak current;
I
OUT
= load current;
I
L
= inductor ripple current.
I
L(VALLEY)
= I
OUT
-
,
where I
L(VALLEY)
= inductor valley current.
Given the requirements of an application such as a buck
converter, it is found that a toroid powdered iron core is
quite suitable due to its low cost, low core losses at the
switching frequency, and low EMI.
Step 5: Selection of the Input Capacitors
These components must be selected and placed carefully to
yield optimal results. Capacitors should be chosen to pro-
vide acceptable ripple on the input supply lines. A key
specification for input capacitors is their ripple current rat-
ing. The input capacitor should also be able to handle the
input RMS current I
IN(RMS)
.
The combination of the input capacitors C
IN
discharges
during the on-time.
The input capacitor discharge current is given by:
I
CINDIS(RMS)
=
,
where
I
CINDIS(RMS)
= input capacitor discharge current;
I
L(PEAK)
= inductor peak current;
I
L(VALLEY)
= inductor valley current.
C
IN
charges during the off-time, the average current
through the capacitor over one switching cycle is zero:
I
CIN(CH)
= I
CIN(DIS)
,
where
I
CIN(CH)
= input capacitor charge current;
I
CIN(DIS)
= input capacitor discharge current;
D = Duty Cycle.
The total Input RMS current is:
I
CIN(RMS)
= (I
CIN(DIS)
2
D) + (I
CIN(CH)
2
(1 - D))
The number of input capacitors required is then deter-
mined by:
N
CIN
= ,
where
N
CIN
= number of input capacitors;
I
CIN(RMS)
= total input RMS current;
I
RIPPLE
= input capacitor ripple current rating (specified
in manufacturer's data sheets).
The total input capacitor ESR needs to be determined in
order to calculate the power dissipation of the input capac-
itors:
ESR
CIN
= ,
where
ESR
CIN
= total input capacitor ESR;
ESR
CAP
= maximum ESR per capacitor (specified in
manufacturer's data sheets);
N
CIN
= number of input capacitors.
ESR
CAP
N
CIN
I
CIN(RMS)
I
RIPPLE
D
1 - D
(I
L(PEAK)
2
+ (I
L(PEAK)
I
L(VALLEY)
) + I
L(VALLEY)
2
D
3
I
L
2
I
L
2
ESR
CAP
ESR
MAX
V
OUT
I
L
V
OUT
ESR
MAX
V
OUT
T
OFF
L
(V
IN
- V
OUT
) t
TR
Once the total ESR of the input capacitors is known, the
input capacitor ripple voltage can be determined using the
formula:
V
CIN(RMS)
= I
CIN(RMS)
ESR
CIN
,
where
V
CIN(RMS)
= input capacitor RMS voltage;
I
CIN(RMS)
= total input RMS current;
ESR
CIN
= total input capacitor ESR.
The designer must determine the input capacitor power
loss in order to ensure there isn't excessive power dissipa-
tion through these components. The following formula is
used:
P
CIN(RMS)
= I
CIN(RMS)
2
ESR
CIN
where
P
CIN(RMS)
= input capacitor RMS power dissipation;
I
CIN(RMS)
= total input RMS current;
ESR
CIN
= total input capacitor ESR.
Step 6: Selection of the Input Inductor
A CPU switching regulator, such as the one in a buck
topology, must not disturb the primary +5V supply. One
method of achieving this is by using an input inductor and
a bypass capacitor. The input inductor isolates the +5V
supply from the noise generated in the switching portion
of the microprocessor buck regulator and also limits the
inrush current into the input capacitors upon power up.
The inductor's limiting effect on the input current slew rate
becomes increasingly beneficial during load transients. The
worst case is when the CPU load changes from no load to
full load (load step), a condition under which the highest
voltage change across the input capacitors is also seen by
the input inductor. The inductor successfully blocks the
ripple current while placing the transient current require-
ments on the input bypass capacitor bank, which has to
initially support the sudden load change.
The minimum inductance value for the input inductor is
therefore:
L
IN
= ,
where
L
IN
= input inductor value;
V = voltage seen by the input inductor during a full
load swing;
(dI/dt)
MAX
= maximum allowable input current slew
rate (0.1A/s for a Pentium II power supply).
The designer must select the LC filter pole frequency so
that at least 40dB attenuation is obtained at the regulator
switching frequency. The LC filter is a double-pole net-
work with a slope of -2, a roll-off rate of 40dB/dec, and a
corner frequency:
f
C
= ,
where
L = input inductor;
C = input capacitor(s).
Step 7: Selection of the Switching FET
FET Basics
The use of the MOSFET as a power switch is propelled by
two reasons: 1) Its very high input impedance; and 2) Its very
fast switching times. The electrical characteristics of a MOS-
FET are considered to be those of a perfect switch. Control
and drive circuitry power is therefore reduced. Because the
input impedance is so high, it is voltage driven. The input
of the MOSFET acts as if it were a small capacitor, which
the driving circuit must charge at turn on. The lower the
drive impedance, the higher the rate of rise of V
GS
, and the
faster the turn- on time. Power dissipation in the switching
MOSFET consists of 1) conduction losses, 2) leakage losses,
3) turn-on switching losses, 4) turn-off switching losses,
and 5) gate-transitions losses. The latter three losses are
proportional to frequency. For the conducting power dissi-
pation rms values of current and resistance are used for
true power calculations. The fast switching speed of the
MOSFET makes it indispensable for high-frequency power
supply applications. Not only are switching power losses
minimized, but also the maximum usable switching fre-
quency is considerably higher. Switching time is indepen-
dent of temperature. Also, at higher frequencies, the use of
smaller and lighter components (transformer, filter choke,
filter capacitor) reduces overall component cost while
using less space for more efficient packaging at lower
weight.
The MOSFET has purely capacitive input impedance. No
DC current is required. It is important to keep in mind the
drain current of the FET has a negative temperature coeffi-
cient. Increase in temperature causes higher on-resistance
and greater leakage current. For switching circuits, V
DS(ON)
should be low to minimize power dissipation at a given I
D
,
and V
GS
should be high to accomplish this. MOSFET
switching times are determined by device capacitance,
stray capacitance, and the impedance of the gate drive cir-
cuit. Thus the gate driving circuit must have high momen-
tary peak current sourcing and sinking capability for
switching the MOSFET. The input capacitance, output
capacitance and reverse-transfer capacitance also increase
with increased device current rating.
Two considerations complicate the task of estimating
switching times. First, since the magnitude of the input
capacitance, C
ISS
, varies with V
DS
, the RC time constant
determined by the gate-drive impedance and C
ISS
changes
during the switching cycle. Consequently, computation of
the rise time of the gate voltage by using a specific gate-
drive impedance and input capacitance yields only a rough
estimate. The second consideration is the effect of the
"Miller" capacitance, C
RSS
, which is referred to as C
DG
in
the following discussion. For example, when a device is on,
V
DS(ON)
is fairly small and V
GS
is about 12V. C
DG
is
charged to V
DS(ON)
- V
GS
, which is a negative potential if
the drain is considered the positive electrode. When the
drain is "off", C
DG
is charged to quite a different potential.
In this case the voltage across C
DG
is a positive value since
the potential from gate-to-source is near zero volts and V
DS
is essentially the drain supply voltage. During turn-on and
turn-off, these large swings in gate-to-drain voltage tax the
current sourcing and sinking capabilities of the gate drive.
In addition to charging and discharging C
GS
, the gate drive
must also supply the displacement current required by
1
2 LC
V
(dI/dt)
MAX
Application Information: continued
CS51311
13
Application Information: continued
CS51311
14
C
DG
(I
GATE
= C
dg
dV
dg
/dt). Unless the gate-drive
impedance is very low, the V
GS
waveform commonly
plateaus during rapid changes in the drain-to-source volt-
age.
The most important aspect of FET performance is the Static
Drain-To-Source On-Resistance (R
DS(ON)
), which effects
regulator efficiency and FET thermal management require-
ments. The On-Resistance determines the amount of cur-
rent a FET can handle without excessive power dissipation
that may cause overheating and potentially catastrophic
failure. As the drain current rises, especially above the con-
tinuous rating, the On-Resistance also increases. Its posi-
tive temperature coefficient is between +0.6%/C and
+0.85%/C. The higher the On-Resistance the larger the
conduction loss is. Additionally, the FET gate charge
should be low in order to minimize switching losses and
reduce power dissipation.
Both logic level and standard FETs can be used. The refer-
ence designs derive gate drive from the 12V supply, which
is generally available in most computer systems and uti-
lizes logic level FETs.
Voltage applied to the FET gates depends on the applica-
tion circuit used. Both upper and lower gate driver outputs
are specified to drive to within 1.5V of ground when in the
low state and to within 2V of their respective bias supplies
when in the high state. In practice, the FET gates will be
driven rail-to-rail due to overshoot caused by the capaci-
tive load they present to the controller IC.
Step 7a - Selection of the switching (upper) FET
The designer must ensure that the total power dissipation
in the FET switch does not cause the power component's
junction temperature to exceed 150C.
The maximum RMS current through the switch can be
determined by the following formula:
I
RMS(H)
=
,
where
I
RMS(H)
= maximum switching MOSFET RMS current;
I
L(PEAK)
= inductor peak current;
I
L(VALLEY)
= inductor valley current;
D = Duty Cycle.
Once the RMS current through the switch is known, the
switching MOSFET conduction losses can be calculated:
P
RMS(H)
= I
RMS(H)
2
R
DS(ON)
where
P
RMS(H)
= switching MOSFET conduction losses;
I
RMS(H)
= maximum switching MOSFET RMS current;
R
DS(ON)
= FET drain-to-source on-resistance
The upper MOSFET switching losses are caused during
MOSFET switch-on and switch-off and can be determined
by using the following formula:
P
SWH
= P
SWH(ON)
+ P
SWH(OFF)
= ,
where
P
SWH(ON)
= upper MOSFET switch-on losses;
P
SWH(OFF)
= upper MOSFET switch-off losses;
V
IN
= input voltage;
I
OUT
= load current;
t
RISE
= MOSFET rise time (from FET manufacturer's
switching characteristics performance curve);
t
FALL
= MOSFET fall time (from FET manufacturer's
switching characteristics performance curve);
T = 1/F
SW
= period.
The total power dissipation in the switching MOSFET can
then be calculated as:
P
HFET(TOTAL)
= P
RMSH
+ P
SWH(ON)
+ P
SWH(OFF)
,
where
P
HFET(TOTAL)
= total switching (upper) MOSFET losses;
P
RMSH
= upper MOSFET switch conduction Losses;
P
SWH(ON)
= upper MOSFET switch-on losses;
P
SWH(OFF)
= upper MOSFET switch-off losses.
Once the total power dissipation in the switching FET is
known, the maximum FET switch junction temperature
can be calculated:
T
J
= T
A
+ [P
HFET(TOTAL)
R
JA
],
where
T
J
= FET junction temperature;
T
A
= ambient temperature;
P
HFET(TOTAL)
= total switching (upper) FET losses;
R
JA
= upper FET junction-to-ambient thermal resistance
Step 7b: Selection of the synchronous (lower) FET
The switch conduction losses for the lower FET can be cal-
culated as follows:
P
RMSL
= I
RMS
2
R
DS(ON)
= [I
OUT
(1 - D)]
2
R
DS(ON)
,
where
P
RMSL
= lower MOSFET conduction losses;
I
OUT
= load current;
D = Duty Cycle;
R
DS(ON)
= lower FET drain-to-source on-resistance.
The synchronous MOSFET has no switching losses, except
for losses in the internal body diode, because it turns on
into near zero voltage conditions. The MOSFET body
diode will conduct during the non-overlap time and the
resulting power dissipation (neglecting reverse recovery
losses) can be calculated as follows:
P
SWL
= V
SD
I
LOAD
non-overlap time F
SW
,
where
P
SWL
= lower FET switching losses;
V
SD
= lower FET source-to-drain voltage;
I
LOAD
= load current
Non-overlap time = GATE(L)-to-GATE(H) or GATE(H)-
to-GATE(L) delay (from CS51311 data sheet Electrical
V
IN
I
OUT
(t
RISE
+ t
FALL
)
6T
(I
L(PEAK)
2
+ (I
L(PEAK)
I
L(VALLEY)
) + I
L(VALLEY)
2
D
3
Application Information: continued
CS51311
15
Characteristics section);
F
SW
= switching frequency.
The total power dissipation in the synchronous (lower)
MOSFET can then be calculated as:
P
LFET(TOTAL)
= P
RMSL
+ P
SWL
,
where
P
LFET(TOTAL)
= Synchronous (lower) FET total losses;
P
RMSL
= Switch Conduction Losses;
P
SWL
= Switching losses.
Once the total power dissipation in the synchronous FET is
known the maximum FET switch junction temperature can
be calculated:
T
J
= T
A
+ [P
LFET(TOTAL)
R
JA
],
where
T
J
= MOSFET junction temperature;
T
A
= ambient temperature;
P
LFET(TOTAL)
= total synchronous (lower) FET losses;
R
JA
= lower FET junction-to-ambient thermal resistance.
Step 8: Control IC Power Dissipation
The power dissipation of the IC varies with the MOSFETs
used, V
CC
, and the CS51311 operating frequency. The aver-
age MOSFET gate charge current typically dominates the
control IC power dissipation.
The IC power dissipation is determined by the formula:
P
CONTROLIC
= I
CC
V
CC
+ P
GATE(H)
+ P
GATE(L)
,
where
P
CONTROLIC
= control IC power dissipation;
I
CC
= IC quiescent supply current;
V
CC
= IC supply voltage;
P
GATE(H)
= upper MOSFET gate driver (IC) losses;
P
GATE(L)
= lower MOSFET gate driver (IC) losses.
The upper (switching) MOSFET gate driver (IC) losses are:
P
GATE(H)
= Q
GATE(H)
F
SW
V
GATE(H)
,
where
P
GATE(H)
= upper MOSFET gate driver (IC) losses;
Q
GATE(H)
= total upper MOSFET gate charge;
F
SW
= switching frequency;
V
GATE(H)
= upper MOSFET gate voltage.
The lower (synchronous) MOSFET gate driver (IC) losses
are:
P
GATE(L)
= Q
GATE(L)
F
SW
V
GATE(L)
,
where
P
GATE(L)
= lower MOSFET gate driver (IC) losses;
Q
GATE(L)
= total lower MOSFET gate charge;
F
SW
= switching frequency;
V
GATE(L)
= lower MOSFET gate voltage.
The junction temperature of the control IC is primarily a
function of the PCB layout, since most of the heat is
removed through the traces connected to the pins of the IC.
Step 9: Slope Compensation
Voltage regulators for today's advanced processors are
expected to meet very stringent load transient require-
ments. One of the key factors in achieving tight dynamic
voltage regulation is low ESR at the CPU input supply
pins. Low ESR at the regulator output results in low output
voltage ripple. The consequence is, however, that there's
very little voltage ramp at the control IC feedback pin (V
FB
)
and regulator sensitivity to noise and loop instability are
two undesirable effects that can surface. The performance
of the CS51311-based CPU V
CC(CORE)
regulator is
improved when a fixed amount of slope compensation is
added to the output of the PWM Error Amplifier (COMP
pin) during the regulator Off-Time. Referring to Figure 11,
the amount of voltage ramp at the COMP pin is dependent
on the gate voltage of the lower (synchronous) FET and the
value of resistor divider formed by R1and R2.
V
SLOPECOMP
= V
GATE(L)
(
)
(1 - e ),
where
V
SLOPECOMP
= amount of slope added;
V
GATE(L)
= lower MOSFET gate voltage;
R1, R2 = voltage divider resistors;
t = t
OFF
(switch off-time);
= RC constant determined by C1 and the parallel com-
bination of R1, R2 (Figure 11), neglecting the low driver
output impedance
The artificial voltage ramp created by the slope compensa-
tion scheme results in improved control loop stability pro-
vided that the RC filter time constant is smaller than the
off-time cycle duration (time during which the lower MOS-
FET is conducting).
Step 10: Selection of Current Limit Filter Components
The current limit filter is implemented by a 0.1F ceramic
capacitor across and two 510 resistors in series with the
V
FB
and V
OUT
current limit comparator input pins. They
provide a time constant = RC = 100s, which enables the
circuit to filter out noise and be immune to false triggering,
caused by sudden and fast load changes. These load tran-
sients can have slew rates as high as 20A/s.
Adaptive voltage positioning is used to help keep the out-
put voltage within specification during load transients. To
implement adaptive voltage positioning a "Droop
Resistor" must be connected between the output inductor
and output capacitors and load. This resistor carries the
full load current and should be chosen so that both DC and
AC tolerance limits are met. An embedded PC trace resis-
tor has the distinct advantage of near zero cost implemen-
tation. However, this droop resistor can vary due to three
reasons: 1) the sheet resistivity variation caused by varia-
tion in the thickness of the PCB layer; 2) the mismatch of
L/W; and 3) temperature variation.
1) Sheet Resistivity
For one ounce copper, the thickness variation is typically
"Droop" Resistor for Adaptive Voltage Positioning
and Current Limit
-t
R2
R1 + R2
CS51311
16
Application Information: continued
1.26 mil to 1.48 mil. Therefore the error due to sheet resis-
tivity is:
= 8%.
2) Mismatch due to L/W
The variation in L/W is governed by variations due to the
PCB manufacturing process. The error due to L/W mis-
match is typically 1%.
3) Thermal Considerations
Due to I
2
R power losses the surface temperature of the
droop resistor will increase causing the resistance to
increase. Also, the ambient temperature variation will con-
tribute to the increase of the resistance, according to the
formula:
R = R
20
[1+
20
(-20)],
where
R
20
= resistance at 20C;
=
;
T= operating temperature;
R = desired droop resistor value.
For temperature T = 50C, the % R change = 12%.
Droop Resistor Tolerance
Tolerance due to sheet resistivity variation
8%
Tolerance due to L/W error
1%
Tolerance due to temperature variation
12%
Total tolerance for droop resistor
21%
In order to determine the droop resistor value the nominal
voltage drop across it at full load has to be calculated. This
voltage drop has to be such that the output voltage at full
load is above the minimum DC tolerance spec:
V
DROOP(TYP)
= .
Example: for a 450MHz Pentium
II, the DC accuracy spec
is 1.93 < V
CC(CORE)
< 2.07V, and the AC accuracy spec is
1.9V < V
CC(CORE)
< 2.1V. The CS51311 DAC output voltage
is +2.001V < V
DAC
< +2.049V. In order not to exceed the
DC accuracy spec, the voltage drop developed across the
resistor must be calculated as follows:
V
DROOP(TYP)
=
=
= 71mV.
With the CS51311 DAC accuracy being 1%, the internal
error amplifier's reference voltage is trimmed so that the
output voltage will be 25mV high at no load. With no load,
there is no DC drop across the resistor, producing an out-
put voltage tracking the error amplifier output voltage,
including the offset. When the full load current is deliv-
ered, a drop of -50mV is developed across the resistor.
Therefore, the regulator output is pre-positioned at 25mV
above the nominal output voltage before a load turn-on.
The total voltage drop due to a load step is V-25mV and
the deviation from the nominal output voltage is 25mV
smaller than it would be if there was no droop resistor.
Similarly at full load the regulator output is pre-positioned
at 25mV below the nominal voltage before a load turn-off.
the total voltage increase due to a load turn-off is V-25mV
and the deviation from the nominal output voltage is
25mV smaller than it would be if there was no droop resis-
tor. This is because the output capacitors are pre-charged
to a value that is either 25mV above the nominal output
voltage before a load turn-on or, 25mV below the nominal
output voltage before a load turn-off .
Obviously, the larger the voltage drop across the droop
resistor (the larger the resistance), the worse the DC and
load regulation, but the better the AC transient response.
Current Limit
The current limit setpoint has to be higher than the normal
full load current. Attention has to be paid to the current
rating of the external power components as these are the
first to fail during an overload condition. The MOSFET
continuous and pulsed drain current rating at a given case
temperature has to be accounted for when setting the cur-
rent limit trip point.
Temperature curves on MOSFET manufacturers' data
sheets allow the designer to determine the MOSFET drain
current at a particular V
GS
and T
J
(junction temperature).
This, in turn, will assist the designer to set a proper current
limit, without causing device breakdown during an over-
load condition.
Let's assume the full CPU load is 16A. The internal current
sense comparator current limit voltage limits are: 77mV <
V
TH
< 101mV. Also, there is a 21% total variation in R
SENSE
as discussed in the previous section.
We compute the value of the current sensing element
(embedded PCB trace) for the minimum current limit set-
point:
R
SENSE(MIN)
= R
SENSE(TYP)
0.79,
R
SENSE(MAX)
= R
SENSE(TYP)
1.21,
R
SENSE(MAX)
= =
= 4.8m.
We select,
R
SENSE(TYP)
= 3.3m.
We calculate the range of load currents that will cause the
internal current sense comparator to detect an overload
condition.
Nominal Current Limit Setpoint
From the overcurrent detection data in the electrical char-
acteristics table:
V
TH(TYP)
= 86mV,
77mV
16A
V
TH(MIN)
I
CL(MIN)
+2.001V-1.93V
1.21
[V
DAC(MIN)
-V
DC (MIN)
]
1+R
DROOP(TOLERANCE)
V
DAC(MIN)
-V
DC(MIN)
1+R
DROOP(TOLERANCE)
0.00393
C
1.48 - 1.26
1.37
Application Information: continued
CS51311
17
I
CL(NOM)
=
=
= 26A.
Maximum Current Limit Setpoint
From the overcurrent detection data in the electrical char-
acteristics table:
V
TH(MAX)
= 101mV,
I
CL(MAX)
=
=
= =
38.7A.
Therefore, the range of load currents that will cause the
internal current sense comparator to detect an overload
condition through a 3.2m embedded PCB trace is: 19.3A
< I
CL
< 38.7A, with 26A being the nominal overload condi-
tion.
Design Rules for Using a Droop Resistor
The basic equation for laying an embedded resistor is:
R
AR
=
or R =
,
where
A= W t = cross-sectional area;
= the copper resistivity (-mil);
L= length (mils);
W = width (mils);
t = thickness (mils).
For most PCBs the copper thickness, t, is 35m (1.37 mils)
for one ounce copper; = 717.86-mil.
For a CPU load of 16A the resistance needed to create a
50mV drop at full load is:
R
DROOP
=
=
= 3.1m.
The resistivity of the copper will drift with the temperature
according to the following guidelines:
R = 12% @ T
A
= +50C;
R = 34% @T
A
= +100C.
Droop Resistor Length, Width, and Thickness
The minimum width and thickness of the droop resistor
should primarily be determined on the basis of the current-
carrying capacity required, and the maximum permissible
droop resistor temperature rise. PCB manufacturer design
charts can be used in determining current- carrying capaci-
ty and sizes of etched copper conductors for various tem-
perature rises above ambient.
For single conductor applications, such as the use of the
droop resistor, PCB design charts show that for a droop
resistor with a required current-carrying capacity of 16A,
and a 45C temperature rise above ambient, the recom-
mended cross section is 275 mil
2
.
W t = 275 mil
2
,
where
W = droop resistor width;
t = droop resistor thickness.
For 1oz. copper, t= 1.37 mils, therefore W = 201 mils =
0.201 in.
R =
,
where
R = droop resistor value;
= 0.71786m-mil (1 oz. copper);
L = droop resistor length;
W = droop resistor width.
R
DROOP
= 3.3m.
3.3m = 0.71786m-mil
.
Hence, L = 1265 mils = 1.265 in.
In layouts where it is impractical to lay out a droop resistor
in a straight line 1265 mils long, the embedded PCB trace
can be "snaked" to fit within the available space.
Thermal Considerations for Power MOSFETs
In order to maintain good reliability, the junction tempera-
ture of the semiconductor components should be kept to a
maximum of 150C or lower. The thermal impedance
(junction to ambient) required to meet this requirement can
be calculated as follows:
Thermal Impedance =
A heatsink may be added to TO-220 components to reduce
their thermal impedance. A number of PC board layout
techniques such as thermal vias and additional copper foil
area can be used to improve the power handling capability
of surface mount components.
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing
for compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions.
These components are not required for regulator operation
and experimental results may allow them to be eliminated.
EMI Management
T
J(MAX)
- T
A
Power
Thermal Management
L
201 mils 1.37 mils
L
W t
50mV
16A
50mV
I
OUT
L
(W t)
L
A
101mV
3.3m 0.79
V
TH(MAX)
R
SENSE(NOM)
0.79
V
TH(MAX)
R
SENSE(MIN)
86mV
3.3m
V
TH(TYP)
R
SENSE(NOM)
Application Information: continued
CS51311
18
The input filter inductor may not be required because bulk
filter and bypass capacitors, as well as other loads located
on the board will tend to reduce regulator di/dt effects on
the circuit board and input power supply. Placement of the
power component to minimize routing distance will also
help to reduce emissions.
When laying out the CPU buck regulator on a printed cir-
cuit board, the following checklist should be used to
ensure proper operation of the CS51311.
1) Rapid changes in voltage across parasitic capacitors and
abrupt changes in current in parasitic inductors are major
concerns for a good layout.
2) Keep high currents out of sensitive ground connections.
3) Avoid ground loops as they pick up noise. Use star or
single point grounding.
4) For high power buck regulators on double-sided PCBs a
single ground plane (usually the bottom) is recommended.
5) Even though double sided PCBs are usually sufficient
for a good layout, four-layer PCBs are the optimum
approach to reducing susceptibility to noise. Use the two
internal layers as the Power and Gnd planes, the top layer
for the power connections, and component vias, and the
bottom layer for noise sensitive traces.
6) Keep the inductor switching node small by placing the
output inductor, switching and synchronous FETs close
together.
7) The MOSFET gate traces to the IC must be as short,
straight, and wide as possible.
8) Use fewer, but larger output capacitors, keep the capaci-
tors clustered, and use multiple layer traces with heavy
copper to keep the parasitic resistance low.
9) Place the switching MOSFET as close to the +5V input
capacitors as possible.
10) Place the output capacitors as close to the load as
possible.
11) Place the V
FB
,V
OUT
filter resistors (510) in series with
the V
FB
and V
OUT
pins as close as possible to the pins.
12) Place the C
OFF
and COMP capacitor as close as possible
to the C
OFF
and COMP pins.
13) Place the current limit filter capacitor between the V
FB
and V
OUT
pins, as close as possible to the pins.
14) Connect the filter components of the following pins:
V
FB
, V
OUT
, C
OFF
, and COMP to the Gnd pin with a single
trace, and connect this local Gnd trace to the output capaci-
tor Gnd.
15) The "Droop" Resistor (embedded PCB trace) has to be
wide enough to carry the full load current.
16) Place the V
CC
bypass capacitor as close as possible to
the IC.
Layout Guidelines
Thermal Data
14L
SO Narrow
R
JC
typ
30
C/W
R
JA
typ
125
C/W
D
Lead Count
Metric
English
Max
Min
Max
Min
14L SO Narrow
8.75
8.55
.344
.337
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES)
PACKAGE THERMAL DATA
Ordering Information
Part Number
Description
CS51311GD14
14L SO Narrow
CS51311GDR14
14L SO Narrow (tape & reel)
19
1999 Cherry Semiconductor Corporation
Rev. 3/11/99
CS51311
Cherry Semiconductor Corporation reserves the right to
make changes to the specifications without notice. Please
contact Cherry Semiconductor Corporation for the latest
available information.
Surface Mount Narrow Body (D); 150 mil wide
1.27 (.050) BSC
0.51 (.020)
0.33 (.013)
6.20 (.244)
5.80 (.228)
4.00 (.157)
3.80 (.150)
1.57 (.062)
1.37 (.054)
D
0.25 (0.10)
0.10 (.004)
1.75 (.069) MAX
1.27 (.050)
0.40 (.016)
REF: JEDEC MS-012
0.25 (.010)
0.19 (.008)
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