Features
s
Synchronous Switching
Regulator Controller for CPU
V
CORE
s
Dual N-Channel MOSFET
Synchronous Buck Design
s
V
2
TM
Control Topology
s
200ns Transient Loop Response
s
5 bit DAC with 1.2% Tolerance
s
Hiccup Mode Overcurrent
Protection
s
40ns Gate Rise and Fall Times
(3.3nF load)
s
65ns Adaptive FET Non-overlap
Time
s
Adaptive Voltage Positioning
s
Power-Good Output Monitors
Regulator Output
s
5V/12V or 12V-only Operation
s
V
CC
Monitor Provides Under
Voltage Lockout
s
OVP Output Monitors Regulator
Output
s
Multifunction COMP Pin
Provides ENABLE, Soft Start,
and Hiccup Timing in
Addition to Control Loop
Compensation
Package Options
CS51312
Synchronous CPU Buck Controller
for 12V Only Applications
CS51312
Description
Application Diagram
GATE(H)
V
OUT
VID0
VID1
VID2
VID3
VID4
V
FB
V
CC2
PWRGD
OVP
GATE(L)
Gnd
COMP
C
OFF
V
CC1
1
16 Lead SO Narrow
1
Pentium is a registered trademark of Intel Corporation.
A Company
V
2
is a trademark of Switch Power, Inc.
Rev. 3/11/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
12V to 16A high performance converter.
The CS51312 is a synchronous dual
NFET Buck Regulator Controller. It is
designed to power the core logic of
the latest high performance CPUs and
ASICs from a single 12V input. It uses
the V
2
TM
control method to achieve
the fastest possible transient response
and best overall regulation. It incor-
porates many additional features
required to ensure the proper opera-
tion and protection of the CPU and
Power system. The CS51312 provides
the industry's most highly integrated
solution, minimizing external compo-
nent count, total solution size, and
cost.
The CS51312 is specifically designed
to power Intel's Pentium
II processor
and includes the following features:
5-bit DAC with 1.2% tolerance,
Power-Good output, overcurrent hic-
cup mode protection, overvoltage
protection, V
CC
monitor, Soft Start,
adaptive voltage positioning, adap-
tive FET non-overlap time, and
remote sense. The CS51312 will oper-
ate over a 9V to 20V (V
CC2
) range
using either single or dual input volt-
age and is available in 16 lead narrow
body surface mount package.
R2
200
C9
0.01
F
C10
1
F
C19
1000pF
12V
C1
1.0
F
D1
SS16GICT-ND
R1
22
D2
ZM4746ACT-ND
V
ID4
V
ID3
V
ID2
V
ID1
C
OFF
COMP
V
ID0
V
CC2
V
CC1
V
FB
GATE(H)
GATE(L)
Gnd
OVP
PWRGD
V
OUT
CS51312
12V
C2 C3 C4
220
F
16SV220
C6
0.010
F
FY10AAJ-03A
FY10AAJ-03A
Q1
Q2
Q3
FY10AAJ-03A
FY10AAJ-03A
Q4
D3
SS12GICT-ND
OVP
PWRGD
R3
10k
L1
1.2
H
R4
0.004
C14 C15
470
F
C11 C12 C13
470
F
1.25V to 3.5V
T510X477K006AS4394
9
8
6
10
12
11
13
14
15
16
1
2
3
4
5
7
1
DAC
ENABLE
+
+
+
+
+
+
+
+
1
2
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
Absolute Maximum Ratings
Pin Symbol
Pin Name
V
MAX
V
MIN
I
SOURCE
I
SINK
CS51312
Operating Junction Temperature, T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C
Lead Temperature Soldering
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 sec. max above 183C, 230C peak
Storage Temperature Range, T
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C
ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
V
CC1
IC Bias and Low Side Driver
16V
-0.3V
N/A
1.5A Peak
Power Input
200mA
V
CC2
IC High Side Driver Power Input
20V
-0.3V
N/A
1.5A Peak
200mA
COMP
Compensation Pin
6V
-0.3V
1mA
5mA
V
FB
, V
OUT
, V
ID0-4
Voltage Feedback Input, Output
6V
-0.3V
1mA
1mA
Voltage Sense Pin, Voltage
ID DAC Inputs
C
OFF
Off-Time Pin
6V
-0.3V
1mA
50mA
GATE(H)
High-Side FET Driver
20V
-0.3V DC
1.5APeak
1.5A Peak
GATE(L)
Low-Side FET Driver
16V
200mA DC 200mA DC
PWRGD
Power-Good Output
6V
-0.3V
1mA
30mA
OVP
Overvoltage Protection
15V
-0.3V
30mA
1mA
Gnd
Ground
0V
0V
1.5A Peak
N/A
200mA DC
1,2,3,4,5
V
IDO
V
ID4
Voltage ID DAC inputs. These pins are internally pulled up to
5.65V if left open. V
ID4
selects the DAC range. When V
ID4
is
high (logic one), the Error Amp reference range is 2.125V to
3.525V with 100mV increments. When V
ID4
is low (logic zero),
the Error amp reference voltage is 1.325V to 2.075V with 50mV
increments.
6
V
FB
Error amp inverting input, PWM comparator non-inverting
input, current limit comparator non-inverting input, PWRGD
and OVP comparator input.
7
V
OUT
Current limit comparator inverting input.
8
V
CC1
Input power supply pin for the internal circuitry and low side
gate driver. Decouple with filter capacitor to Gnd.
9
V
CC2
Input power supply pin for the high side gate driver.
Decouple with filter capacitor to Gnd.
10
GATE(H)
High side switch FET driver pin .
11
Gnd
Ground pin and IC substrate connection.
12
GATE(L)
Low side synchronous FET driver pin.
13
OVP
Overvoltage protection pin. Drives high when overvoltage
condition is detected on V
FB
.
14
PWRGD
Power-Good Output. Open collector output drives low when
V
FB
is out of regulation.
15
C
OFF
Off-Time Capacitor Pin. A capacitor from this pin to Gnd sets
the off time for the regulator
16
COMP
Error amp output. PWM comparator inverting input.
A capacitor on this pin provides error amp compensation, and
determines the Soft Start and hiccup timing. Pulling COMP
below 1.1V (typ) turns off both GATE drivers and shuts down
the regulator.
Electrical Characteristics: 0C < T
A
< 70C; 0C < T
J
< 125C; 9V < V
CC1
< 14V; 9V V
CC2
20V;
2.0V DAC Code(V
ID4
= V
ID3
=V
ID2
= V
ID1
= 0, V
ID0
= 1), C
GATE(H)
= C
GATE(L)
= 3.3nF, C
OFF
= 390pF; Unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3
CS51312
s
Voltage Identification DAC
Measure V
FB
= V
COMP
, V
CC
= 12V (Note 1)
75C T
J
125C
25C T
J
75C
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
MIN
TYP
MAX
TOL
MIN
TYP
MAX
TOL
UNIT
s
Error Amplifier
V
FB
Bias Current
0.2V V
FB
3.5V
-7.0
0.1
7.0
A
COMP Source Current
V
COMP
= 1.2V to 3.6V; V
FB
= 1.9 V
15
30
60
A
COMP Sink Current
V
COMP
=1.2V; V
FB
= 2.1V;
30
60
120
A
Open Loop Gain
C
COMP
= 0.1F
80
dB
Unity Gain Bandwidth
C
COMP
= 0.1F
50
kHz
PSRR @ 1kHz
C
COMP
= 0.1F
70
dB
Transconductance
32
mmho
Output Impedance
0.5
M
1
0
0
0
0
3.483
3.525
3.567
1.2%
3.455
3.525
3.596
2.0%
V
1
0
0
0
1
3.384
3.425
3.466
1.2%
3.357
3.425
3.494
2.0%
V
1
0
0
1
0
3.285
3.325
3.365
1.2%
3.259
3.325
3.392
2.0%
V
1
0
0
1
1
3.186
3.225
3.264
1.2%
3.161
3.225
3.290
2.0%
V
1
0
1
0
0
3.087
3.125
3.163
1.2%
3.063
3.125
3.188
2.0%
V
1
0
1
0
1
2.989
3.025
3.061
1.2%
2.965
3.025
3.086
2.0%
V
1
0
1
1
0
2.890
2.925
2.960
1.2%
2.875
2.925
2.975
1.7%
V
1
0
1
1
1
2.791
2.825
2.859
1.2%
2.777
2.825
2.873
1.7%
V
1
1
0
0
0
2.692
2.725
2.758
1.2%
2.679
2.725
2.771
1.7%
V
1
1
0
0
1
2.594
2.625
2.657
1.2%
2.580
2.625
2.670
1.7%
V
1
1
0
1
0
2.495
2.525
2.555
1.2%
2.482
2.525
2.568
1.7%
V
1
1
0
1
1
2.396
2.425
2.454
1.2%
2.389
2.425
2.461
1.5%
V
1
1
1
0
0
2.297
2.325
2.353
1.2%
2.290
2.325
2.360
1.5%
V
1
1
1
0
1
2.198
2.225
2.252
1.2%
2.192
2.225
2.258
1.5%
V
1
1
1
1
0
2.099
2.125
2.151
1.2%
2.093
2.125
2.157
1.5%
V
0
0
0
0
0
2.050
2.075
2.100
1.2%
2.044
2.075
2.106
1.5%
V
0
0
0
0
1
2.001
2.025
2.049
1.2%
1.995
2.025
2.055
1.5%
V
0
0
0
1
0
1.953
1.975
1.997
1.1%
1.945
1.975
2.005
1.5%
V
0
0
0
1
1
1.904
1.925
1.946
1.1%
1.896
1.925
1.954
1.5%
V
0
0
1
0
0
1.854
1.875
1.896
1.1%
1.847
1.875
1.903
1.5%
V
0
0
1
0
1
1.805
1.825
1.845
1.1%
1.798
1.825
1.852
1.5%
V
0
0
1
1
0
1.755
1.775
1.795
1.1%
1.748
1.775
1.802
1.5%
V
0
0
1
1
1
1.706
1.725
1.744
1.1%
1.699
1.725
1.751
1.5%
V
0
1
0
0
0
1.656
1.675
1.694
1.1%
1.650
1.675
1.700
1.5%
V
0
1
0
0
1
1.607
1.625
1.643
1.1%
1.601
1.625
1.649
1.5%
V
0
1
0
1
0
1.558
1.575
1.593
1.1%
1.551
1.575
1.599
1.5%
V
0
1
0
1
1
1.508
1.525
1.542
1.1%
1.502
1.525
1.548
1.5%
V
0
1
1
0
0
1.459
1.475
1.491
1.1%
1.453
1.475
1.497
1.5%
V
0
1
1
0
1
1.409
1.425
1.441
1.1%
1.404
1.425
1.446
1.5%
V
0
1
1
1
0
1.360
1.375
1.390
1.1%
1.354
1.375
1.396
1.5%
V
0
1
1
1
1
1.310
1.325
1.340
1.1%
1.305
1.325
1.345
1.5%
V
1
1
1
1
1
1.225
1.250
1.275
2.0%
1.225
1.250
1.275
2.0%
V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4
CS51312
Electrical Characteristics: 0C < T
A
< 70C; 0C < T
J
< 125C; 9V < V
CC1
< 14V; 9V V
CC2
20V;
2.0V DAC Code(V
ID4
= V
ID3
=V
ID2
= V
ID1
= 0, V
ID0
= 1), C
GATE(H)
= C
GATE(L)
= 3.3nF, C
OFF
= 390pF; Unless otherwise stated.
Line Regulation
9V V
CC1
14V
0.01
%/V
Input Threshold
V
ID4
, V
ID3
, V
ID2
, V
ID1
, V
ID0
1.00
1.25
2.40
V
Input Pull-up Resistance
V
ID4
, V
ID3
, V
ID2
, V
ID1
, V
ID0
25
50
100
k
Pull-up Voltage
5.48
5.65
5.82
V
s
GATE(H) and GATE(L)
High Voltage at 100mA
Measure V
CC1/2
GATE(L)/(H)
1.2
2.1
V
Low Voltage at 100mA
Measure GATE(L)/(H)
1.0
1.5
V
Rise Time
1.6V < GATE(H)/(L) < (V
CC1/2
2.5V)
40
80
ns
Fall Time
(V
CC1/2
2.5V) > GATE(L)/(H) > 1.6V
40
80
ns
GATE(H) to GATE(L) Delay
GATE(H)<2V, GATE(L)>2V, V
CC1/2
= 12V 30
65
110
ns
GATE(L) to GATE(H) Delay
GATE(L)<2V, GATE(H)>2V,V
CC1/2
= 12V 30
65
110
ns
GATE pull-down
Resistance to Gnd (Note 2)
20
50
115
k
s
Overcurrent Protection
OVC Comparator Offset Voltage
0V V
OUT
3.5V
77
86
101
mV
Discharge Threshold Voltage
0.2
0.25
0.3
V
V
OUT
Bias Current
0.2V V
OUT
3.5V
-7.0
0.1
7.0
A
OVC Latch Discharge Current
V
COMP
= 1V
100
800
2500
A
s
PWM Comparator
PWM Comparator Offset Voltage 0V V
FB
3.5V
0.99
1.10
1.23
V
Transient Response
V
FB
= 0 to 3.5V
200
300
ns
s
C
OFF
Off-Time
1.0
1.6
2.3
s
Charge Current
V
COFF
= 1.5V
550
A
Discharge Current
V
COFF
= 1.5V
25
mA
s
Power-Good Output
PWRGD Sink Current
V
FB
= 1.7V, V
PWRGD
= 1V
0.5
4
15
mA
PWRGD Upper Threshold
% of nominal DAC code
5
8.5
12
%
PWRGD Lower Threshold
% of nominal DAC code
-12
-8.5
-5
%
PWRGD Output Low Voltage
V
FB
= 1.7V, I
PWRGD
= 500A
0.2
0.3
V
s
Overvoltage Protection (OVP) Output
OVP Source Current
OVP = 1V
1
10
25
mA
OVP Threshold
% of nominal DAC code
5
8.5
12
%
OVP Pull-up Voltage
I
OVP
= 1mA, V
CC1
- V
OVP
1.1
1.5
V
CS51312
5
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Electrical Characteristics: 0C < T
A
< 70C; 0C < T
J
< 125C; 9V < V
CC1
< 14V; 9V V
CC2
20V;
2.0V DAC Code(V
ID4
= V
ID3
=V
ID2
= V
ID1
= 0, V
ID0
= 1), C
GATE(H)
= C
GATE(L)
= 3.3nF, C
OFF
= 390pF; Unless otherwise stated.
Block Diagram
s
General Electrical Specifications
V
CC1
Monitor Start Threshold
7.9
8.4
8.9
V
V
CC1
Monitor Stop Threshold
7.6
8.1
8.6
V
Hysteresis
Start - Stop
0.15
0.30
0.60
V
V
CC1
Supply Current
No Load on GATE(H), GATE(L)
9.5
16
mA
V
CC2
Supply Current
No Load on GATE(H), GATE(L)
2.5
4.5
mA
Note 1: The IC power dissipation in a typical application with V
CC
= 12V, switching frequency f
SW
= 250kHz, 50nc
MOSFETs and R
JA
= 115C/W yields an operating junction temperature rise of approximately 52C, and a junction tem-
perature of 77C with an ambient temperature of 25C.
Note 2: Guaranteed by design, not 100% tested in production.
+
-
+
-
+
-
V
FB
COMP
C
OFF
OFF
TIME
PWM COMP
DISCHARGE
COMP
+
-
V
OUT
V
ID0
V
ID1
V
ID2
V
ID3
V
ID4
DAC
+
-
+
-
+
-
1.1V
EA
CURRENT LIMIT
+
-
86mV
0.25V
FAULT
LATCH
R
S
Q
V
CC1
OVP
PWRGD
Gnd
GATE(L)
GATE(H)
V
CC1
UVLO
NONOVERLAP
LOGIC
+
-
V
CC2
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