1
5V, 750mA Low Dropout Linear
Regulator with Lower RESET Threshold
Features
s
5V +/- 3% Regulated
Output
s
Low Dropout Voltage
(0.6V @ 0.5A)
s
750mA Output Current
Capability
s
Reduced
Threshold
for use with 4V Micro-
processors
s
Externally Programmed
Delay
s
Fault Protection
Reverse Battery
60V, -50V Peak Transient
Voltage
Short Circuit
Thermal Shutdown
RESET
RESET
Package Options
5 Lead TO-220
CS8129
1
V
IN
NC
NC
Gnd
Gnd
NC
Delay
RESET
V
OUT
NC
V
OUT(SENSE)
Gnd
Gnd
Gnd
NC
NC
Description
The CS8129 is a precision 5V linear reg-
ulator capable of sourcing 750mA.
The
threshold voltage has been
lowered to 4.2V so that the regulator
can be used with 4V microprocessors.
The lower
threshold also per-
mits operation under low battery condi-
tions (5.5V plus a diode). The
s
delay time is externally programmed
using a discrete RC network. During
power up, or when the output goes out
of regulation,
remains in the
low state for the duration of the delay.
This function is independent of the
input voltage and will function correct-
ly as long as the output voltage remains
at or above 1V. Hysteresis is included in
the Delay and the
comparators
to improve noise immunity. A latching
discharge circuit is used to discharge
the delay capacitor when it is triggered
by a brief fault condition.
The regulator is protected against a
variety of fault conditions: i.e. reverse
battery, overvoltage, short circuit and
thermal runaway conditions. The regu-
lator is protected against voltage tran-
sients ranging from -50V to +40V. Short
circuit current is limited to 1.2A (typ).
The CS8129 is packaged in a 5 lead
TO220 and a 16 lead surface mount
package.
RESET
RESET
RESET
RESET
RESET
Block Diagram
V
OUT
V
IN
Over Voltage
Shutdown
Pre-
Regulator
Regulated Supply
for Circuit Bias
Bandgap
Reference
Anti-Saturation
and
Current Limit
-
+
+
-
Q
R
S
+
-
+
-
Delay
Gnd
V
OUTSENSE
Error
Amplifier
Delay Comparator
Latching Discharge
Charge
Current
Generator
RESET
Thermal
Shutdown
V
DISCHARGE
CS8129
1
V
IN
2
3
Gnd
4
Delay
5
V
OUT
RESET
1
16 Lead SOIC Wide
A Company
Rev. 3/31/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
* To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable.
Delay Time =
= C
Delay
x 3.5 x 10
5
(typ)
Note 1: assuming ideal capacitor
C
Delay
x V
Delay Threshold Charge
I
Charge
Electrical Characteristics:
-40C T
A
+ 125C, -40C T
J
+150C, 6V V
IN
26V, 5mA I
OUT
500mA, R
= 4.7k to V
OUT
unless otherwise noted*
RESET
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Absolute Maximum Ratings
Input Operating Range..................................................................................................................................................-0.5 to 26V
Power Dissipation.............................................................................................................................................Internally Limited
Peak Transient Voltage (46V Load Dump @ 14V V
IN
) ...............................................................................................-50V, 60V
Output Current .................................................................................................................................................Internally Limited
ESD Susceptibility (Human Body Model)..............................................................................................................................4kV
Junction Temperature .............................................................................................................................................-55C to 150C
Storage Temperature...............................................................................................................................................-55C to 150C
Lead Temperature Soldering
Wave Solder (through hole styles only) .....................................................................................10 sec. max, 260C peak
Reflow (SMD styles only) ......................................................................................60 sec. max above 183C, 230C peak
CS8129
2
s
Output Stage (V
OUT
)
Output Voltage
4.85
5.00
5.15
V
Dropout Voltage
I
OUT
= 500mA
0.35
0.60
V
Supply Current
I
OUT
10mA
2
7
mA
I
OUT
100mA
6
12
I
OUT
500mA
55
100
Line Regulation
6V V
IN
26V, I
OUT
= 50mA
5
50
mV
Load Regulation
50mA I
OUT
500mA, V
IN
= 14V
10
50
mV
Ripple Rejection
f = 120Hz, V
IN
= 7 to 17V,
54
75
dB
I
OUT
= 250mA
Current Limit
0.75
1.20
A
Overvoltage Shutdown
32
40
V
Reverse Polarity Input
V
OUT
-0.6V, 10 Load
-15
-30
V
Voltage DC
Thermal Shutdown
Guaranteed by Design
150
180
210
C
s
and Delay Functions
Delay Charge Current
V
DELAY
= 2V
5
10
15
A
Threshold
V
OUT
Increasing, V
RT(ON)
4.05
4.35
4.50
V
V
OUT
Decreasing, V
RT(OFF)
4.00
4.20
4.45
V
Hysteresis
V
RH
=V
RT(ON)
- V
RT(OFF)
50
150
250
mV
Delay Threshold
Charge, V
DC(HI)
3.25
3.50
3.75
V
Discharge, V
DC(LO)
2.85
3.10
3.35
V
Delay Hysteresis
200
400
800
mV
Output Voltage Low1V < V
OUT
< V
RT(L)
, 3k to V
OUT
0.1
0.4
V
Output Leakage
V
OUT
> V
RT(H)
0
10
A
Current
Delay Capacitor
Discharge Latched ON,
0.2
0.5
V
Discharge Voltage
V
OUT
> V
RT
Delay Time
C
DELAY
= 0.1F (Note 1)
16
32
48
ms
RESET
RESET
RESET
RESET
RESET
3
Typical Performance Characteristics
0.0
0.0
I
CQ
(mA)
V
IN
(V)
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
55.0
125C
25C
-40C
R
load
= 25
W
0.0
0.0
I
CQ
(mA)
V
IN
(V)
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
20.0
40.0
60.0
80.0
100.0
120.0
R
load
= 6.67
W
R
load
= 10
W
R
load
= 25
W
R
load
= NO LOAD
Room Temp.
0.0
0.0
V
OUT
(V)
V
IN
(V)
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
R
load
= 25
W
125C
25C
-40C
Output Voltage vs Input Voltage over Temperature
Quiescent Current vs Input Voltage over Load Resistance
Quiescent Current vs Input Voltage over Temperature
0.0
0.0
V
OUT
(V)
V
IN
(V)
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Rload =
NO LOAD
Rload = 6.67
W
Rload = 10
W
Room Temp.
V
OUT
vs. V
IN
over R
LOAD
Package Lead Description
PACKAGE LEAD #
LEAD SYMBOL
FUNCTION
CS8129
-100
0
LINE REGULA
TION (mV)
OUTPUT CURRENT (mA)
-80
-60
-40
-20
0
20
40
60
80
100
100
200
300
400
500
600
700
800
V
IN
6-26V
TEMP = 25C
TEMP = -40C
TEMP = 125C
-14
0
LOAD REGULA
TION (mV)
OUTPUT CURRENT (mA)
-12
-10
-8
-6
-4
-2
0
2
4
6
100
200
300
400
500
600
700
800
TEMP = 25C
TEMP = 125C
V
IN
= 14V
TEMP = -40C
Load Regulation vs. Output Current
Line Regulation vs. Output Current
R
load
=25
16L SOIC Wide
5L TO-220
1
1
V
IN
Unregulated supply voltage to IC.
16
5
V
OUT
Regulated 5V output.
4, 5, 11, 12, 13
3
Gnd
Ground connection.
8
4
Delay
Timing capacitor for
function.
6
2
CMOS/TTL compatible output lead.
goes low whenev-
er V
OUT
drops below 6% of it's regulated value.
14
N/A
V
OUT(SENSE)
Remote sensing of output voltage.
RESET
RESET
RESET
4
CS8129
Test & Application Circuit
C
IN
*
100nF
V
IN
Delay
Gnd
RESET
V
OUT
CS8129
C
OUT
**
10
mF to 100mF
R
RST
4.7k
W
Delay
0.1
mF
0
0
DROPOUT
VOL
T
AGE (mV)
OUTPUT CURRENT (mA)
100
200
300
400
500
600
700
800
100
200
300
400
500
600
700
800
900
25C
-40C
125C
0
0
QUIESCENT
CURRENT
(mA)
OUTPUT CURRENT (mA)
10
20
30
40
50
60
70
80
90
100
100
200
300
400
500
600
700
800
V
IN
= 14V
125C
25C
-40C
0
10
0
REJECTION (dB)
FREQUENCY (Hz)
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
20
30
40
50
60
70
80
90
I
OUT
= 250mA
C
OUT
= 10
mF, ESR = 10W
C
OUT
= 10
mF, ESR = 1W
C
OUT
= 10
mF, ESR = 1 & 0.1mF,
ESR = 0
Ripple Rejection
Quiescent Current vs. Output Current
Dropout Voltage vs. Output Current
Typical Performance Characteristics Continued
10
0
ESR (ohms)
Output Current (mA)
10
1
10
2
10
3
10
1
10
2
10
3
10
-4
10
0
10
-1
10
-2
10
-3
C
OUT
= 68
mF
C
OUT
= 47
mF
C
OUT
= 47/68
mF
Stable Region
Output Capacitor ESR
*C
IN
required if regulator is far from the power source filter.
**C
OUT
required for stability.
The CS8129
function has hysteresis on both the
reset and delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1V.
The
circuit output is an open collector type with
ON and OFF parameters as specified. The
output
NPN transistor is controlled by the two circuits described
(see Block Diagram).
This circuit monitors output voltage, and when output
voltage is below the specified minimum causes the
output transistor to be in the ON (saturation)
state. When the output voltage is above the specified level,
this circuit permits the
output transistor to go into
the OFF state if allowed by the
Delay circuit.
This circuit provides a programmable (by external capaci-
tor) delay on the
output lead. The Delay lead pro-
vides source current to the external delay capacitor only
when the "Low Voltage Inhibit" circuit indicates that out-
put voltage is above V
RT(ON)
. Otherwise, the Delay lead
sinks current to ground (used to discharge the delay
capacitor). The discharge current is latched ON when the
output voltage is below V
RT(OFF)
. The Delay capacitor is
fully discharged anytime the output voltage falls out of
regulation, even for a short period of time. This feature
ensures a controlled
pulse is generated following
detection of an error condition. The circuit allows
the
output transistor to go to the OFF (open) state
only when the voltage on the Delay lead is higher than
V
DC(HI)
.
The Delay time for the
function is calculated from
the formula:
Delay time =
Delay time = C
Delay(F)
x
3.2
x
10
5
If C
Delay
=0.1F, Delay time (ms)=32ms 50%: i.e. 16ms to
48ms. The tolerance of the capacitor must be taken into
account to calculate the total variation in the delay time.
C
Delay
x V
Delay Threshold
I
Charge
RESET
RESET
RESET
RESET
Reset Delay Circuit
RESET
RESET
RESET
Low Voltage Inhibit Circuit
RESET
RESET
RESET
5
(1)
(2)
(3)
(2)
Delay
V
OUT
V
RT(ON)
V
RT(OFF)
V
RH
V
DC(HI)
V
DC(LO)
V
DH
t
Delay
V
DIS
V
RL
RESET
(1) = No Delay Capacitor
(2) = With Delay Capacitor
(3) = Max:
Voltage (1.0V)
RESET
Circuit Waveform
RESET
Circuit Functional Description
RESET
CS8129
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