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Электронный компонент: Pm49FL004T-33JCE

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FEATURES
PMC
2 Mbit / 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory
Programmable Microelectronics Corp.
Issue Date: December, 2003 Rev:1.4
Pm49FL002 / Pm49FL004
1
Single Power Supply Operation
-
Low voltage range: 3.0 V - 3.6 V
Standard Intel Firmware Hub/LPC Inter-
face
-
Read compatible to Intel
82802 Firmware
Hub devices
-
Conforms to Intel LPC Interface Specification
Revision 1.1
Memory Configuration
-
Pm49FL002: 256K x 8 (2 Mbit)
-
Pm49FL004: 512K x 8 (4 Mbit)
Cost Effective Sector/Block Architecture
-
Pm49FL002: Sixty-four uniform 4 Kbyte
sectors, or sixteen uniform 16 Kbyte blocks
(sector group)
-
Pm49FL004: One hundred and twenty-eight
uniform 4 Kbyte sectors, or eight uniform 64
Kbyte blocks (sector group)
Top Boot Block
-
Pm49FL002: 16 Kbyte top Boot Block
-
Pm49FL004: 64 Kbyte top Boot Block
Automatic Erase and Program Operation
-
Build-in automatic program verification for
extended product endurance
-
Typical 25 s/byte programming time
-
Typical 50 ms sector/block/chip erase time
Two Configurable Interfaces
-
In-System hardware interface: Auto detection
of Firmware Hub (FWH) or Low Pin Count
(LPC) memory cycle for in-system read and
write operations
-
Address/Address-Multiplexed (A/A Mux)
interface for programming on EPROM Pro-
grammers during manufacturing
Firmware HUB (FWH)/Low Pin Count
(LPC) Mode
-
33 MHz synchronous operation with PCI bus
-
5-signal communication interface for in-
system read and write operations
-
Standard SDP Command Set
-
Data# Polling and Toggle Bit features
-
Register-based read and write protection for
each block (FWH mode only)
-
4 ID pins for multiple Flash chips selection
(FWH mode only)
-
5 GPI pins for General Purpose Input Register
-
TBL# pin for hardware write protection to Boot
Block
-
WP# pin for hardware write protection to whole
memory array except Boot Block
Address/Address Multiplexed (A/A Mux)
Mode
-
11-pin multiplexed address and 8-pin data I/O
interface
-
Supports fast programming on EPROM
programmers
-
Standard SDP Command Set
-
Data# Polling and Toggle Bit features
Lower Power Consumption
-
Typical 2 mA active read current
-
Typical 7 mA program/erase current
High Product Endurance
-
Guarantee 100,000 program/erase cycles per
single sector (preliminary)
-
Minimum 20 years data retention
Compatible Pin-out and Packaging
-
32-pin (8 mm x 14 mm) VSOP
-
32-pin PLCC
-
Optional lead-free (Pb-free) package
Hardware Data Protection
PMC and P-Flash are registered trademark of Programmable Microelectronics Corporation.
Intel is a registered trademark of Intel Corporation.
Programmable Microelectronics Corp.
Issue Date: December, 2003 Rev: 1.4
PMC
Pm49FL002 / 004
2
GENERAL DESCRIPTION
The Pm49FL002/004 are 2 Mbit/4 Mbit 3.3 Volt-only Flash Memories used as BIOS in PCs and Notebooks. These
devices are designed to use a single low voltage, ranging from 3.0 Volt to 3.6 Volt, power supply to perform in-
system or off-system read, erase and program operations. The 12.0 Volt V
PP
power supply are not required for the
program and erase operations of devices. The devices conform to Intel
Low Pin Count (LPC) Interface specification
revision 1.1 and also read-compatible with Intel 82802 Firmware Hub (FWH) for most PC and Notebook applica-
tions. The Pm49FL002/004 support two configurable interfaces: In-system hardware interface which can automatic
detect the FWH or LPC memory cycle for in-system read and write operations, and Address/Address Multiplexed
(A/A Mux) interface for fast manufacturing on EPROM Programmers. These devices are designed to work with both
Intel Family chipset and Non-Intel Family Chipset platforms, it will provide PC and Notebook manufacturers great
flexibility and simplicity for design, procurement, and material inventory.
The memory array of Pm49FL002 is divided into uniform 4 Kbyte sectors, or uniform 16 Kbytes blocks (sector
group - consists of four adjecent sectors). The memory array of Pm49FL004 is divided into uniform 4 Kbyte sectors,
or uniform 64 Kbyte blocks (sector group - consists of sixteen adjecent sectors). The sector or block erase feature
allows users to flexibly erase a memory area as small as 4 Kbyte or as large as 64 Kbyte by one single erase
operation without affecting the data in others. The chip erase feature allows the whole memory to be erased in one
single erase operation. The devices can be programmed on a byte-by-byte basis after performing the erase opera-
tion.
The program operation of Pm49FL002/004 is executed by issuing the program command code into command
register. The internal control logic automatically handles the programming voltage ramp-up and timing. The erase
operation of the devices is executed by issuing the sector, block, or chip erase command code into command
register. The internal control logic automatically handles the erase voltage ramp-up and timing. The preprogramming
on the array which has not been programmed is not required before an erase operation. The devices offer Data#
Polling and Toggle Bit functions in FWH/LPC and A/A Mux modes, the progress or completion of program and
erase operations can be detected by reading the Data# Polling on I/O7 or Toggle Bit on I/O6.
The Pm49FL002 has a 16 Kbyte top boot block which can be used to store user security data and code. The
Pm49FL004 has a 64 Kbyte top boot block. The boot block can be write protected by a hardware method controlled
by the TBL# pin or a register-based protection turned on/off by the Block Locking Registers (FWH mode only). The
rest of blocks except boot block in the devices also can be write protected by WP# pin or Block Locking Registers
(FWH mode only).
The Pm49FL002/004 are manufactured on PMC's advanced nonvolatile technology, P-FLASHTM. The devices are
offered in 32-pin VSOP and PLCC packages with optional environmental friendly lead-free package.
Programmable Microelectronics Corp.
Issue Date: December, 2003 Rev: 1.4
PMC
Pm49FL002 / 004
3
CONNECTION DIAGRAMS
20
19
18
17
16
15
14
5
6
7
8
9
10
11
12
13
1
2
3
4
32
31
30
A8
A9
RST#
V
CC
R/C#
A10
I/O1
GND
I/O2
I/O3
I/O4
I/O5
I/O6
I/O0
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
29
28
27
26
25
24
23
22
21
IC
G N D
N C
V
C C
O E #
W E #
I/O7
INIT#
R E S
IC
LAD1
GND
RES
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GND
L A D 0
R E S
T B L #
W P #
GPI1
F W H 0
ID0
GPI1
GPI2
GPI3
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CLK
GPI4
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GPI2
GPI3
V
CC
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RST#
GPI4
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A/A Mux LPC FWH
FWH LPC A/A Mux
RST#
G N D
G N D
N C
N C
N C
N C
N C
V
C C
V
C C
INIT#
L F R A M E # F W H 4
N C
N C
N C
R E S
LAD2
FWH2
LAD3
FWH3
RES
RES
RES
RES
RES
GPI0
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W P #
T B L #
R E S
R E S
R E S
ID1
ID2
ID3
IC
A/A Mux LPC FWH
FWH LPC A/A Mux
OE# INIT# INIT#
WE# LFRAME# FWH4
NC NC NC
I/O7 RES RES
I/O6 RES RES
I/O5 RES RES
I/O4 RES RES
I/O3 LAD3 FWH3
G N D GND GND
I/O2 LAD2 FWH2
I/O1 LAD1 FWH1
I/O0 LAD0 FWH0
A0 RES ID0
A1 RES ID1
A2 RES ID2
A3 RES ID3
V
C C
V
C C
V
C C
NC NC NC
NC NC NC
GND GND GND
IC IC IC
GPI4 GPI4 A10
CLK CLK R/C#
V
C C
V
C C
V
C C
NC NC NC
RST# RST# RST#
GPI3 GPI3 A9
GPI2 GPI2 A8
GPI1 GPI1 A7
GPI0 GPI0 A6
WP# WP# A5
TBL# TBL# A4
32-PIN (8mm x 14mm) VSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A/A Mux LPC FWH
FWH LPC A/A Mux
32-PIN PLCC
Programmable Microelectronics Corp.
Issue Date: December, 2003 Rev: 1.4
PMC
Pm49FL002 / 004
4
PRODUCT ORDERING INFORMATION
Pm49FL00x T -33 J C E
Temperature Range
 C = Commercial (0C to +70C)
Package Type
 J = 32-pin Plastic J-Leaded Chip Carrier (32J)
V = 32-pin (8 mm x 14 mm) VSOP (32V)
Speed Option
Boot Block Location
T = Top Boot Block
PMC Device Number
Pm49FL002 (2 Mbit)
Pm49FL004 (4 Mbit)
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Programmable Microelectronics Corp.
Issue Date: December, 2003 Rev: 1.4
PMC
Pm49FL002 / 004
5
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