CHRONTEL
CHRONTEL
CHRONTEL
CHRONTEL
CHRONTEL
Chrontel
201-0000-056 Rev. 1.0, 3/07/2003
1
CH7301C
Chrontel CH7301 DVI Transmitter Device
1. F
EATURES
DVI Transmitter up to 165M pixels/second
DVI low jitter PLL
DVI hot plug detection
Supporting graphics resolutions up to1600 x 1200 pixels
Providing RGB output
DAC connection detection
Programmable power management
Fully programmable through serial port
Complete Windows and DOS driver support
Low voltage interface support to graphics device
Offered in a 64-pin LQFP package
2. G
ENERAL
D
ESCRIPTION
The CH7301 is a display controller device which accepts a
digital graphics input signal, and encodes and transmits
data through a DVI or DFP (Digital flat panel). The device
accepts data over one 12-bit wide variable voltage data
port which supports four different RGB data formats.
The DVI processor includes a low jitter PLL for generation
of the high frequency serialized clock, and all circuitry
required to encode, serialize and transmit data. The
CH7301 comes in versions able to drive a DFP display at a
pixel rate of up to 165MHz, supporting UXGA resolution
displays. No scaling of input data is performed on the data
output to the DVI device. See Figure 1 for the functional
block diagram of the CH7301.
Figure 1. Functional Block Diagram
XCLK,XCLK*
D[11:0]
H,V,DE
3
12
TDC2,TDC2*
TDC1,TDC1*
TDC0,TDC0*
TLC,TLC*
DVI
Encode
DVI
Serialize
DVI
Driver
DVI PLL
VREF
B (DAC0)
G (DAC1)
Three
8-bit
DAC's
C/H SYNC
ISET
R (DAC2)
VSWING
2
24
24
3
24
2
2
2
2
TLDET*
HPDET
AS
SPC
SPD
GPIO[1:0]
RESET*
Serial Port Control
Data
Latch,
Demux
H,V,DE
Latch
Clock
Driver
2
BCO/V SYNC
CHRONTEL
CH7301C
2
201-0000-056 Rev. 1.0, 3/07/2003
3. P
IN
D
ESCRIPTIONS
3.1 Package Diagram
Figure 2. 64-Pin LQFP
DVDDV
C / H SYNC
G
R
NC
ISET
VDD
GND
GND
AGND
GND
NC
AVDD
GPIO[1] / TLDET*
GPIO[0]
AS
DGND
AG
ND
AV
DD
VSW
I
N
G
TL
C
TL
C*
TDC0
TDC0
*
TDC1
TDC1
*
TDC2
TDC2
*
TVDD
TVDD
TGND
TGND
TGND
DGND
SPD
SPC
RESET*
HPDET
DVDD
VREF
DVDD
AGND
B
Chrontel
XCL
K
XCL
K
*
D[
1
1
]
D[
1
0
]
D[
9
]
D[
8
]
D[
7
]
D[
6
]
D[
5
]
D[
4
]
D[
3
]
D[
2
]
D[
1
]
D[
0
]
DGND
DVDD
H
V
DE
BCO / V SYNC
TLDET*
CH7301
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
25
201-0000-056 Rev. 1.0, 3/07/2003
3
CHRONTEL
CH7301C
3.2 Pin Description
Table 1. Pin Description
64-Pin
LQFP
# Pins Type
Symbol
Description
2
1
In
DE
Data Enable
This pin accepts a data enable signal which is high when active
video data is input to the device, and low all other times. The levels
are 0 to DVDDV, and the VREF signal is used as the threshold level.
This input is used by the DVI.
3
1
In
VREF
Reference Voltage Input
The VREF pin inputs a reference voltage of DVDDV / 2. The signal
is derived externally through a resistor divider and decoupling
capacitor, and will be used as a reference level for data, sync, data
enable and clock inputs.
4
1
In/Out
H
Horizontal Sync Input / Output
This pin receives / sends out horizontal sync input from / output to
the graphics controller.
5
1
In/Out
V
Vertical Sync Input / Output
This pin receives / sends vertical sync input from / output to the
graphics controller.
7
2
In/Out
GPIO[1] /
TLDET*
General Purpose Input - Output[1] /
DVI Detect Output
(Open drain or internal weak pull-up)
This pin provides a general purpose I/O controlled via the serial port
bus. The internal pull-up will be to the DVDD supply.
When the GPIO[1] pin is configured as an input, this pin can be used
to output the DVI detect signal (pulls low when a termination change
has been detected on the HPDET input). This is an open drain
output. The output is released through serial port control.
8
2
In/Out
GPIO[0]
General Purpose Input - Output[0]
(Open drain or internal weak pull-up)
This pin provides a general purpose I/O controlled via the serial port.
This allows an external switch to be used to select NTSC or PAL at
power-up.
9
1
In
HPDET
Hot Plug Detect (internal pull-down)
This input pin determines whether the DVI is connected to a DVI
monitor. When terminated, the monitor is required to apply a
voltage greater than 2.4 volts. Changes on the status of this pin will
be relayed to the graphics controller via the TLDET* or
GPIO[1]/TLDET* pin pulling low.
10
1
In
AS
Address Select (Internal pull-up)
This pin determines the serial port address of the device
(1,1,1,0,1,AS*,AS).
13
1
In
RESET*
Reset * Input (Internal pull-up)
When this pin is low, the device is held in the power-on reset
condition. When this pin is high, reset is controlled through the
serial port register.
14
1
In/Out
SPD
Serial Port Data Input / Output
This pin functions as the serial data pin of the serial port interface,
and uses the DVDD supply.
CHRONTEL
CH7301C
4
201-0000-056 Rev. 1.0, 3/07/2003
64-Pin
LQFP
# Pins Type
Symbol
Description
15
1
In
SPC
Serial Port Clock Input
This pin functions as the clock pin of the
serial port
interface, and
uses the DVDD supply.
19
1
In
VSWING
DVI Swing Control
This pin sets the swing level of the DVI outputs. A 2.4K ohm
resistor should be connected between this pin and TGND using short
and wide traces.
22, 21
2
Out
TDC0,
TDC0*
DVI Data Channel 0 Outputs
These pins provide the DVI differential outputs for data channel 0
(blue).
25, 24
2
Out
TDC1,
TDC1*
DVI Data Channel 1 Outputs
These pins provide the DVI differential outputs for data channel 1
(green).
28, 27
2
Out
TDC2,
TDC2*
DVI Data Channel 2 Outputs
These pins provide the DVI differential outputs for data channel 2
(red).
30, 31
2
Out
TLC,
TLC*
DVI Clock Outputs
These pins provide the differential clock output for the DVI interface
corresponding to data on the TDC[0:2] outputs.
35
1
In
ISET
Current Set Resistor Input
This pin sets the DAC current. A 140 ohm resistor should be
connected between this pin and GND (DAC ground) using short and
wide traces.
37
1
Out
G
Green Output
38
1
Out
R
Red Output
39
1
Out
B
Blue Output
43
1
NC
No Connect
46
1
Out
TLDET*
DVI Detect Output
This pin provides an open drain output which pulls low when a
termination change has been detected on the HPDET input. The
output is released through serial port control.
47
1
Out
BCO /
V SYNC
Buffered Clock Output
This output pin provides a buffered clock output, driven by the
DVDD supply. The output clock can be selected using the BCO reg-
ister. A buffered version of VGA vertical sync can be acquired from
this pin. (Refer to Register 22h, BCO register)
48
1
Out
C / H SYNC
Composite / Horizontal Sync Output
A buffered version of VGA horizontal sync can be acquired from this
pin. (Refer to Register 21h, DC register)
50 55,
58 63
12
In
D[11] - D[0]
Data[11] through Data[0] Inputs
These pins accept the 12 data inputs from a digital video port of a
graphics controller. The levels are 0 to DVDDV, and the VREF
signal is used as the threshold level.
Table 1. Pin Description
201-0000-056 Rev. 1.0, 3/07/2003
5
CHRONTEL
CH7301C
64-Pin
LQFP
# Pins Type
Symbol
Description
57, 56
2
In
XCLK,
XCLK*
External Clock Inputs
These inputs form a differential clock signal input to the CH7301
for use with the H, V, DE and D[11:0] data. If differential clocks
are not available, the XCLK* input should be connected to
VREF. The output clocks from this pad cell are able to have their
polarities reversed under the control of the MCP bit (in register
1Ch).
1, 12, 49
3
Power
DVDD
Digital Supply Voltage (3.3V)
6, 11, 64
3
Power
DGND
Digital Ground
45
1
Power
DVDDV
I/O Supply Voltage (3.3V to 1.1V)
23, 29
2
Power
TVDD
DVI Transmitter Supply Voltage (3.3V)
20, 26, 32 3
Power
TGND
DVI Transmitter Ground
18, 44
2
Power
AVDD
PLL Supply Voltage (3.3V)
16, 17,
41,42
4
Power
AGND
PLL Ground
33
1
Power
VDD
DAC Supply Voltage (3.3V)
34, 36, 40 3
Power
GND
DAC Ground
Table 1. Pin Description
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