Document Outline
- CS4341: 24-Bit, 96 kHz Stereo DAC with Volume Control
- Features
- Description
- TABLE OF CONTENTS
- LIST OF FIGURES
- LIST OF TABLES
- Contacting Cirrus Logic Support
- 1. CHARACTERISTICS AND SPECIFICATIONS
- 2. TYPICAL CONNECTION DIAGRAM
- 3. REGISTER QUICK REFERENCE
- 3.1 MCLK Control (address 00h)
- 3.2 Mode Control (address 01h)
- 3.3 Volume and Mixing Control (address 02h)
- 3.4 Channel A Volume Control (address 03h)
- 3.5 Channel B Volume Control (address 04h)
- 4. REGISTER BIT DESCRIPTION
- 4.1 MASTER CLOCK DIVIDE ENABLE
- Table 1. Master Clock Divide Enable
- 4.2 AUTO-MUTE
- Table 2. Auto-Mute Enable
- 4.3 DIGITAL INTERFACE FORMAT
- Table 3. Digital Interface Formats
- 4.4 DE-EMPHASIS CONTROL
- Table 4. De-emphasis Filter Configurations
- 4.5 POWER ON/OFF QUIESCENT VOLTAGE RAMP
- Table 5. Power On/Off Ramp Enable
- 4.6 POWER DOWN
- Table 6. Power Down Enable
- 4.7 CHANNEL A VOLUME = CHANNEL B VOLUME
- Table 7. A=B Volume Control Enable
- 4.8 SOFT RAMP OR ZERO CROSS ENABLE
- Table 8. Soft Ramp and Zero Cross Enable
- 4.9 ATAPI CHANNEL MIXING AND MUTING
- 4.10 MUTE
- 4.11 VOLUME CONTROL
- Table 11. Digital Volume Settings
- 5. PIN DESCRIPTION
- 6. APPLICATIONS
- 7. CONTROL PORT INTERFACE
- 8. PARAMETER DEFINITIONS
- 9. REFERENCES
- 10. PACKAGE DIMENSIONS
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 1999
(All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CS4341
24-Bit, 96 kHz Stereo DAC with Volume Control
Features
l
Complete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
l
ATAPI Mixing
l
101 dB Dynamic Range
l
89 dBFS THD+N
l
Low Clock Jitter Sensitivity
l
+3 V to +5 V Power Supply
l
Filtered Line Level Outputs
l
On-Chip Digital De-emphasis for 32, 44.1,
and 48 kHz
l
Digital Volume Control with Soft Ramp
94 dB Attenuation
1 dB Step Size
Zero Crossing Click-Free Transitions
l
30 mW with 3 V supply
Description
The CS4341 is a complete stereo digital-to-analog sys-
tem including digital interpolation, fourth-order delta-
sigma digital-to-analog conversion, digital de-emphasis,
volume control, channel mixing and analog filtering. The
advantages of this architecture include: ideal differential
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and tempera-
ture and a high tolerance to clock jitter.
The CS4341 accepts data at audio sample rates from
2 kHz to 100 kHz, consumes very little power and oper-
ates over a wide power supply range. These features are
ideal for DVD, A/V receiver and set-top box systems.
ORDERING INFORMATION
CS4341-KS
16-pin SOIC, -10 to 70 C
CDB4341
Evaluation Board
I
Volume Control
Interpolation Filter
DAC
Analog Filter
Control Port
Volume Control
Interpolation Filter
Analog Filter
Se
r
i
al
P
o
rt
SCL/CCLK
MUTEC
AD0/CS
AOUTA
AOUTB
RST
LRCK
SDATA
MCLK
SDA/CDIN
DAC
External
Mute Control
SCLK
Mixer
2
AUG `99
DS298PP2
CS4341
2
DS298PP2
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5
ANALOG CHARACTERISTICS ................................................................................................ 5
POWER AND THERMAL CHARACTERISTICS....................................................................... 7
DIGITAL CHARACTERISTICS ................................................................................................. 7
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 7
RECOMMENDED OPERATING CONDITIONS ....................................................................... 7
SWITCHING CHARACTERISTICS .......................................................................................... 8
SWITCHING CHARACTERISTICS - CONTROL PORT......................................................... 10
2. TYPICAL CONNECTION DIAGRAM .................................................................................... 12
3. REGISTER QUICK REFERENCE .......................................................................................... 13
3.1 MCLK Control (address 00h) ............................................................................................ 13
3.2 Mode Control (address 01h) ............................................................................................. 13
3.3 Volume and Mixing Control (address 02h)........................................................................ 14
3.4 Channel A Volume Control (address 03h) ........................................................................ 14
3.5 Channel B Volume Control (address 04h) ........................................................................ 14
4. REGISTER BIT DESCRIPTION .............................................................................................. 15
4.1 Master Clock Divide Enable.............................................................................................. 15
4.2 Auto-Mute ......................................................................................................................... 15
4.3 Digital Interface Format..................................................................................................... 16
4.4 De-emphasis Control ........................................................................................................ 16
4.5 Power On/Off Quiescent Voltage Ramp ........................................................................... 17
4.6 Power Down...................................................................................................................... 17
4.7 Channel A Volume = Channel B Volume .......................................................................... 18
4.8 Soft Ramp or Zero Cross Enable...................................................................................... 18
4.9 ATAPI Channel Mixing and Muting ................................................................................... 19
4.10 Mute ................................................................................................................................ 20
4.11 Volume Control ............................................................................................................... 21
5. PIN DESCRIPTION ................................................................................................................. 22
Analog Power - VA.................................................................................................................. 22
Analog Ground - AGND .......................................................................................................... 22
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
I
2
C is a registered trademark of Philips Semiconductors.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.
CS4341
DS298PP2
3
Analog Output - AOUTA and AOUTB..................................................................................... 22
Reference Ground - REF_GND.............................................................................................. 22
Positive Voltage Reference - FILT+........................................................................................ 22
Quiescent Voltage - VQ .......................................................................................................... 22
Master Clock - MCLK ............................................................................................................. 23
Left/Right Clock - LRCK ......................................................................................................... 23
Serial Audio Data - SDATA .................................................................................................... 23
Serial Clock - SCLK ................................................................................................................ 24
Reset - RST ............................................................................................................................ 24
Serial Control Interface Clock - SCL/CCLK ........................................................................... 24
Serial Control Data I/O - SDA/CDIN ....................................................................................... 24
Address Bit / Chip Select - AD0/CS........................................................................................ 24
Mute Control - MUTEC ........................................................................................................... 24
6. APPLICATIONS ..................................................................................................................... 25
6.1 Grounding and Power Supply Decoupling ....................................................................... 25
6.2 Oversampling Modes ....................................................................................................... 25
6.3 Recommended Power-up Sequence ............................................................................... 25
6.4 Use of the Power ON/OFF Quiescent Voltage Ramp ..................................................... 25
7. CONTROL PORT INTERFACE .............................................................................................. 26
7.1 SPI Mode ......................................................................................................................... 26
7.2 I
2
C Compatible Mode ...................................................................................................... 26
7.2 Memory Address Pointer (MAP) ....................................................................................... 27
8. PARAMETER DEFINITIONS .................................................................................................. 33
Total Harmonic Distortion + Noise (THD+N) .......................................................................... 33
Dynamic Range ...................................................................................................................... 33
Interchannel Isolation ............................................................................................................. 33
Interchannel Gain Mismatch ................................................................................................... 33
Gain Error ............................................................................................................................... 33
Gain Drift ................................................................................................................................ 33
9. REFERENCES ........................................................................................................................ 33
10. PACKAGE DIMENSIONS .................................................................................................... 34
LIST OF FIGURES
Figure 1.
External Serial Mode Input Timing ................................................................................. 9
Figure 2.
Internal Serial Mode Input Timing .................................................................................. 9
Figure 3.
Internal Serial Clock Generation .................................................................................... 9
Figure 4.
I
2
C Control Port Timing ................................................................................................ 10
Figure 5.
SPI Control Port Timing ............................................................................................... 11
Figure 6.
Typical Connection Diagram ........................................................................................ 12
Figure 7.
SPI Mode Control Port Formating ................................................................................ 27
Figure 8.
I
2
C Mode Control Port Formating ................................................................................ 27
Figure 9.
Base-Rate Stopband Rejection .................................................................................... 28
Figure 10. Base-Rate Transition Band .......................................................................................... 28
Figure 11. Base-Rate Transition Band (Detail) ............................................................................. 28
Figure 12. Base-Rate Passband Ripple ........................................................................................ 28
Figure 13. High-Rate Stopband Rejection .................................................................................... 28
Figure 14. High-Rate Transition Band ........................................................................................... 28
Figure 15. High-Rate Transition Band (Detail) .............................................................................. 29
Figure 16. High-Rate Passband Ripple ......................................................................................... 29
Figure 17. Output Test Load ......................................................................................................... 29
CS4341
4
DS298PP2
Figure 18. Maximum Loading ........................................................................................................ 29
Figure 19. Power vs. Sample Rate (VA = 5V) ............................................................................... 29
Figure 20. CS4341 Format 0 (I
2
S) ................................................................................................ 30
Figure 21. CS4341 Format 1 (I
2
S) ................................................................................................ 30
Figure 22. CS4341 Format 2 ......................................................................................................... 30
Figure 23. CS4341 Format 3 ......................................................................................................... 31
Figure 24. CS4341 Format 4 ......................................................................................................... 31
Figure 25. CS4341 Format 5 ......................................................................................................... 31
Figure 26. CS4341 Format 6 ......................................................................................................... 32
Figure 27. De-Emphasis Curve ..................................................................................................... 32
Figure 28. ATAPI Block Diagram .................................................................................................. 32
LIST OF TABLES
Table 1. Master Clock Divide Enable ............................................................................................... 15
Table 2. Auto-Mute Enable ............................................................................................................... 15
Table 3. Digital Interface Formats .................................................................................................... 16
Table 4. De-emphasis Filter Configurations ..................................................................................... 16
Table 5. Power On/Off Ramp Enable ............................................................................................... 17
Table 6. Power Down Enable ........................................................................................................... 17
Table 7. A=B Volume Control Enable............................................................................................... 18
Table 8. Soft Ramp and Zero Cross Enable..................................................................................... 19
Table 9. ATAPI Decode .................................................................................................................... 19
Table 10. Mute Enable ..................................................................................................................... 20
Table 11. Digital Volume Settings .................................................................................................... 21
Table 12. Common Clock Frequencies ............................................................................................ 23
CS4341
DS298PP2
5
1.
CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS
(T
A
= 25 C; Logic "1" = VA = 5 V; Logic "0" = AGND;
Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz,
Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for High-Rate Mode = 96 kHz,
SCLK = 6.144 MHz, Measurement Bandwidth 10 Hz to 40 kHz, unless otherwise specified. Test load R
L
= 10 k
,
C
L
= 10 pF (see Figure 17)),
Notes: 1. One-half LSB of triangular PDF dither is added to data.
Parameter
Base-rate Mode
High-Rate Mode
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Dynamic Performance for VA = 5 V
Specified Temperature Range
T
A
-10
-
70
-10
-
70
C
Dynamic Range
(Note 1)
18 to 24-Bit
unweighted
A-Weighted
16-Bit unweighted
A-Weighted
92
96
-
-
97
101
95
99
-
-
-
-
91
95
-
-
96
100
94
98
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 1)
18 to 24-Bit
0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
THD+N
-
-
-
-
-
-
-89
-77
-37
-88
-75
-35
-84
-72
-32
-
-
-
-
-
-
-
-
-
-89
-74
-36
-89
-73
-34
-84
-69
-31
-
-
-
dB
dB
dB
dB
dB
dB
Interchannel Isolation
(1 kHz)
-
100
-
-
100
-
dB
Dynamic Performance for VA = 3 V
Specified Temperature Range
T
A
-10
-
70
-10
-
70
C
Dynamic Range
(Note 1)
18 to 24-Bit
unweighted
A-Weighted
16-Bit unweighted
A-Weighted
99
102
-
-
94
97
93
96
-
-
-
-
97
101
-
-
92
96
91
96
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 1)
18 to 24-Bit
0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
THD+N
-
-
-
-
-
-
-94
-74
-34
-93
-73
-33
-89
-69
-29
-
-
-
-
-
-
-
-
-
-92
-76
-32
-91
-71
-31
-87
-71
-27
-
-
-
dB
dB
dB
dB
dB
dB
Interchannel Isolation
(1 kHz)
-
100
-
-
100
-
dB
CS4341
6
DS298PP2
ANALOG CHARACTERISTICS
(Continued)
Notes: 2. Refer to Figure 18.
3. Filter response is guaranteed by design.
4. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9-16) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
5. For Base-Rate Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For High-Rate Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
6. De-emphasis is not available in High-Rate Mode.
Parameters
Symbol
Min
Typ
Max
Units
Analog Output
Full Scale Output Voltage
0.63VA
0.7VA
0.77VA
Vpp
Quiescent Voltage
V
Q
-
0.5VA
-
VDC
Interchannel Gain Mismatch
-
0.1
-
dB
Gain Drift
-
100
-
ppm/C
AC-Load Resistance
(Note 2)
R
L
3
-
-
k
Load Capacitance
(Note 2)
C
L
-
-
100
pF
Parameter
Base-rate Mode
High-Rate Mode
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Combined Digital and On-chip Analog Filter Response (Note 3)
Passband
(Note 4)
to -0.05 dB corner
to -0.1 dB corner
to -3 dB corner
0
-
0
-
-
-
.4535
-
.4998
-
0
0
-
-
-
-
.4621
.4982
Fs
Fs
Fs
Frequency Response 10 Hz to 20 kHz
-.02
-
+.08
-0.06
-
0
dB
StopBand
.5465
-
-
.577
-
-
Fs
StopBand Attenuation
(Note 5)
50
-
-
55
-
-
dB
Group Delay
tgd
-
9/Fs
-
-
4/Fs
-
s
Passband Group Delay Deviation 0 - 40 kHz
0 - 20 kHz
-
-
-
0.36/Fs
-
-
-
-
1.39/Fs
0.23/Fs
-
-
s
s
De-emphasis Error
Fs = 32 kHz
(Relative to 1 kHz)
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
+.2/-.1
+.05/-.14
+0/-.22
(Note 6)
dB
dB
dB
CS4341
DS298PP2
7
POWER AND THERMAL CHARACTERISTICS
Notes: 7. Refer to Figure 19.
8. Valid with the recommended capacitor values on FILT+ and V
Q
as shown in Figure 1.
DIGITAL CHARACTERISTICS
(T
A
= 25C; VA = 2.7V - 5.5V)
ABSOLUTE MAXIMUM RATINGS
(AGND = 0V; all voltages with respect to ground.)
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND = 0V; all voltages with respect to ground.)
Parameters
Symbol
Min
Typ
Max
Units
Power Supplies
Power Supply Current
normal operation
VA = 5 V
power-down state
I
A
I
A
-
-
15
60
17
-
mA
A
Power Dissipation
(Note 7)
VA = 5 V
normal operation
power-down
-
-
75
0.3
85
-
mW
mW
Power Supply Current
normal operation
VA = 3 V
power-down state
I
A
I
A
-
-
10
30
14
-
mA
A
Power Dissipation
(Note 7)
VA = 3 V
normal operation
power-down
-
-
30
0.09
42
-
mW
mW
Package Thermal Resistance
JA
-
110
-
C/Watt
Power Supply Rejection Ratio (1 kHz)
(Note 8)
(60 Hz)
PSRR
-
-
60
40
-
-
dB
dB
Parameters
Symbol Min Typ
Max
Units
High-Level Input Voltage
VA = 5 V
VA = 3 V
V
IH
2.0
2.0
-
-
-
-
V
V
Low-Level Input Voltage
VA = 5 V
VA = 3 V
V
IL
-
-
-
-
0.8
0.8
V
V
Input Leakage Current
I
in
-
-
10
A
Input Capacitance
-
8
-
pF
Maximum MUTEC Drive Current
-
3
-
mA
Parameters
Symbol
Min
Max
Units
DC Power Supply
VA
-0.3
6.0
V
Input Current, Any Pin Except Supplies
I
in
-
10
mA
Digital Input Voltage
V
IND
-0.3
VA+0.4
V
Ambient Operating Temperature (power applied)
T
A
-55
125
C
Storage Temperature
T
stg
-65
150
C
Parameters
Symbol Min Typ
Max
Units
DC Power Supply
VA
2.7
5.0
5.5
V
CS4341
8
DS298PP2
SWITCHING CHARACTERISTICS
(T
A
= -10 to 70C; VA = 2.7V - 5.5V; Inputs: Logic 0 = 0V,
Logic 1 = VA, C
L
= 20pF)
Notes: 9. In Internal SCLK Mode, the Duty Cycle must be 50% 1/2 MCLK Period.
10. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK
ratio. (See Figures 20-26)
Parameters
Symbol Min Typ
Max
Units
Input Sample Rate
Fs
2
-
100
kHz
MCLK Pulse Width High
MCLK/LRCK = 512
10
-
1000
ns
MCLK Pulse Width Low
MCLK/LRCK = 512
10
-
1000
ns
MCLK Pulse Width High MCLK / LRCK = 384 or 192
21
-
1000
ns
MCLK Pulse Width Low
MCLK / LRCK = 384 or 192
21
-
1000
ns
MCLK Pulse Width High MCLK / LRCK = 256 or 128
31
-
1000
ns
MCLK Pulse Width Low
MCLK / LRCK = 256 or 128
31
-
1000
ns
External SCLK Mode
LRCK Duty Cycle (External SCLK only)
40
50
60
%
SCLK Pulse Width Low
t
sclkl
20
-
-
ns
SCLK Pulse Width High
t
sclkh
20
-
-
ns
SCLK Period
MCLK / LRCK = 512, 256 or 384
t
sclkw
-
-
ns
SCLK Period
MCLK / LRCK = 128 or 192
t
sclkw
-
-
ns
SCLK rising to LRCK edge delay
t
slrd
20
-
-
ns
SCLK rising to LRCK edge setup time
t
slrs
20
-
-
ns
SDATA valid to SCLK rising setup time
t
sdlrs
20
-
-
ns
SCLK rising to SDATA hold time
t
sdh
20
-
-
ns
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only)
(Note 9)
-
50
-
%
SCLK Period
(Note 10)
t
sclkw
-
-
ns
SCLK rising to LRCK edge
t
sclkr
-
-
s
SDATA valid to SCLK rising setup time
t
sdlrs
-
-
ns
SCLK rising to SDATA hold time
MCLK / LRCK = 512, 256 or 128
t
sdh
-
-
ns
SCLK rising to SDATA hold time
MCLK / LRCK = 384 or 192
t
sdh
-
-
ns
1
128
(
)
Fs
----------------------
1
64
( )
Fs
------------------
1
SCLK
----------------
tsclkw
2
------------------
1
512
(
)
Fs
----------------------
10
+
1
512
(
)
Fs
----------------------
15
+
1
384
(
)
Fs
----------------------
15
+
CS4341
DS298PP2
9
sclkh
t
slrs
t
slrd
t
sdlrs
t
sdh
t
sclkl
t
SDATA
SCLK
LRCK
Figure 1. External Serial Mode Input Timing
SDATA
*INTERNAL SCLK
LRCK
sclkw
t
sdlrs
t
sdh
t
sclkr
t
Figure 2. Internal Serial Mode Input Timing
*The SCLK pulses shown are internal to the CS4341.
SDATA
LRCK
MCLK
*INTERNAL SCLK
1
N
2
N
Figure 3. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4341.
N equals MCLK divided by SCLK
CS4341
10
DS298PP2
SWITCHING CHARACTERISTICS - CONTROL PORT
(T
A
= 25 C; VA = +5 V 5%; Inputs: logic 0 = AGND, logic 1 = VA, C
L
= 30 pF)
Notes: 11. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Parameter
Symbol
Min
Max
Unit
I
2
C
Compatible Mode
SCL Clock Frequency
f
scl
-
100
kHz
RST Rising Edge to Start
t
irs
500
-
ns
Bus Free Time Between Transmissions
t
buf
4.7
-
s
Start Condition Hold Time (prior to first clock pulse)
t
hdst
4.0
-
s
Clock Low time
t
low
4.7
-
s
Clock High Time
t
high
4.0
-
s
Setup Time for Repeated Start Condition
t
sust
4.7
-
s
SDA Hold Time from SCL Falling
(Note 11)
t
hdd
0
-
s
SDA Setup time to SCL Rising
t
sud
250
-
ns
Rise Time of Both SDA and SCL Lines
t
r
-
1
s
Fall Time of Both SDA and SCL Lines
t
f
-
300
ns
Setup Time for Stop Condition
t
susp
4.7
-
s
t
buf
t
hdst
t
hdst
t
low
t r
t f
t
hdd
t
high
t sud
t sust
t susp
Stop
Start
Start
Stop
Repeated
SDA
SCL
t
irs
RST
Figure 4. I
2
C Control Port Timing
CS4341
DS298PP2
11
SWITCHING CHARACTERISTICS - CONTROL PORT
(T
A
= 25 C; VA = +5 V 5%; Inputs: logic 0 = AGND, logic 1 = VA, C
L
= 30 pF)
Notes: 12. t
spi
only needed before first falling edge of CS after RST rising edge. t
spi
= 0 at all other times.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For F
SCK
< 1 MHz
Parameter
Symbol
Min
Max
Unit
SPI Mode
CCLK Clock Frequency
f
sclk
-
6
MHz
RST Rising Edge to CS Falling
t
srs
500
-
ns
CCLK Edge to CS Falling
(Note 12)
t
spi
500
-
ns
CS High Time Between Transmissions
t
csh
1.0
-
s
CS Falling to CCLK Edge
t
css
20
-
ns
CCLK Low Time
t
scl
66
-
ns
CCLK High Time
t
sch
66
-
ns
CDIN to CCLK Rising Setup Time
t
dsu
40
-
ns
CCLK Rising to DATA Hold Time
(Note 13)
t
dh
15
-
ns
Rise Time of CCLK and CDIN
(Note 14)
t
r2
-
100
ns
Fall Time of CCLK and CDIN
(Note 14)
t
f2
-
100
ns
t r2
t f2
t dsu t dh
t sch
t scl
CS
CCLK
CDIN
t css
t csh
t spi
t srs
RST
Figure 5. SPI Control Port Timing
CS4341
12
DS298PP2
2.
TYPICAL CONNECTION DIAGRAM
13
Audio
Data
Processor
External Clock
MCLK
AGND
AOUTB
CS4341
SDATA
LRCK
VA
AOUTA
3
4
5
14
0.1 F
+
1 F
12
+5 V to +3 V
3.3 F
3.3 F
10 k
C
C
560
560
+
+
- Controlled
Configuration
8
6
7
SCLK
1
2
SCL/CCLK
SDA/CDIN
AD0/CS
RST
MUTEC 16
OPTIONAL
MUTE
CIRCUIT
15
1 F
0.1 F
Audio
Output A
Audio
Output B
R L
R L
+
+
10 k
.1 F
1 F
9
10
11
REF_GND
FILT+
VQ
C =
4
Fs(R 560)
L
R
560
L +
Figure 6. Typical Connection Diagram
CS4341
DS298PP2
13
3.
REGISTER QUICK REFERENCE
** "default" ==> bit status after power-up-sequence or reset.
3.1
MCLK Control (address 00h)
MCLKDIV (MCLK Divide-by-2 Enable)
Default = `0'.
0 - Disabled
1 - Enabled
3.2
Mode Control (address 01h)
AMUTE (Auto-mute)
Default = `1'.
0 - Disabled
1 - Enabled
DIF2, DIF1 and DIF0 (Digital Interface Format)
Default = `0'.
0 - Format 0, I
2
S, up to 24-bit data, 64 x Fs Internal SCLK
1 - Format 1, I
2
S, up to 24-bit data, 32 x Fs Internal SCLK
2 - Format 2, Left Justified, up to 24-bit data
3 - Format 3, Right Justified, 24-bit Data
4 - Format 4, Right Justified, 20-bit Data
5 - Format 5, Right Justified, 16-bit Data
6 - Format 6, Right Justified, 18-bit Data
7 - Identical to Format 1
DEM 1, DEM 0 (De-Emphasis Mode)
Default = `0'.
0 - Disabled
1 - 44.1 kHz De-Emphasis
2 - 48 kHz De-Emphasis
3 - 32 kHz De-Emphasis
POR (Power on/off Quiescent Voltage ramp)
Default = `1'.
0 - Disabled
1 - Enabled
PDN (Power-Down)
Default ='1'.
0 - Disabled
1 - Enabled
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MCLKDIV
Reserved
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
AMUTE
DIF2
DIF1
DIF0
DEM1
DEM0
POR
PDN
1
0
0
0
0
0
1
1
CS4341
14
DS298PP2
3.3
Volume and Mixing Control (address 02h)
A = B (Channel A Volume = Channel B Volume)
Default = `0'.
0 - AOUTA volume is determined by register 03h and AOUTB volume is determined by register
04h.
1 - AOUTA and AOUTB volumes are determined by register 03h and register 04h is ignored.
Soft & Zero Cross (Soft control and zero cross detection control)
Default = `10'.
Soft
Zero Cross
Mode
0
0
Changes take effect immediately
0
1
Changes take effect on zero crossings
1
0
Changes take effect with a soft ramp (default)
1
1
Changes take effect in 1/8 dB steps on each zero crossing
ATAPI 0-4 (Channel mixing and muting)
(refer to Table 9)
Default = `01001', (Stereo)
AOUTA = Left Channel
AOUTB = Right Channel
3.4
Channel A Volume Control (address 03h)
3.5
Channel B Volume Control (address 04h)
MUTE
Default = `0'
0 - Disabled
1 - Enabled
Volume
Default = `0'
(Refer to Table 11)
7
6
5
4
3
2
1
0
A = B
Soft
Zero Cross
ATAPI4
ATAPI3
ATAPI2
ATAPI1
ATAPI0
0
1
0
0
1
0
0
1
7
6
5
4
3
2
1
0
MUTE
VOL6
VOL5
VOL4
VOL3
VOL2
VOL1
VOL0
0
0
0
0
0
0
0
0
CS4341
DS298PP2
15
4.
REGISTER BIT DESCRIPTION
4.1
MASTER CLOCK DIVIDE ENABLE
MCLK Control Register (address 00h)
Access:
R/W in I
2
C and write only in SPI.
Default:
0 - Disabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2.
Note: This feature is present on revision C and newer devices. For backward compatibility with pre-
vious revision devices, this bit defaults to zero.
4.2
AUTO-MUTE
Mode Control Register (address 01h)
Access:
R/W in I
2
C and write only in SPI.
Default:
1 - Enabled
Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio
samples of static 0 or -1. A single sample of non-zero data will release the mute. Detection and mut-
ing is done independently for each channel. The quiescent voltage on the output will be retained and
the Mute Control pin will go active during the mute period. The muting function is effected, similiar to
volume control changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register.
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MCLKDIV
Reserved
MCLKDIV
MODE
0
Disabled
1
Enabled
Table 1. Master Clock Divide Enable
7
6
5
4
3
2
1
0
AMUTE
DIF2
DIF1
DIF0
DEM1
DEM0
POR
PDN
AMUTE
MODE
0
Disabled
1
Enabled
Table 2. Auto-Mute Enable
CS4341
16
DS298PP2
4.3
DIGITAL INTERFACE FORMAT
Mode Control Register (address 01h)
Access:
R/W in I
2
C and write only in SPI.
Default:
0 - Format 0 (I
2
S, up to 24-bit data, 64 x Fs Internal SCLK)
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the
Digital Interface Format and the options are detailed in Figures 20-26.
4.4
DE-EMPHASIS CONTROL
Mode Control Register (address 01h)
Access:
R/W in I
2
C and write only in SPI.
Default:
0 - Disabled
Function:
Implementation of the standard 15
s/50
s digital de-emphasis filter response, Figure 27, requires re-
configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample
rates. NOTE: De-emphasis is not available in High-Rate Mode.
7
6
5
4
3
2
1
0
AMUTE
DIF2
DIF1
DIF0
DEM1
DEM0
POR
PDN
DIF2
DIF1
DIF0
DESCRIPTION
FORMAT
FIGURE
0
0
0
I
2
S, up to 24-bit data, 64 x Fs Internal SCLK
0
20
0
0
1
I
2
S, up to 24-bit data, 32 x Fs Internal SCLK
1
21
0
1
0
Left Justified, up to 24-bit data
2
22
0
1
1
Right Justified, 24-bit Data
3
23
1
0
0
Right Justified, 20-bit Data
4
24
1
0
1
Right Justified, 16-bit Data
5
25
1
1
0
Right Justified, 18-bit Data
6
26
1
1
1
Identical to Format 1
7
20
Table 3. Digital Interface Formats
7
6
5
4
3
2
1
0
AMUTE
DIF2
DIF1
DIF0
DEM1
DEM0
POR
PDN
DEM1
DEMO
DESCRIPTION
0
0
Disabled
0
1
44.1kHz
1
0
48kHz
1
1
32kHz
Table 4. De-emphasis Filter Configurations
CS4341
DS298PP2
17
4.5
POWER ON/OFF QUIESCENT VOLTAGE RAMP
Mode Control Register (address 01h)
Access:
R/W in I
2
C and write only in SPI.
Default:
1 - Enabled
Function:
The power On/Off Quiescent Voltage Ramp allows the quiescent voltage to slowly ramp to and from
0 volts to the quiescent voltage during power-on or power-off. Please refer to the applications section
for details of implementing this feature.
4.6
POWER DOWN
Mode Control Register (address 01h)
Access:
R/W in I
2
C and write only in SPI.
Default:
1 - Enabled
Function:
The device will enter a low-power state whenever this function is activated. The power-down bit de-
faults to `enabled' on power-up and must be disabled before normal operation will begin. The contents
of the control registers are retained in this mode.
7
6
5
4
3
2
1
0
AMUTE
DIF2
DIF1
DIF0
DEM1
DEM0
POR
PDN
POR
MODE
0
Disabled
1
Enabled
Table 5. Power On/Off Ramp Enable
7
6
5
4
3
2
1
0
AMUTE
DIF2
DIF1
DIF0
DEM1
DEM0
POR
PDN
PDN
MODE
0
Disabled
1
Enabled
Table 6. Power Down Enable
CS4341
18
DS298PP2
4.7
CHANNEL A VOLUME = CHANNEL B VOLUME
Volume and Mixing Control Register (address 02h)
Access:
R/W in I
2
C and write only in SPI.
Default:
0 - Disabled
Function:
The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Vol-
ume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are de-
termined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function
is enabled.
4.8
SOFT RAMP OR ZERO CROSS ENABLE
Volume and Mixing Control Register (address 02h)
Access:
R/W in I
2
C and write only in SPI.
Default:
10 - Soft Ramp enabled.
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8 left/right clock
periods.
Zero Cross Enable
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is indepently monitored
and implemented for each channel.
7
6
5
4
3
2
1
0
A = B
Soft
Zero Cross
ATAPI4
ATAPI3
ATAPI2
ATAPI1
ATAPI0
A = B
MODE
0
Disabled
1
Enabled
Table 7. A=B Volume Control Enable
7
6
5
4
3
2
1
0
A = B
Soft
Zero Cross
ATAPI4
ATAPI3
ATAPI2
ATAPI1
ATAPI0
CS4341
DS298PP2
19
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes
or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level
change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
indepently monitored and implemented for each channel.
4.9
ATAPI CHANNEL MIXING AND MUTING
Volume and Mixing Control Register (address 02h)
Access:
R/W in I
2
C and write only in SPI.
Default:
01001 - AOUTA=aL, AOUTB=bR (Stereo)
Function:
The CS4341 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to
Table 9 and Figure 28 for additional information.
SOFT
ZERO
Mode
0
0
Changes to affect immediately
0
1
Zero Cross enabled
1
0
Soft Ramp enabled
1
1
Soft Ramp and Zero Cross enabled
Table 8. Soft Ramp and Zero Cross Enable
7
6
5
4
3
2
1
0
A = B
Soft
Zero Cross
ATAPI4
ATAPI3
ATAPI2
ATAPI1
ATAPI0
ATAPI4
ATAPI3
ATAPI2
ATAPI1
ATAPI0
AOUTA
AOUTB
0
0
0
0
0
MUTE
MUTE
0
0
0
0
1
MUTE
bR
0
0
0
1
0
MUTE
bL
0
0
0
1
1
MUTE
b[(L+R)/2]
0
0
1
0
0
aR
MUTE
0
0
1
0
1
aR
bR
0
0
1
1
0
aR
bL
0
0
1
1
1
aR
b[(L+R)/2]
0
1
0
0
0
aL
MUTE
0
1
0
0
1
aL
bR
0
1
0
1
0
aL
bL
0
1
0
1
1
aL
b[(L+R)/2]
0
1
1
0
0
a[(L+R)/2]
MUTE
0
1
1
0
1
a[(L+R)/2]
bR
0
1
1
1
0
a[(L+R)/2]
bL
0
1
1
1
1
a[(L+R)/2]
b[(L+R)/2]
1
0
0
0
0
MUTE
MUTE
1
0
0
0
1
MUTE
bR
Table 9. ATAPI Decode
CS4341
20
DS298PP2
4.10
MUTE
Channel A Volume Control Register (address 03h)
Channel B Volume Control Register (address 04h)
Access:
R/W in I
2
C and write only in SPI.
Default:
0 - Disabled
Function:
The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output
will be retained. The muting function is effected, similiar to attenuation changes, by the Soft and Zero
Cross bits in the Volume and Mixing Control register. The MUTEC will go active during the mute pe-
riod if the Mute function is enabled for both channels.
1
0
0
1
0
MUTE
bL
1
0
0
1
1
MUTE
[(aL+bR)/2]
1
0
1
0
0
aR
MUTE
1
0
1
0
1
aR
bR
1
0
1
1
0
aR
bL
1
0
1
1
1
aR
[(bL+aR)/2]
1
1
0
0
0
aL
MUTE
1
1
0
0
1
aL
bR
1
1
0
1
0
aL
bL
1
1
0
1
1
aL
[(aL+bR)/2]
1
1
1
0
0
[(aL+bR)/2]
MUTE
1
1
1
0
1
[(aL+bR)/2]
bR
1
1
1
1
0
[(bL+aR)/2]
bL
1
1
1
1
1
[(aL+bR)/2]
[(aL+bR)/2]
7
6
5
4
3
2
1
0
MUTE
VOL6
VOL5
VOL4
VOL3
VOL2
VOL1
VOL0
MUTE
MODE
0
Disabled
1
Enabled
Table 10. Mute Enable
ATAPI4
ATAPI3
ATAPI2
ATAPI1
ATAPI0
AOUTA
AOUTB
Table 9. ATAPI Decode (Continued)
CS4341
DS298PP2
21
4.11
VOLUME CONTROL
Channel A Volume Control Register (address 03h)
Channel B Volume Control Register (address 04h)
Access:
R/W in I
2
C and write only in SPI.
Default:
0 - 0 dB (No attenuation)
Function:
The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -90 dB.
Volume settings are decoded as shown in Table 11. The volume changes are implemented as dic-
tated by the Soft and Zero Cross bits in the Volume and Mixing Control register. All volume settings
less than - 94 dB are equivalent to enabling the Mute bit.
7
6
5
4
3
2
1
0
MUTE
VOL6
VOL5
VOL4
VOL3
VOL2
VOL1
VOL0
Binary Code
Decimal Value
Volume Setting
0000000
0
0 dB
0010100
20
-20 dB
0101000
40
-40 dB
0111100
60
-60 dB
1011010
90
-90 dB
Table 11. Digital Volume Settings
CS4341
22
DS298PP2
5.
PIN DESCRIPTION
Analog Power - VA
Pin 14, Input
Function:
Analog power supply. Typically 3 to 5VDC.
Analog Ground - AGND
Pin 13, Input
Function:
Analog ground reference.
Analog Output - AOUTA and AOUTB
Pins 12 and 15, Output
Function:
The full scale analog output level is specified in the Analog Characteristics specifications table.
Reference Ground - REF_GND
Pin 11, Input
Function:
Ground reference for the internal sampling circuits. Must be connected to analog ground.
Positive Voltage Reference - FILT+
Pin 9, Output
Function:
Positive reference for internal sampling circuits. External capacitors are required from FILT+ to analog
ground, as shown in Figure 6. The recommended values will typically provide 60 dB of PSRR at 1 kHz
and 40 dB of PSRR at 60 Hz. FILT+ is not intended to supply external current. FILT+ has a typical source
impedence of 250 k
and any current drawn from this pin will alter device performance.
Quiescent Voltage - VQ
Pin 10, Output
Function:
Filter connection for internal quiescent reference voltage, typically 50% of VA. Capacitors must be con-
nected from V
Q
to analog ground, as shown in Figure 6. V
Q
is not intended to supply external current. V
Q
has a typical source impedence of 250 k
and any current drawn from this pin will alter device perfor-
mance.
15
2
14
3
13
4
16
1
11
6
10
7
9
8
12
5
Reset
RST
MUTEC
Mute Control
Serial Data
SDATA
AOUTA
Analog Output A
Serial Clock
SCLK
VA
Analog Power
Left/Right Clock
LRCK
AGND
Analog Ground
Master Clock
MCLK
AOUTB
Analog Output B
SCL/CCLK
SCL/CCLK
REF_GND Reference Ground
SDA/CDIN
SDA/CDIN
VQ
Quiescent Voltage
AD0/CS
AD0/CS
FILT+
Positive Voltage Reference
CS4341
DS298PP2
23
Master Clock - MCLK
Pin 5, Input
Function:
The master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in Base
Rate Mode (BRM) and 128x, 192x, 256x or 384x the input sample rate in High Rate Mode (HRM). Note
that some multiplication factors require setting the MCLKDIV bit in the MCLK Control Register. Table 12
illustrates several standard audio sample rates and the required master clock frequencies.
Left/Right Clock - LRCK
Pin 4, Input
Function:
The Left/Right clock determines which channel is currently being input on the serial audio data input, SDA-
TA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in Left/Right
sample pairs will be simultaneously output from the digital-to-analog converter whereas Right/Left pairs
will exhibit a one sample period difference. The required relationship between the Left/Right clock, serial
clock and serial data is defined by the Mode Control Byte and the options are detailed in Figures 20-26.
Serial Audio Data - SDATA
Pin 2, Input
Function:
Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial
clock and the channel is determined by the Left/Right clock. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are de-
tailed in Figures 20-26.
Sample Rate
(kHz)
MCLK (MHz)
HRM
BRM
128x
192x
256x*
384x*
256x
384x
512x
768x*
1024x*
32
4.0960
6.1440
8.1920
12.2880
8.1920
12.2880
16.3840
24.5760
32.7680
44.1
5.6448
8.4672
11.2896
16.9344
11.2896
16.9344
22.5792
32.7680
45.1584
48
6.1440
9.2160
12.2880
18.4320
12.2880
18.4320
24.5760
36.8640
49.1520
64
8.1920
12.2880
16.3840
24.5760
-
-
-
-
-
88.2
11.2896
16.9344
22.5792
33.8688
-
-
-
-
-
96
12.2880
18.4320
24.5760
36.8640
-
-
-
-
-
* Requires MCLKDIV bit = 1 in MCLK Control Register (address 00h)
Table 12. Common Clock Frequencies
CS4341
24
DS298PP2
Serial Clock - SCLK
Pin 3, Input
Function:
Clocks the individual bits of the serial data into the SDATA pin. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are de-
tailed in Figures 20-26.
The CS4341 supports both internal and external serial clock generation modes. The Internal Serial Clock
Mode eliminates possible clock interference from an external SCLK. Use of the Internal Serial Clock Mode
is always preferred.
Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with the master
clock and left/right clock. The SCLK/LRCK frequency ratio is either 32, 48, or 64 depending upon data
format, as shown in Figures 20-26. Operation in this mode is identical to operation with an external serial
clock synchronized with LRCK.
External Serial Clock Mode
The CS4341 will enter the External Serial Clock Mode whenever 16 low to high transitions are detected
on the SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode
if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK.
Reset - RST
Pin 1, Input
Function:
The device enters a low power mode and all internal registers are reset to the default settings, including
the control port, when low. When high, the control port becomes operational and the PDN bit must be
cleared before normal operation will occur. The control port can not be accessed when reset is low.
Serial Control Interface Clock - SCL/CCLK
Pin 6, Input
Function:
Clocks the serial control data into or from SDA/CDIN.
Serial Control Data I/O - SDA/CDIN
Pin 7, Input/Output
Function:
In I
2
C mode, SDA is a data I/O line. CDIN is the input data line for the control port interface in SPI mode.
Address Bit / Chip Select - AD0/CS
Pin 8, Input
Function:
In I
2
C mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The
device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device
has entered the SPI mode, it will remain until either the part is reset or undergoes a power-down cycle.
Mute Control - MUTEC
Pin 16, Output
Function:
The Mute Control pin goes high during power-up initialization, reset, muting, master clock to left/right clock
frequency ratio is incorrect or power-down. This pin is intended to be used as a control for an external mute
circuit to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not
mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops.
CS4341
DS298PP2
25
6. APPLICATIONS
6.1
Grounding and Power Supply
Decoupling
As with any high resolution converter, the CS4341
requires careful attention to power supply and
grounding arrangements to optimize performance.
Figure 6 shows the recommended power arrange-
ment with VA connected to a clean supply. Decou-
pling capacitors should be located as close to the
device package as possible.
6.2
Oversampling Modes
The CS4341 operates in one of two oversampling
modes based on the input sample rate and the state
of the MCLKDIV bit in the MCLK Control Regis-
ter. Base Rate Mode (BRM) supports input sample
rates up to 50 kHz while High Rate Mode (HRM)
supports input sample rates up to 100 kHz. When
the MCLKDIV bit is cleared, the devices operate in
BRM when MCLK/LRCK is 256, 384 or 512 and
in HRM when MCLK/LRCK is 128 or 192. When
the MCLKDIV bit is set, the devices operate in
BRM when MCLK/LRCK is 512, 768 or 1024 and
in HRM when MCLK/LRCK is 256 or 384.
6.3
Recommended Power-up Sequence
1. Hold RST low until the power supply, master,
and left/right clocks are stable. In this state, the
control port is reset to its default settings and V
Q
will remain low.
2. Bring RST high. The device will remain in a low
power state with V
Q
low and the control port acce-
sable. The desired register settings can be loaded
while keeping the PDN bit set to 1.
3. Set the PDN bit to 0 which will initiate the pow-
er-up sequence, which requires approximately 50
s when the POR bit is set to 0. If the POR bit is
set to 1, see Section 6.4 for total power-up timing.
6.4
Use of the Power ON/OFF Quiescent
Voltage Ramp
The CS4341 uses a novel technique to minimize
the effects of output transients during power-up
and power-down. This technique, when used with
external DC-blocking capacitors in series with the
audio outputs, minimizes the audio transients com-
monly produced by single-ended single-supply
converters.
When the device is initially powered-up, the audio
outputs, AOUTA and AOUTB, are clamped to
AGND. Following a delay of approximately 1000
sample periods, each output begins to ramp toward
the quiescent voltage. Approximately 10,000
left/right clock cycles later, the outputs reach VQ
and audio output begins. This gradual voltage
ramping allows time for the external DC-blocking
capacitor to charge to the quiescent voltage, mini-
mizing the power-up transient.
To prevent transients at power-down, the device
must first enter its power-down state. When this oc-
curs, audio output ceases and the internal output
buffers are disconnected from AOUTA and
AOUTB. In their place, a soft-start current sink is
substituted which allows the DC-blocking capaci-
tors to slowly discharge. Once this charge is dissi-
pated, the power to the device may be turned off
and the system is ready for the next power-on.
To prevent an audio transient at the next power-on,
it is necessary to ensure that the DC-blocking ca-
pacitors have fully discharged before turning off
the power or exiting the power-down state. If not, a
transient will occur when the audio outputs are ini-
tially clamped to AGND. The time that the device
must remain in the power-down state is related to
the value of the DC-blocking capacitance. For ex-
ample, with a 3.3 F capacitor, the minimum pow-
er-down time will be approximately 0.4 seconds.
Use of the Mute Control function is recommended
for designs requiring the absolute minimum in ex-
traneous clicks and pops. Also, use of the Mute
CS4341
26
DS298PP2
Control function can enable the system designer to
achieve idle channel noise/signal-to-noise ratios
which are only limited by the external mute circuit.
7. CONTROL PORT INTERFACE
The control port is used to load all the internal set-
tings of the CS4341. The operation of the control
port may be completely asynchronous to the audio
sample rate. However, to avoid potential interfer-
ence problems, the control port pins should remain
static if no operation is required. *
The control port has 2 modes: SPI and I
2
C compat-
ible, with the CS4341 operating as a slave device in
both modes. If I
2
C operation is desired, AD0/CS
should be tied to VA or AGND. If the CS4341 ever
detects a high to low transition on AD0/CS after
power-up, SPI mode will be selected. The control
port registers are write-only in SPI mode.
7.1
SPI Mode
In SPI mode, CS is the CS4341 chip select signal,
CCLK is the control port bit clock, CDIN is the in-
put data line from the microcontroller and the chip
address is 0010000. All signals are inputs and data
is clocked in on the rising edge of CCLK.
Figure 7 shows the operation of the control port in
SPI mode. To write to a register, bring CS low. The
first 7 bits on CDIN form the chip address, and
must be 0010000. The eighth bit is a read/write in-
dicator (R/W), which must be low to write. The
next 8 bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next 8 bits are the data
which will be placed into the register designated by
the MAP.
The CS4341 has MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is 0, then the MAP will stay constant for suc-
cessive writes. If INCR is set to 1, then MAP will
auto increment after each byte is written, allowing
block reads or writes of successive registers.
7.2
I
2
C Compatible Mode
In I
2
C compatible mode, SDA is a bi-directional
data line. Data is clocked into and out of the part by
the clock, SCL, with the clock to data relationship
as shown in Figure 8. There is no CS pin. Pin AD0
forms the partial chip address and should be tied to
VA or AGND as required. The upper 6 bits of the
7-bit address field must be 001000. To communi-
cate with the CS4341 the LSB of the chip address
field, which is the first byte sent to the CS4341,
should match the setting of the AD0 pin. The eighth
bit of the address byte is the R/W bit (high for a
read, low for a write). If the operation is a write, the
next byte is the Memory Address Pointer, MAP,
which selects the register to be read or written. The
MAP is then followed by the data to be written. If
the operation is a read, then the contents of the reg-
ister pointed to by the MAP will be output after the
chip address.
The CS4341 has MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is 0, then the MAP will stay constant for suc-
cessive writes. If INCR is set to 1, then MAP will
auto increment after each byte is written, allowing
block reads or writes of successive registers.
For more information on I
2
C, please see "The I
2
C-
Bus Specification: Version 2.0", listed in the Ref-
erences section.
* The MCLK is required for both control port inter-
faces.
CS4341
DS298PP2
27
Memory Address Pointer (MAP)
INCR (Auto MAP Increment Enable)
Default = `0'.
0 - Disabled
1 - Enabled
MAP0-2 (Memory Address Pointer)
Default = `000'.
7
6
5
4
3
2
1
0
INCR
Reserved
Reserved
Reserved
Reserved
MAP2
MAP1
MAP0
0
0
0
0
0
0
0
0
MAP
MSB
LSB
DATA
byte 1
byte n
R/W
MAP = Memory Address Pointer
ADDRESS
CHIP
CDIN
CCLK
CS
0010000
Figure 7. SPI Mode Control Port Formating
SDA
SCL
001000
ADDR
AD0
R/W
Start
ACK
DATA
1-8
ACK
DATA
1-8
ACK
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Note 1
Figure 8. I
2
C Mode Control Port Formating
CS4341
28
DS298PP2
Figure 9. Base-Rate Stopband Rejection
Figure 10. Base-Rate Transition Band
Figure 11. Base-Rate Transition Band (Detail)
Figure 12. Base-Rate Passband Ripple
Figure 13. High-Rate Stopband Rejection
Figure 14. High-Rate Transition Band
CS4341
DS298PP2
29
Figure 15. High-Rate Transition Band (Detail)
Figure 16. High-Rate Passband Ripple
AOUTx
AGND
3.3 F
V
out
R
L
C
L
+
Figure 17. Output Test Load
100
50
75
25
2.5
5
10
15
Safe Operating
Region
C
a
p
a
c
i
t
i
ve
Lo
ad
--
C
(
p
F
)
L
Resistive Load -- R (k
)
L
125
3
20
Figure 18. Maximum Loading
75
50
30
Po
w
e
r
(
m
W
)
Sample Rate (kHz)
B
R
M
HR
M
70
65
60
55
40
50
60
70
80
90
100
Figure 19. Power vs. Sample Rate (VA = 5V)
CS4341
30
DS298PP2
LRCK
SCLK
Left Channel
Right Channel
SDATA
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4
Internal SCLK Mode
External SCLK Mode
I
2
S, Up to 24-Bit data and INT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128I
2
S, Up to 24-Bit data
and INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
I
2
S, up to 24-Bit DataData Valid on Rising Edge of
SCLK
Figure 20. CS4341 Format 0 (I
2
S)
LRCK
SCLK
Left Channel
Right Channel
SDATA
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4
Internal SCLK Mode
External SCLK Mode
I
2
S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128I
2
S, Up to 24-Bit data
and INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
I
2
S, up to 24-Bit DataData Valid on Rising Edge of
SCLK
Figure 21. CS4341 Format 1 (I
2
S)
LRCK
SCLK
Left Channel
Right Channel
SDATA
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4
Internal SCLK Mode
External SCLK Mode
Left Justified, up to 24-Bit DataINT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Left Justified, up to 24-Bit DataData Valid on Rising
Edge of SCLK
Figure 22. CS4341 Format 2
CS4341
DS298PP2
31
LRCK
SCLK
Left Channel
SDATA
6
5
4
3
2
1
0
7
23 22 21 20 19 18
6
5
4
3
2
1
0
7
23 22 21 20 19 18
32 clocks
0
Right Channel
Internal SCLK Mode
External SCLK Mode
Right Justified, 24-Bit DataINT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Right Justified, 24-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 48 Cycles per LRCK
Period
Figure 23. CS4341 Format 3
LRCK
SCLK
Left Channel
Right Channel
SDATA
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
1
0
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
17 16
17 16
32 clocks
19 18
19 18
Internal SCLK Mode
External SCLK Mode
Right Justified, 20-Bit DataINT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Right Justified, 20-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 40 Cycles per LRCK
Period
Figure 24. CS4341 Format 4
LRCK
SCLK
Left Channel
Right Channel
SDATA
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
32 clocks
Internal SCLK Mode
External SCLK Mode
Right Justified, 16-Bit DataINT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Right Justified, 16-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 32 Cycles per LRCK
Period
Figure 25. CS4341 Format 5
CS4341
32
DS298PP2
LRCK
SCLK
Left Channel
Right Channel
SDATA
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
1
0
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
17 16
17 16
32 clocks
Internal SCLK Mode
External SCLK Mode
Right Justified, 18-Bit DataINT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Right Justified, 18-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 36 Cycles per LRCK
Period
Figure 26. CS4341 Format 6
Gain
dB
-10dB
0dB
Frequency
T2 = 15 s
T1=50 s
F1
F2
3.183 kHz
10.61 kHz
Figure 27. De-Emphasis Curve
A Channel
Volume
Control
AoutA
AoutB
Left Channel
Audio Data
Right Channel
Audio Data
B Channel
Volume
Control
MUTE
MUTE
Figure 28. ATAPI Block Diagram
CS4341
DS298PP2
33
8.
PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
affect the measurement. This measurement technique has been accepted by the Audio Engineering So-
ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/C.
9.
REFERENCES
1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris.
Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2) CDB4341 Evaluation Board Datasheet
3) "The I
2
C Bus Specification: Version 2.0" Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
CS4341
34
DS298PP2
10. PACKAGE DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
A 0.053
0.069
1.35
1.75
A1
0.004
0.010
0.10
0.25
B
0.013
0.020
0.33
0.51
C
0.007
0.010
0.19
0.25
D
0.386
0.394
9.80
10.00
E
0.150
0.157
3.80
4.00
e
0.040
0.060
1.02
1.52
H
0.228
0.244
5.80
6.20
L
0.016
0.050
0.40
1.27
0
8
0
8
JEDEC # : MS-012
e
16L SOIC (150 MIL BODY) PACKAGE DRAWING
D
H
E
b
A1
A
c
L
SEATING
PLANE
1
Notes
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