Copyright

http://www.cirrus.com

Multi-Bit A/D for Class-D Real-Time PSR Feedback

Features

Advanced Multi-bit Delta-Sigma Architecture
Real-time Feedback of Power Supply

Conditions (AC and DC)
Filterless Digital Output Resulting in Very Low

Signal Delay
135 mW Power Consumption
Supports Logic Levels Between 3.3 V and

5.0 V
Differential Analog Architecture
Modulator Overflow Detection
Interfaces Directly to the CS44800/CS44600

Class-D PWM Modulator
Multi-bit Conversion at up to 7.5 MHz
Delivers Modulated Data Over 2-Wire Interface

General Description

The CS4461 is a complete analog-to-digital converter
for class-D real-time power supply rejection (PSR) feed-
back. It performs sampling and analog-to-digital
conversion, generating digital data for input to a
class-D modulator with real-time PSR feedback
capabilities.

The CS4461 uses a 5th-order, multi-bit delta-sigma
modulator followed by output data formatting. The ADC
uses a differential architecture which provides excellent
noise rejection.

The CS4461 feeds back the AC and DC voltage compo-
nents and is ideal for class-D audio systems requiring
high power supply rejection.

The CS4461 is available in a 24-pin TSSOP package in
both Commercial (-10° to +70° C) and Automotive
grade (-40° to +85° C). The CDB44800 Customer Dem-
onstration board is also available for device evaluation
and implementation suggestions. Please see

"Ordering

Information" on page 11

for complete details.

Voltage Reference

REFGND

AIN-

AIN+

FILT+

PSR_DATA

PSR_SYNC

5.0 V

(VA)

GND

PSR_MCLK

S/H

LP Filter

DAC

Output Data

Formatting

3.3 V to 5.0 V

(VDP)

PSR_EN

OVERFLOW

PSR_RESET

SEPTEMBER '05

DS650F1

CS4461

DS650F1

CS4461

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 3
2. PIN DESCRIPTIONS ............................................................................................................................. 6
3. TYPICAL CONNECTION DIAGRAM .................................................................................................... 7
4. APPLICATIONS .................................................................................................................................... 8

4.1 Digital Connections ......................................................................................................................... 8
4.2 Analog Connections ....................................................................................................................... 8
4.3 Power-Up Sequence ...................................................................................................................... 9
4.4 Overflow Detection ......................................................................................................................... 9
4.5 Grounding and Power Supply Decoupling ...................................................................................... 9

5. PACKAGE DIMENSIONS ................................................................................................................. 10
6. ORDERING INFORMATION ............................................................................................................... 11
7. REVISION HISTORY ........................................................................................................................... 11

LIST OF FIGURES

Figure 1. Typical Connection Diagram......................................................................................................... 7
Figure 2. CS4461 Recommended Analog Input Buffer................................................................................ 8

DS650F1

CS4461

1. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at typical supply voltages
and T

= 25

°C.)

SPECIFIED OPERATING CONDITIONS

(GND = 0 V, all voltages with respect to 0 V.)

ABSOLUTE MAXIMUM RATINGS

(GND = 0 V, All voltages with respect to ground.)

(Note 1)

Notes:

1. Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause

SCR latch-up.

3. The maximum over/under voltage is limited by the input current.

Parameter

Symbol Min Typ

Max

Unit

DC Power Supplies:

Positive Analog

Positive Digital

VDP

4.75

3.1

5.0
3.3

5.25
5.25

V
V

Ambient Operating Temperature

Commercial (-CZZ)

Automotive (-DZZ)

-10
-40

-
-

+70
+85

°C
°C

Parameter

Symbol

Min

Max

Units

DC Power Supplies:

Analog

Digital

VDP

-0.3
-0.3

+6.0
+6.0

V
V

Input Current

(Note 2)

±10

Analog Input Voltage

(Note 3)

GND - 0.7

VA + 0.7

Digital Input Voltage

(Note 3)

IND

-0.7

VDP + 0.7

Ambient Operating Temperature (Power Applied)

-50

+95

°C

Storage Temperature

stg

-65

+150

°C

DS650F1

CS4461

DC ELECTRICAL CHARACTERISTICS

(GND = 0 V, all voltages with respect to ground. PSR_MCLK=12.288 MHz)

Notes:

4. Power Down Mode is defined as PSR_RESET = Low with all clocks and data lines held static.

5. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection

Diagram.

DIGITAL CHARACTERISTICS

THERMAL CHARACTERISTICS

Parameter

Symbol

Min

Typ

Max

Unit

Power Supply Current

(Normal Operation)

VDP = 5.0 V
VDP = 3.3 V

-
-
-

17.5

14.5

21
26
17

mA
mA
mA

Power Supply Current

(Power-Down Mode)

(Note 4)

VDP = 5.0 V

-
-

2
2

-
-

mA
mA

Power Consumption
(Normal Operation)

VDP = 5.0 V
VDP = 3.3 V

(Power-Down Mode)

VDP = 5.0 V

-
-
-

198
135

235
161

mW
mW
mW
mW

ADC Power Supply Rejection Ratio (1 kHz)

(Note 5)

PSRR

Nominal Voltage

Output Impedance

Maximum allowable DC current source/sink

-
-
-

2.5

0.01

-
-
-

FILT+ Nominal Voltage

Output Impedance

Maximum allowable DC current source/sink

-
-
-

0.01

-
-
-

Parameter

Symbol

Min

Typ

Max

Units

High-Level Input Voltage

(% of VDP)

70%

Low-Level Input Voltage

(% of VDP)

30%

High-Level Output Voltage at I

= 100

µA

(% of VDP)

70%

Low-Level Output Voltage at I

= 100

µA

(% of VDP)

15%

OVERFLOW Current Sink

OVERFLOW

4.0

Input Leakage Current

±10

µA

Parameter

Symbol

Min

Typ

Max

Unit

Allowable Junction Temperature

135

°C

Junction to Ambient Thermal Impedance

°C/W

DS650F1

CS4461

PIN DESCRIPTIONS

Pin Name

Pin Descriprion

VDP

6
8

13
14

Digital Logic Power (Input) Digital core and input/output power supply. Nominally +3.3 V or +5.0 V.
Supply decoupling should placed as close as possible to pin 6.

Analog Power (Input) - Analog power supply. Nominally +5.0 V.

GND

2
7

10
12
18
20
21

Ground (Input) - Ground reference for both analog and digital.

PSR_RESET

Reset (Input) - When PSR_RESET is low, the CS4461 enters a low power mode and all internal states
are reset. On initial power up, PSR_RESET must be held low until the power supply is stable, and all
input clocks are stable in frequency and phase.

Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.

REFGND

Reference Ground (Input) - Ground reference for the internal sampling circuits.

FILT+

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuit.

AIN+
AIN-

16
17

Differential PSR Analog Input (Input) - Signals are presented differentially to the delta-sigma modula-
tor via the AIN+/- pins.

PSR_MCLK

Master Clock (Input) - Clock source for the delta-sigma modulator and output data.

PSR_SYNC

Synchronization Data Output (Output) - Used to synchronize the serial data in the PWM modulator.

PSR_DATA

PSR Serial Data Output (Output) - Power supply modulated and formatted serial data.

PSR_EN

PSR Enable (Input) - A high to low transition on this pin will enable the PSR feedback circuit.

OVERFLOW

Overflow (Output, open drain) - Indicates a modulator overflow condition.

TEST

Test (Output) - This pin may toggle during normal operation and should be pulled low through a 47 k

resistor to GND in order to minimize noise.

PSR_RESET

FILT+

GND

REFGND

PSR_SYNC

PSR_DATA

GND

PSR_MCLK

GND

VDP

GND

VDP

AIN-

TEST

AIN+

GND

OVERFLOW

PSR_EN

VDP

GND

VDP

1
2
3
4
5
6
7
8

9
10
11
12

Top-Down View

24-pin TSSOP Package

DS650F1

CS4461

4. APPLICATIONS

4.1

Digital Connections

PSR_MCLK provides the system clock for the CS4461. PSR_SYNC and PSR_DATA provide the output of
the modulator to the class-D modulator with feedback capabilities. Series damping resistors should be used
on PSR_MCLK, PSR_SYNC, and PSR_DATA to minimize noise. These should be placed as close as pos-
sible to their signal source. The pin labeled TEST should also be pulled low to GND through a 47 k

resistor

to minimize noise coupling into the ADC modulator.

4.2

Analog Connections

The analog modulator samples the input at PSR_MCLK/4 (6.144 MHz with PSR_MCLK=24.576 MHz).

Figure 2

shows the suggested analog input filter. This filter topology will correctly buffer the power supply's

AC and DC components for PSR processing by the class-D modulator. The use of capacitors which have a
large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade sig-
nal linearity. C0G dielectrics should be used wherever possible. R1 and R2 should be used to scale VP
(class-D amplifier high voltage power supply) to less than the CS4461 maximum AIN+/AIN- input voltage
(3.9 V).

The following equation can be used to scale R1 and R2:

2 * (VP * (1 + %

VP_Ripple

)) * (R2 / (R1 + R2)) < 3.9 V

Example (VP = 40 V, %

VP_Ripple

= 4%):

2 * (40 * (1 + 0.04)) * (1.96 k

/ (40.2 k + 1.96 k) = 3.87 V

CS4461

AIN+

AIN-

2200 pF

C0G

90.9

120 pF

2 k

+5.0 V

649

90.9

+5.0 V

120 pF

649

Figure 2. CS4461 Recommended Analog Input Buffer

DS650F1

CS4461

4.3

Power-Up Sequence

Reliable power-up can be accomplished by keeping the device in reset until the power supplies and clocks
are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the min-
imum specified operating voltages to prevent power glitch related issues.

The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a de-
lay between the release of reset and the generation of valid output, due to the finite output impedance of
FILT+ and the presence of the external capacitance.

4.4

Overflow Detection

The CS4461 includes modulator overflow detection, indicated on pin 15, OVERFLOW (open drain, active
low). OVERFLOW will go to a logical low as soon as an overrange condition is detected. The data will re-
main low until the condition is cleared.

4.5

Grounding and Power Supply Decoupling

As with any high resolution converter, the CS4461 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure

shows the recommended power ar-

rangements, with VA and VDP connected to clean supplies. VDP, which powers the digital logic, may be
run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no
additional devices should be powered from VDP. Decoupling capacitors should be as near to the ADC as
possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be
kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulator. The FILT+
and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path
from FILT+ to GND. The CDB44800 evaluation board demonstrates the optimum layout and power supply
arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.

DS650F1

CS4461

5. PACKAGE DIMENSIONS

Notes:

1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.

2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not re-
duce dimension "b" by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

INCHES

MILLIMETERS

NOTE

DIM

MIN

NOM

MAX

MIN

NOM

MAX

0.043

1.10

0.002

0.004

0.006

0.05

0.15

0.03346

0.0354

0.037

0.85

0.90

0.95

0.00748

0.0096

0.012

0.19

0.245

0.30

0.303

0.307

0.311

7.70

7.80

7.90

0.248

0.2519

0.256

6.30

6.40

6.50

0.169

0.1732

0.177

4.30

4.40

4.50

0.026 BSC

0.65 BSC

0.020

0.024

0.028

0.50

0.60

0.70

0°

4°

8°

0°

4°

8°

JEDEC #: MO-153

Controlling Dimension is Millimeters.

24L TSSOP (4.4 mm BODY) PACKAGE DRAWING

1 2 3

SEATING

PLANE

SIDE VIEW

END VIEW

TOP VIEW

DS650F1

CS4461

6. ORDERING INFORMATION

7. REVISION HISTORY

Product

Description

Package Pb-Free

Grade

Temp Range

Container

Order #

CS4461

Multi-bit A/D for

Class-D Real-time

PSR Feedback

24-TSSOP

YES

Commercial -10° to +70° C

Rail

CS4461-CZZ

Tape & Reel

CS4461-CZZR

Automotive

-40° to +85° C

Rail

CS4461-DZZ

Tape & Reel

CS4461-DZZR

CDB44800

Evaluation board for

the CS44800/600

and the CS4461

CDB44800

Release

Date

Changes

May 2004

1st Advance Release

September 2005

Updated ordering information

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to

www.cirrus.com

IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject

to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant

information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale

supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus

for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third

parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,

copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-

sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent

does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-

ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE

IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE-

VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDER-

STOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,

INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT

THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL

APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND

OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION

WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks

or service marks of their respective owners.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CDB44800

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CDB44800