Preliminary Product Information

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright

P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com

CS4202

Audio Codec '97 with Headphone Amplifier

Features

AC '97 2.2 Compliant

Exceeds the Microsoft

PC 2001 Audio

Performance Requirements

Integrated High-Performance Headphone
Amplifier

On-chip PLL for use with External Clock
Sources

Integrated High-Performance Microphone
Pre-Amplifier

Automatic Jack Sense through GPIO

BIOS-Driver Interface for Audio Feature
Configuration through Software

S/PDIF Digital Audio Output

S Serial Digital Outputs Enable Cost

Effective Six Channel Applications

Independent Simultaneous S/PDIF and Six
Channel Audio Playback

20-bit Stereo Digital-to-Analog Converters

18-bit Stereo Analog-to-Digital Converters

Sample Rate Converters
Three Analog Line-level Stereo Inputs
High Quality Pseudo-Differential CD Input
Two Analog Line-level Mono Inputs
Dual Microphone Inputs
Stereo and Mono Line-level Outputs
Extensive Power Management Support

Description

The CS4202 is an AC '97 2.2 compliant stereo audio co-
dec designed for PC multimedia systems. It uses
industry leading delta-sigma and mixed signal technolo-
gy. This advanced technology and these features are
designed to help enable the design of PC 99 and
PC 2001 compliant high-quality audio systems for desk-
top, portable, and entertainment PCs.

Coupling the CS4202 with a PCI audio accelerator or
core logic supporting the AC '97 interface implements a
cost effective, superior quality audio solution. The
CS4202 surpasses PC 99, PC 2001, and AC '97 2.2 au-
dio quality standards.

ORDERING INFO

CS4202-JQ

48-pin TQFP

9x9x1.4 mm

AC '97

REGISTERS

LINE

AUX

VIDEO

MIC1

MIC2

PHONE

PC_BEEP

LINE_OUT

HP_OUT

MONO_OUT

ANALOG INPUT MUX

AND OUTPUT MIXER

AC-LINK AND AC '97

REGISTERS

PCM_DATA

GAIN / MUTE CONTROLS

INPUT

MUX

OUTPUT

MIXER

MIXER / MUX SELECTS

AC-

LINK

PWR
MGT

TEST

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

PCM_DATA

SRC

ID0#

ID1#

GPIO, S/PDIF

SERIAL DATA PORT

EAPD

SPDIF_OUT

GPIO[4:0]

SDOUT,LRCLK,SCLK

18 bit

ADC

20 bit

DAC

INPUT
MIXER

MAY '02

DS549PP1

CS4202

DS549PP1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 6

ANALOG CHARACTERISTICS ................................................................................................ 6
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 7
RECOMMENDED OPERATING CONDITIONS ....................................................................... 7
AC '97 SERIAL PORT TIMING................................................................................................. 9

2. GENERAL DESCRIPTION ..................................................................................................... 12

2.1 AC-Link ............................................................................................................................ 12
2.2 Control Registers ............................................................................................................. 13
2.3 Sample Rate Converters .................................................................................................. 13
2.4 Mixers .............................................................................................................................. 13
2.5 Input Mux ......................................................................................................................... 13
2.6 Volume Control ................................................................................................................ 13

3. AC-LINK FRAME DEFINITION .............................................................................................. 15

3.1 AC-Link Serial Data Output Frame .................................................................................. 16
3.1.1 Serial Data Output Slot Tags (Slot 0)............................................................................. 16
3.1.2 Command Address Port (Slot 1) .................................................................................... 16
3.1.3 Command Data Port (Slot 2).......................................................................................... 17
3.1.4 PCM Playback Data (Slots 3-4,6-11) ............................................................................. 17
3.1.5 GPIO Pin Control (Slot12).............................................................................................. 17
3.2 AC-Link Serial Data Input Frame ..................................................................................... 18
3.2.1 Serial Data Input Slot Tag Bits (Slot 0) ........................................................................ 18
3.2.2 Status Address Port (Slot 1) .......................................................................................... 18
3.2.3 Status Data Port (Slot 2) ................................................................................................ 19
3.2.4 PCM Capture Data (Slot 3-4,6-8,11).............................................................................. 19
3.2.5 GPIO Pin Status (Slot 12) ............................................................................................. 19
3.3 AC-Link Protocol Violation - Loss of SYNC ..................................................................... 20

4. REGISTER INTERFACE

..................................................................................................... 21

4.1 Reset Register (Index 00h) .............................................................................................. 22
4.2 Analog Mixer Output Volume Registers (Index 02h - 04h) .............................................. 22
4.3 Mono Volume Register (Index 06h) .................................................................................. 23
4.4 PC_BEEP Volume Register (Index 0Ah) .......................................................................... 23

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm

IMPORTANT NOTICE

"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product infor-
mation describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the infor-
mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-
marks or service marks of their respective owners.

CS4202

DS549PP1

4.5 Phone Volume Register (Index 0Ch) ................................................................................ 23
4.6 Microphone Volume Register (Index 0Eh)........................................................................ 24
4.7 Analog Mixer Input Gain Registers (Index 10h - 18h) ...................................................... 25
4.8 Input Mux Select Register (Index 1Ah) ............................................................................. 26
4.9 Record Gain Register (Index 1Ch) ................................................................................... 27
4.10 General Purpose Register (Index 20h) ......................................................................... 28
4.11 Powerdown Control/Status Register (Index 26h) ........................................................... 29
4.12 Extended Audio ID Register (Index 28h) ........................................................................ 30
4.13 Extended Audio Status/Control Register (Index 2Ah) .................................................... 31
4.14 Audio Sample Rate Control Registers (Index 2Ch - 32h) ............................................... 32
4.15 S/PDIF Control Register (Index 3Ah) ............................................................................. 33
4.16 Extended Modem ID Register (Index 3Ch) .................................................................... 34
4.17 Extended Modem Status/Control Register (Index 3Eh) ................................................. 34
4.18 GPIO Pin Configuration Register (Index 4Ch) ................................................................ 34
4.19 GPIO Pin Polarity/Type Configuration Register (Index 4Eh) .......................................... 35
4.20 GPIO Pin Sticky Register (Index 50h) ............................................................................ 35
4.21 GPIO Pin Wakeup Mask Register (Index 52h) ............................................................... 36
4.22 GPIO Pin Status Register (Index 54h)............................................................................ 36
4.23 AC Mode Control Register (Index 5Eh) .......................................................................... 36
4.24 Misc. Crystal Control Register (Index 60h) ..................................................................... 38
4.25 Serial Port Control Register (Index 6Ah) ........................................................................ 39
4.26 BIOS-Driver Interface Control Registers (Index 70h - 72h) ............................................ 40
4.27 BIOS-Driver Interface Status Register (Index 7Ah) ........................................................ 40
4.28 Vendor ID1 Register (Index 7Ch) ................................................................................... 41
4.29 Vendor ID2 Register (Index 7Eh) ................................................................................... 41

5. SERIAL DATA PORTS ........................................................................................................... 42

5.1 Overview .......................................................................................................................... 42
5.2 Multi-Channel Expansion ................................................................................................. 42
5.3 Serial Data Formats ......................................................................................................... 43

6. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) ................................................................... 44
7. EXCLUSIVE FUNCTIONS ...................................................................................................... 44
8. POWER MANAGEMENT ....................................................................................................... 45

8.1 AC '97 Reset Modes ........................................................................................................ 45

8.1.1 Cold Reset .......................................................................................................... 45
8.1.2 Warm Reset ........................................................................................................ 45
8.1.3 New Warm Reset ................................................................................................ 45
8.1.4 Register Reset .................................................................................................... 45

8.2 Powerdown Controls ....................................................................................................... 46

9. CLOCKING ............................................................................................................................. 48

9.1 PLL Operation (External Clock) ....................................................................................... 48
9.2 24.576 MHz Crystal Operation ........................................................................................ 48
9.3 Secondary Codec Operation ........................................................................................... 48

10. ANALOG HARDWARE DESCRIPTION ............................................................................... 50

10.1 Analog Inputs ................................................................................................................. 50

10.1.1 Line Inputs ........................................................................................................ 50
10.1.2 CD Input ............................................................................................................ 50
10.1.3 Microphone Inputs ............................................................................................ 50
10.1.4 PC Beep Input ................................................................................................... 51
10.1.5 Phone Input ....................................................................................................... 51

10.2 Analog Outputs .............................................................................................................. 51

10.2.1 Stereo Outputs .................................................................................................. 51
10.2.2 Mono Output ..................................................................................................... 52

10.3 Miscellaneous Analog Signals ....................................................................................... 52
10.4 Power Supplies .............................................................................................................. 52

CS4202

DS549PP1

10.5 Reference Design .......................................................................................................... 53

11. GROUNDING AND LAYOUT .............................................................................................. 54

12. PIN DESCRIPTIONS

........................................................................................................ 56

13. PARAMETER AND TERM DEFINITIONS ............................................................................ 62

14. REFERENCE DESIGN

................................................................................................... 64

15. REFERENCES ...................................................................................................................... 65

16. PACKAGE DIMENSIONS ..................................................................................................... 66

LIST OF FIGURES

Figure 1. Power Up Timing............................................................................................................ 10

Figure 2. Codec Ready from Start-up or Fault Condition .............................................................. 10

Figure 3. Clocks ............................................................................................................................ 10

Figure 4. Data Setup and Hold ...................................................................................................... 11

Figure 5. PR4 Powerdown and Warm Reset ................................................................................ 11

Figure 6. Test Mode ...................................................................................................................... 11

Figure 7. AC-link Connections....................................................................................................... 12

Figure 8. CS4202 Mixer Diagram .................................................................................................. 14

Figure 9. AC-link Input and Output Framing.................................................................................. 15

Figure 10. Serial Data Port: Six Channel Circuit ........................................................................... 42

Figure 11. Serial Data Format 0 (I2S) ........................................................................................... 43

Figure 12. Serial Data Format 1 (Left Justified) ............................................................................ 43

Figure 13. Serial Data Format 2 (Right Justified, 20-bit data) ....................................................... 43

Figure 14. Serial Data Format 3 (Right Justified, 16-bit data) ....................................................... 43

Figure 15. S/PDIF Output.............................................................................................................. 44

Figure 16. PLL External Loop Filter............................................................................................... 48

Figure 17. External Crystal ............................................................................................................ 49

Figure 18. Line Input (Replicate for Video and AUX) .................................................................... 50

Figure 19. Differential 1 VRMS CD Input ...................................................................................... 50

Figure 20. Microphone Input ......................................................................................................... 51

Figure 21. PC_BEEP Input............................................................................................................ 51

Figure 22. Modem Connection ...................................................................................................... 51

Figure 23. Line Out and Headphone Out Setup ............................................................................ 52

Figure 24. Line Out/Headphone Out Setup ................................................................................... 52

Figure 25. +5V Analog Voltage Regulator..................................................................................... 53

Figure 26. Conceptual Layout for the CS4202 when in XTAL or OSC Clocking Modes ............... 55

Figure 27. Pin Locations for the CS4202 ...................................................................................... 56

Figure 28. CS4202 Reference Design .......................................................................................... 64

CS4202

DS549PP1

LIST OF TABLES

Table 1. Register Overview for the CS4202 ..................................................................... 21
Table 2. Analog Mixer Output Attenuation........................................................................ 22
Table 3. Microphone Input Gain Values ........................................................................... 24
Table 4. Analog Mixer Input Gain Values ......................................................................... 25
Table 5. Analog Mixer Input Gain Register Index ............................................................. 25
Table 6. Input Mux Selection ............................................................................................ 26
Table 7. Record Gain Values ........................................................................................... 27
Table 8. Slot Mapping for the CS4202 ............................................................................. 30
Table 9. Slot Assignment Defaults ................................................................................... 30
Table 10. Directly Supported SRC Sample Rates for the CS4202................................... 32
Table 11. GPIO Input/Output Configurations.................................................................... 35
Table 12. Serial Data Format Selection............................................................................ 39
Table 13. Device ID with Corresponding Part Number..................................................... 41
Table 14. Serial Data Formats and Compatible DACs for the CS4202 ............................ 43
Table 15. Powerdown PR Bit Functions ........................................................................... 46
Table 16. Powerdown PR Function Matrix for the CS4202 .............................................. 47
Table 17. Power Consumption by Powerdown Mode for the CS4202 ............................. 47
Table 18. Clocking Configurations for the CS4202 .......................................................... 49

CS4202

DS549PP1

1. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS

(Standard test conditions unless otherwise noted: T

ambient

= 25° C,

AVdd = 5.0 V ±5%, DVdd = 3.3 V ±5%; 1 kHz Input Sine wave; Sample Frequency, Fs = 48 kHz; Z

=100 k

1000 pF load for Mono and Line Outputs; C

= 18 pF load (Note 1); Measurement bandwidth is 20 Hz - 20 kHz,

18-bit linear coding for ADC functions, 20-bit linear coding for DAC functions; Mixer registers set for unity gain.

Notes: 1. Z

refers to the analog output pin loading and C

refers to the digital output pin loading.

2. Parameter definitions are given in Section 13, Parameter and Term Definitions.
3. Path refers to the signal path used to generate this data. These paths are defined in Section 13,

Parameter and Term Definitions.

4. This specification is guaranteed by silicon characterization; it is not production tested.

Parameter

(Note 2)

Symbol

Path

(Note 3)

CS4202-JQ

Unit

Min

Typ

Max

Full Scale Input Voltage
Line Inputs
Mic Inputs

(10dB = 0, 20dB = 0)

Mic Inputs

(10dB = 1, 20dB = 0)

Mic Inputs

(10dB = 0, 20dB = 1)

Mic Inputs

(10dB = 1, 20dB = 1)

A-D
A-D
A-D
A-D
A-D

0.91
0.91

0.283
0.091

0.0283

1.00
1.00

0.315

0.10

0.0315

-
-
-
-
-

RMS

Full Scale Output Voltage
Line and Mono Outputs
Headphone Output

D-A
D-A

0.91

1.0
1.4

1.13

RMS

Frequency Response

(Note 4)

Analog

Ac = ± 0.25 dB

DAC

Ac = ± 0.25 dB

ADC

Ac = ± 0.25 dB

A-A

D-A
A-D

20
20
20

-
-
-

20,000
20,000
20,000

Hz
Hz
Hz

Dynamic Range
Stereo Analog Inputs to LINE_OUT
Mono Analog Input to LINE_OUT
DAC Dynamic Range
ADC Dynamic Range

A-A
A-A

D-A
A-D

90
85
85
85

95
90
90
90

-
-
-
-

dB FS A
dB FS A
dB FS A
dB FS A

DAC SNR
(-20 dB FS input w/ CCIR-RMS filter on output)

SNR

D-A

Total Harmonic Distortion + Noise
(-3 dB FS input signal):
Line Output
Headphone Output
DAC
ADC

(all inputs)

THD+N

A-A
A-A

D-A
A-D

-
-
-
-

-90
-75
-87
-84

-80
-70
-80
-80

dB FS
dB FS
dB FS
dB FS

Power Supply Rejection Ratio
(1 kHz, 0.5 V

RMS

w/ 5 V DC offset)

(Note 4)

Interchannel Isolation

Spurious Tone

(Note 4)

-100

dB FS

Input Impedance

(Note 4)

CS4202

DS549PP1

ANALOG CHARACTERISTICS

(Continued)

MIXER CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

(AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

RECOMMENDED OPERATING CONDITIONS

(AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

Parameter

(Note 2)

Symbol

Path

(Note 3)

CS4202-JQ

Unit

Min

Typ

Max

External Load Impedance
Line Output, Mono Output
Headphone Output

10
32

-
-

Output Impedance
Line Output, Mono Output
Headphone Output

(Note 4)

-
-

730

0.8

-
-

Input Capacitance

(Note 4)

Vrefout

2.3

2.4

2.5

Parameter

Min

Typ

Max

Unit

Mixer Gain Range Span
PC Beep
Line In, Aux, CD, Video, Mic1, Mic2, Phone
Mono Out, Line Out, Headphone Out
ADC Gain

-
-
-
-

45.0
46.5
46.5
22.5

-
-
-
-

dB
dB
dB
dB

Step Size
All volume controls except PC Beep
PC Beep

-
-

1.5
3.0

-
-

dB
dB

Parameter

Min

Typ

Max

Unit

Power Supplies

+3.3 V Digital

+5 V Digital

Analog

-0.3
-0.3
-0.3

-
-
-

5.5
5.5
5.5

V
V
V

Total Power Dissipation

(Supplies, Inputs, Outputs)

1.25

Input Current per Pin

(Except Supply Pins)

-10

Output Current per Pin

(Except Supply Pins)

-15

Analog Input voltage

-0.3

AVdd+

0.3

Digital Input voltage

-0.3

DVdd +

0.3

Ambient Temperature

(Power Applied)

°C

Storage Temperature

-65

150

°C

Parameter

Symbol

Min

Typ

Max

Unit

Power Supplies

+3.3 V Digital

+5 V Digital

Analog

DVdd1, DVdd2
DVdd1, DVdd2

AVdd1, AVdd2

3.135

4.75
4.75

3.3

5
5

3.465

5.25
5.25

V
V
V

Operating Ambient Temperature

°C

CS4202

DS549PP1

AC '97 SERIAL PORT TIMING

Standard test conditions unless otherwise noted: T

ambient

= 25° C,

AVdd = 5.0 V, DVdd = 3.3 V; C

= 55 pF load.

Parameter

Symbol

Min

Typ

Max

Unit

RESET Timing

RESET# active low pulse width

rst_low

1.0

µs

RESET# inactive to BIT_CLK start-up delay

(XTL mode)

(OSC mode)

(PLL mode)

rst2clk

-
-
-

4.0
4.0
2.5

-
-
-

µs

1st SYNC active to CODEC READY `set'

sync2crd

62.5

µs

Vdd stable to RESET# inactive

vdd2rst#

100

µs

Clocks

BIT_CLK frequency

clk

12.288

MHz

BIT_CLK period

clk_period

81.4

BIT_CLK output jitter (depends on XTL_IN source)

750

BIT_CLK high pulse width

clk_high

40.7

BIT_CLK low pulse width

clk_low

40.7

SYNC frequency

sync

kHz

SYNC period

sync_period

20.8

µs

SYNC high pulse width

sync_high

1.3

µs

SYNC low pulse width

sync_low

19.5

µs

Data Setup and Hold

Output propagation delay from rising edge of BIT_CLK

Input setup time from falling edge of BIT_CLK

isetup

Input hold time from falling edge of BIT_CLK

ihold

Input signal rise time

irise

Input signal fall time

ifall

Output signal rise time

(Note 4)

orise

Output signal fall time

(Note 4)

ofall

Misc. Timing Parameters

End of Slot 2 to BIT_CLK, SDATA_IN low (PR4)

s2_pdown

0.285

1.0

µs

SYNC pulse width (PR4) Warm Reset

sync_pr4

1.0

µs

SYNC inactive (PR4) to BIT_CLK start-up delay

sync2clk

162.8

285

Setup to trailing edge of RESET# (ATE test mode) (Note 4)

setup2rst

Rising edge of RESET# to Hi-Z delay

(Note 4)

off

CS4202

DS549PP1

2. GENERAL DESCRIPTION

The CS4202 is a mixed-signal serial audio codec
with integrated headphone power amplifier com-
pliant with the Intel

Audio Codec '97 Specifica-

tion, revision 2.2 [6] (referred to as AC '97). It is
designed to be paired with a digital controller, typ-
ically located on the PCI bus or integrated within
the system core logic chip set. The controller is re-
sponsible for all communications between the
CS4202 and the remainder of the system. The
CS4202 contains two distinct functional sections:
digital and analog. The digital section includes the
AC-link interface, S/PDIF interface, serial data
port, GPIO, power management support, and Sam-
ple Rate Converters (SRCs). The analog section in-
cludes the analog input multiplexer (mux), stereo
input mixer, stereo output mixer, mono output mix-
er, headphone amplifier, stereo Analog-to-Digital
Converters (ADCs), stereo Digital-to-Analog Con-
verters (DACs), and their associated volume con-
trols.

2.1

AC-Link

All communication with the CS4202 is established
with a 5-wire digital interface to the controller
called the AC-link. This interface is shown in
Figure 7. All clocking for the serial communication
is synchronous to the BIT_CLK signal. BIT_CLK
is generated by the primary audio codec and is used
to clock the controller and any secondary audio co-
decs. Both input and output AC-link audio frames
are organized as a sequence of 256 serial bits form-
ing 13 groups referred to as `slots'. During each au-
dio frame, data is passed bi-directionally between
the CS4202 and the controller. The input frame is
driven from the CS4202 on the SDATA_IN line.
The output frame is driven from the controller on
the SDATA_OUT line. The controller is also re-
sponsible for issuing reset commands via the RE-
SET# signal. Following a Cold Reset, the CS4202
is responsible for notifying the controller that it is
ready for operation after synchronizing its internal
functions. The CS4202 AC-link signals must use
the same digital supply voltage as the controller, ei-
ther +5 V or +3.3 V. See Section 3, AC-Link Frame
Definition, for detailed AC-link information.

CODEC

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

Digital AC'97

Controller

AC'97

Figure 7. AC-link Connections

CS4202

DS549PP1

2.2

Control Registers

The CS4202 contains a set of AC '97 compliant
control registers, and a set of Cirrus Logic defined
control registers. These registers control the basic
functions and features of the CS4202. Read access-
es of the control registers by the AC '97 controller
are accomplished with the requested register index
in Slot 1 of a SDATA_OUT frame. The following
SDATA_IN frame will contain the read data in Slot
2. Write operations are similar, with the register in-
dex in Slot 1 and the write data in Slot 2 of a
SDATA_OUT frame. The function of each input
and output frame is detailed in Section 3, AC-Link
Frame Definition. Individual register descriptions
are found in Section 4, Register Interface.

2.3

Sample Rate Converters

The sample rate converters (SRC) provide high ac-
curacy digital filters supporting sample frequencies
other than 48 kHz to be captured from the CS4202
or played from the controller. AC '97 requires sup-
port for two audio rates (44.1 and 48 kHz). In addi-
tion, the Intel

I/O Controller Hub (ICHx)

specification [9] requires support for five more au-
dio rates (8, 11.025, 16, 22.05, and 32 kHz). The
CS4202 supports all these rates, as shown in
Table 10 on page 32.

2.4

Mixers

The CS4202 input and output mixers are illustrated
in Figure 8. The stereo input mixer sums together

the analog inputs to the CS4202 according to the
settings in the volume control registers. The stereo
output mixer sums the output of the stereo input
mixer with the PC_BEEP and PHONE signals. The
stereo output mix is then sent to the LINE_OUT
and HP_OUT pins of the CS4202. The mono out-
put mixer generates a monophonic sum of the left
and right audio channels from the stereo input mix-
er. The mono output mix is then sent to the
MONO_OUT pin on the CS4202.

2.5

Input Mux

The input multiplexer controls which analog input
is sent to the ADCs. The output of the input mux is
converted to stereo 18-bit digital PCM data and
transmitted to the controller by means of the
AC-link SDATA_IN signal.

2.6

Volume Control

The CS4202 volume registers control analog input
levels to the input mixer and analog output levels,
including the master volume level. The PC_BEEP
volume control uses 3 dB steps with a range of 0 dB
to -45 dB attenuation. All other analog volume con-
trols use 1.5 dB steps. The analog inputs have a
mixing range of +12 dB signal gain to -34.5 dB sig-
nal attenuation. The analog output volume controls
have a range of 0 dB to -46.5 dB attenuation for
LINE_OUT, HP_OUT and MONO_OUT.

CS4202

DS549PP1

3. AC-LINK FRAME DEFINITION

The AC-link is a bi-directional serial port with data
organized into frames consisting of one 16-bit and
twelve 20-bit time-division multiplexed slots.
Slot 0 is a special reserved time slot containing
16-bits which are used for AC-link protocol infra-
structure. Slots 1 through 12 contain audio or con-
trol/status data. Both the serial data output and
input frames are defined from the controller per-
spective, not from the CS4202 perspective.

The controller synchronizes the beginning of a
frame with the assertion of the SYNC signal.
Figure 9 shows the position of each bit location

within the frame. The first bit position in a new se-
rial data frame is F0 and the last bit position in the
serial data frame is F255. When SYNC goes active
(high) and is sampled active by the CS4202 (on the
falling edge of BIT_CLK), both devices are syn-
chronized to a new serial data frame. The data on
the SDATA_OUT pin at this clock edge is the final
bit of the previous frame's serial data. On the next
rising edge of BIT_CLK, the first bit of Slot 0 is
driven by the controller on the SDATA_OUT pin.
On the next falling edge of BIT_CLK, the CS4202
latches this data in as the first bit of the frame.

20.8

µ s

(48 kHz)

Tag Phase

Data Phase

12.288 MHz

81.4 ns

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

F16

F15

F14

F13

F12

F35

F56

F76

D19

F255

Valid

Frame

Slot 1

Valid

R/W

WD15

F36

F57

D19

D18

D19

D18

D19

RD15

F16

F15

F14

F13

F12

F35

F56

F76

F255

F36

F57

F255

GPIO

INT

F96

D19

Slot 0

Slot 1

Slot 2

Slot 3

Slot 4

Slots 5-12

Slot 2

Valid

Slot 1

Valid

Slot 2

Valid

Codec
Ready

Slot 12

Valid

Codec

ID1

Codec

ID0

Slot 12

Valid

GPIO

INT

Bit Frame Position:

Figure 9. AC-link Input and Output Framing

CS4202

DS549PP1

3.1

AC-Link Serial Data Output Frame

In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4202 from the AC '97
controller. Figure 9 illustrates the serial port timing.

The PCM playback data being passed to the CS4202 is shifted out MSB first in the most significant bits
of each slot. Any PCM data from the AC '97 controller that is not 20 bits wide should be left justified in
its corresponding slot and dithered or zero-padded in the unused bit positions.

Bits that are reserved should always be `cleared' by the AC '97 controller.

3.1.1

Serial Data Output Slot Tags (Slot 0)

Valid Frame

The Valid Frame bit determines if any of the following slots contain either valid playback data

for the CS4202 or data for read/write operations. When `set', at least one of the other AC-link
slots contains valid data. If this bit is `clear', the remainder of the frame is ignored.

Slot 1 Valid

The Slot 1 Valid bit indicates a valid register read/write address for a primary codec.

Slot 2 Valid

The Slot 2 Valid bit indicates valid register write data for a primary codec.

Slot [3:4,6:11] Valid

The Slot [3:4,6:11] Valid bits indicate the validity of data in their corresponding serial data out-

put slots. If a bit is `set', the corresponding output slot contains valid data. If a bit is `cleared',
the corresponding slot will be ignored.

Slot 12 Valid

The Slot 12 Valid bit indicates if output Slot 12 contains valid GPIO control data.

Codec ID[1:0]

The Codec ID[1:0] bits determine which codec is being accessed during the current AC-link

frame. Codec ID[1:0] = 00 indicates the primary codec is being accessed. Codec ID[1:0] = 01,
10, or 11 indicates one of three possible secondary codecs is being accessed. A Codec ID
value of 01, 10, or 11 also indicates a valid read/write address and/or valid register write data
for a secondary codec.

3.1.2

Command Address Port (Slot 1)

R/W

Read/Write. When this bit is `set', a read of the AC '97 register specified by the register index

bits will occur in the AC '97 2.x audio codec. When the bit is `cleared', a write will occur. For
any read or write access to occur, the Valid Frame bit (F0) must be `set' and the Codec ID[1:0]
bits (F[14:15]) must match the Codec ID of the AC '97 2.x audio codec being accessed. Ad-
ditionally, for a primary codec, the Slot 1 Valid bit (F1) must be `set' for a read access and
both the Slot 1 Valid bit (F1) and the Slot 2 Valid bit (F2) must be `set' for a write access. For
a secondary codec, both the Slot 1 Valid bit (F1) and the Slot 2 Valid bit (F2) must be `cleared'
for read and write accesses. See Figure 9 for bit frame positions.

RI[6:0]

CS4202. All registers are defined at word addressable boundaries. The RI0 bit must be `clear'
to access CS4202 registers.

Bit 15

Valid

Frame

Slot 1

Valid

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Not

Implem

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

Slot 10

Valid

Slot 11

Valid

Slot 12

Valid

Res

Codec

ID1

Codec

ID0

Bit 19

R/W

RI6

RI5

RI4

RI3

RI2

RI1

RI0

Reserved

CS4202

DS549PP1

3.1.3

Command Data Port (Slot 2)

WD[15:0]

Write Data. The WD[15:0] bits contain the 16-bit value to be written to the register. If an ac-

cess is a read, this slot is ignored.

NOTE:

For any write to an AC '97 register, the write is defined to be an `atomic' access. This means

that when the Slot 1 Valid bit in output Slot 0 is `set', the Slot 2 Valid bit in output Slot 0 should
always be `set' during the same audio frame. No write access may be split across 2 frames.

3.1.4

PCM Playback Data (Slots 3-4,6-11)

PD[19:0]

Playback Data. The PD[19:0] bits contain the 20-bit PCM (2's complement) playback data for

the left and right DACs, serial data ports, and/or the S/PDIF transmitter. Table 8 on page 30
lists a cross reference for each function and its respective slot. The mapping of a given slot
to the DAC, serial data port, or S/PDIF transmitter is determined by the state of the DSA[1:0]
bits in the Extended Audio ID Register (Index 28h) and the SPSA[1:0] bits in the Extended
Audio Status/Control Register (Index 2Ah).

3.1.5

GPIO Pin Control (Slot12)

GPIO[4:0]

GPIO Pin Control. The GPIO[4:0] bits control the CS4202 GPIO pins configured as outputs.
Write accesses using GPIO pin control bits configured as outputs will be reflected on the
GPIO pin output on the next AC-link frame. Write accesses using GPIO pin control bits con-
figured as inputs will have no effect and are ignored. If the GPOC bit in the Misc. Crystal Con-
trol Register (Index 60h) is `set', the bits in output Slot 12 are ignored and GPIO pins
configured as outputs are controlled through the GPIO Pin Status Register (Index 54h).

Bit 19

WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0

Reserved

Bit 19

PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Bit 19

Not Implemented

GPIO4 GPIO3 GPIO2 GPIO1 GPIO0

Reserved

CS4202

DS549PP1

3.2

AC-Link Serial Data Input Frame

In the serial data input frame, data is passed on the SDATA_IN pin from the CS4202 to the AC '97 con-
troller. The data format for the input frame is very similar to the output frame. Figure 9 on page 15 illus-
trates the serial port timing.

The PCM capture data from the CS4202 is shifted out MSB first in the most significant 18 bits of each slot.
The least significant 2 bits in each slot will be `cleared'. If the host requests PCM data from the AC '97
Controller that is less than 18 bits wide, the controller should dither and round or just round (but not trun-
cate) to the desired bit depth.

Bits that are reserved or not implemented in the CS4202 will always be returned `cleared'.

3.2.1

Serial Data Input Slot Tag Bits (Slot 0)

Codec Ready

Codec Ready. The Codec Ready bit indicates the readiness of the CS4202 AC-link. Immedi-
ately after a Cold Reset this bit will be `clear'. Once the CS4202 clocks and voltages are sta-
ble, this bit will be `set'. Until the Codec Ready bit is `set', no AC-link transactions should be
attempted by the controller. The Codec Ready bit does not indicate readiness of the DACs,
ADCs, Vref, or any other analog function. Those must be checked in the Powerdown Con-
trol/Status Register (Index 26h) by the controller before any access is made to the mixer reg-
isters. Any accesses to the CS4202 while Codec Ready is `clear' are ignored.

Slot 1 Valid

The Slot 1 Valid bit indicates Slot 1 contains a valid read back address.

Slot 2 Valid

The Slot 2 Valid bit indicates Slot 2 contains valid register read data.

Slot [3:4,6:8,11] Valid The Slot [3:4,6:8,11] Valid bits indicate Slot [3:4,6:8,11] contains valid capture data from the

CS4202 ADCs. If a bit is `set', the corresponding input slot contains valid data. If a bit is
`cleared', the corresponding slot will be ignored.

Slot 12 Valid

The Slot 12 Valid bit indicates Slot 12 contains valid GPIO status data.

3.2.2

Status Address Port (Slot 1)

RI[6:0]

Register Index. The RI[6:0] bits echo the AC '97 register address when a register read has
been requested in the previous frame. The CS4202 will only echo the register index for a read
access. Write accesses will not return valid data in Slot 1.

SR[3:4,6:11]

Slot Request. If SRx is `set', this indicates the CS4202 SRC does not need a new sample on
the next AC-link frame for that particular slot. If SRx is `clear', the SRC indicates a new sample
is needed on the following frame. If the VRA bit in the Extended Audio Status/Control Register
(Index 2Ah) is `clear', the SR[3:4,6:11] bits are always 0. When VRA is `set', the SRC is en-
abled and the SR[3:4,6:11] bits are used to request data.

Bit 15

Codec
Ready

Slot 1

Valid

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 11

Valid

Slot 12

Valid

Reserved

Bit 19

Res

RI6

RI5

RI4

RI3

RI2

RI1

RI0

SR3 SR4

SR6 SR7 SR8 SR9 SR10 SR11

Reserved

CS4202

DS549PP1

3.2.3

Status Data Port (Slot 2)

RD[15:0]

Read Data. The RD[15:0] bits contain the register data requested by the controller from the
previous read request. All read requests will return the read address in the input Slot 1 and
the register data in the input Slot 2 on the following serial data frame.

3.2.4

PCM Capture Data (Slot 3-4,6-8,11)

CD[17:0]

Capture Data. The CD [17:0] bits contain 18-bit PCM (2's complement) capture data. The

data will only be valid when the respective slot valid bit is `set' in input Slot 0. The mapping of
a given slot to an ADC is determined by the state of the ASA[1:0] bits in the AC Mode Control
Register (index 5Eh). The definition of each slot can be found in Table 8 on page 30.

3.2.5

GPIO Pin Status (Slot 12)

GPIO[4:0]

GPIO Pin Status. The GPIO[4:0] bits reflect the status of the CS4202 GPIO pins configured
as inputs. The pin status of GPIO pins configured as outputs will be reflected back on the
GPIO[4:0] bits of input Slot 12 in the next frame. The output GPIO pins are controlled by the
GPIO[4:0] pin control bits in output Slot 12.

BDI

BIOS-Driver Interface. The BDI bit indicates that a BIOS event has occurred. This bit is a logic
OR of all bits in the BDI Status Register (Index 7Ah) ANDed with their corresponding bit in the
BDI Config Register (Index 70h).

GPIO_INT

GPIO Interrupt. The GPIO_INT bit indicates that a GPIO or BDI interrupt event has occurred.

The occurrence of a GPIO interrupt is determined by the GPIO interrupt requirements as out-
lined in the GPIO Pin Wakeup Mask Register (Index 52h) description. In this case, the
GPIO_INT bit is cleared by writing a `0' to the bit in the GPIO Pin Status Register (Index 54h)
corresponding to the GPIO pin which generated the interrupt.

The occurrence of a BDI interrupt is determined by the BDI interrupt requirements as outlined

in the BDI Control Registers (Index 70h - 72h). In this case, the GPIO_INT bit is cleared by
writing a `0' to the bit in the BDI Status Register (Index 7Ah) that generated the interrupt.

Bit 19

RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

Reserved

Bit 19

CD17 CD16 CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0

Bit 19 18

GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Res BDI Res

GPIO

_INT

CS4202

DS549PP1

4. REGISTER INTERFACE

Reg

Register Name

D15 D14

D13

D12 D11 D10

Default

00h

Reset

ID8

ID7

ID4

0190h

02h

Master Volume

Mute

ML5

ML4

ML3

ML2

ML1

ML0

MR5

MR4

MR3

MR2

MR1

MR0

8000h

04h

Headphone Volume

Mute

ML5

ML4

ML3

ML2

ML1

ML0

MR5

MR4

MR3

MR2

MR1

MR0

8000h

06h

Mono Volume

Mute

MM5

MM4

MM3

MM2

MM1

MM0

8000h

0Ah

PC_BEEP Volume

Mute

PV3

PV2

PV1

PV0

0000h

0Ch

Phone Volume

Mute

GN4

GN3

GN2

GN1

GN0

8008h

0Eh

Mic Volume

Mute

20dB

GN4

GN3

GN2

GN1

GN0

8008h

10h

Line In Volume

Mute

GL4

GL3

GL2

GL1

GL0

GR4

GR3

GR2

GR1

GR0

8808h

12h

CD Volume

Mute

GL4

GL3

GL2

GL1

GL0

GR4

GR3

GR2

GR1

GR0

8808h

14h

Video Volume

Mute

GL4

GL3

GL2

GL1

GL0

GR4

GR3

GR2

GR1

GR0

8808h

16h

Aux Volume

Mute

GL4

GL3

GL2

GL1

GL0

GR4

GR3

GR2

GR1

GR0

8808h

18h

PCM Out Volume

Mute

GL4

GL3

GL2

GL1

GL0

GR4

GR3

GR2

GR1

GR0

8808h

1Ah

Record Select

SL2

SL1

SL0

SR2

SR1

SR0

0000h

1Ch

Record Gain

Mute

GL3

GL2

GL1

GL0

GR3

GR2

GR1

GR0

8000h

20h

General Purpose

MIX

LPBK

0000h

26h

Powerdown Ctrl/Stat

EAPD

PR6

PR5

PR4

PR3

PR2

PR1

PR0

REF

ANL

DAC

ADC

000Fh

28h

Ext'd Audio ID

ID1

ID0

REV1 REV0 AMAP

DSA1

DSA0

SPDIF

VRA

x605h

2Ah

Ext'd Audio Stat/Ctrl

SPCV

SPSA1 SPSA0

SPDIF

VRA

0410h

2Ch

PCM Front DAC Rate

SR15

SR14

SR13

SR12

SR11 SR10

SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

BB80h

32h

PCM L/R ADC Rate

SR15

SR14

SR13

SR12

SR11 SR10

SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

BB80h

3Ah

S/PDIF Control

DRS

SPSR1 SPSR0

CC6

CC5

CC4

CC3

CC2

CC1

CC0

PRE

COPY

/AUDIO

PRO

2000h

3Ch

Ext'd Modem ID

ID1

ID0

x000h

3Eh

Ext'd Modem Stat/Ctrl

PRA

GPIO

0100h

4Ch

GPIO Pin Config.

GC4

GC3

GC2

GC1

GC0

001Fh

4Eh

GPIO Pin Polarity/Type

GP4

GP3

GP2

GP1

GP0

FFFFh

50h

GPIO Pin Sticky

GS4

GS3

GS2

GS1

GS0

0000h

52h

GPIO Pin Wakeup

GW4

GW3

GW2

GW1

GW0

0000h

54h

GPIO Pin Status

GI4

GI3

GI2

GI1

GI0

0000h

Cirrus Logic Defined Registers:

5Eh

AC Mode Control

ASPM

TMM DDM

ASA1

ASA0

0000h

60h

Misc. Crystal Control

DPC

Reserved

10dB

CRST

GPOC

Reserved

LOSM

0003h

6Ah

Serial Port Control

SDEN

SDO2

SDSC

SDF1

SDF0

0000h

70h

BDI Config

E15

E14

E13

E12

E11

E10

0000h

72h

BDI Wakeup

E15

E14

E13

E12

E11

E10

0000h

7Ah

BDI Status

E15

E14

E13

E12

E11

E10

0000h

7Ch

Vendor ID1

4352h

7Eh

Vendor ID2

DID2

DID1

DID0

REV2

REV1

REV0

5971h

Table 1. Register Overview for the CS4202

CS4202

DS549PP1

4.1

Reset Register (Index 00h)

ID8

18-bit ADC Resolution. The ID8 bit is `set', indicating this feature is present.

ID7

20-bit DAC resolution. The ID7 bit is `set', indicating this feature is present.

ID4

Headphone Out. The ID4 bit is `set', indicating this feature is present. The state of this bit de-
pends on the state of the HPCFG pin.

Default

0190h. The data in this register is read-only data.

Any write to this register causes a Register Reset of the audio control (Index 00h - 3Ah) and Cirrus Logic defined
(Index 5Ah - 7Ah) registers. A read from this register returns configuration information about the CS4202.

4.2

Analog Mixer Output Volume Registers (Index 02h - 04h)

Mute

Output Mute. Setting this bit mutes the LINE_OUT_L/R or HP_OUT_L/R output signals.

ML[5:0]

Output Volume Left. These bits control the left output volume. Each step corresponds to 1.5
dB gain adjustment, with a total available range from 0 dB to -46.5 dB attenuation. Setting the
ML5 bit sets the left channel attenuation to -46.5 dB by forcing ML[4:0] to a `1' state. ML[5:0]
will read back 011111 when ML5 has been `set'. See Table 2 for further details.

MR[5:0]

Output Volume Right. These bits control the right output volume. Each step corresponds to
1.5 dB gain adjustment, with a total available range from 0 dB to -46.5 dB attenuation. Setting
the MR5 bit sets the right channel attenuation to -46.5 dB by forcing MR[4:0] to a `1' state.
MR[5:0] will read back 011111 when MR5 has been `set'. See Table 2 for further details.

Default

8000h. This value corresponds to 0 dB attenuation and Mute `set'.

If the HPCFG pin is left floating, register 02h controls the Master Output Volume and register 04h controls the Head-
phone Output Volume. If the HPCFG pin is tied `low', register 02h controls the Headphone Volume and register 04h
is a read-only register and always returns 0000h when `read'.

D15

D14

D13

D12

D11

D10

ID8

ID7

ID4

D15

D14

D13

D12

D11

D10

Mute

ML5

ML4

ML3

ML2

ML1

ML0

MR5

MR4

MR3

MR2

MR1

MR0

Mx5 - Mx0

Write

Mx5 - Mx0

Read

Gain

Level

000000

0 dB

000001

-1.5 dB

...

011111

-46.5 dB

100000

011111

-46.5 dB

...

111111

011111

-46.5 dB

Table 2. Analog Mixer Output Attenuation

CS4202

DS549PP1

4.3

Mono Volume Register (Index 06h)

Mute

Mono Mute. Setting this bit mutes the MONO_OUT output signal.

MM[5:0]

Mono Volume Control. The MM[5:0] bits control the mono output volume. Each step corre-

sponds to 1.5 dB gain adjustment, with a total available range from 0 dB to -46.5 dB attenu-
ation. Setting the MM5 bit sets the mono attenuation to -46.5 dB by forcing MM[4:0] to a `1'
state. MM[5:0] will read back 011111 when MM5 has been `set'. See Table 2 on page 22 for
further attenuation levels.

Default

8000h. This value corresponds to 0 dB attenuation and Mute `set'.

4.4

PC_BEEP Volume Register (Index 0Ah)

Mute

PC_BEEP Mute. Setting this bit mutes the PC_BEEP input signal.

PV[3:0]

PC_BEEP Volume Control. The PV[3:0] bits control the gain levels of the PC_BEEP input

source to the Input Mixer. Each step corresponds to 3 dB gain adjustment, with 0000 = 0 dB.
The total range is 0 dB to -45 dB attenuation.

Default

0000h. This value corresponds to 0 dB attenuation and Mute `clear'.

This register has no effect on the PC_BEEP volume during RESET#.

4.5

Phone Volume Register (Index 0Ch)

Mute

Phone Mute. Setting this bit mutes the Phone input signal.

GN[5:0]

Phone Volume Control. The GN[4:0] bits control the gain level of the Phone input source to

the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with 01000 = 0 dB. The
total range is +12 dB to -34.5 dB attenuation. See Table 4 on page 25 for further attenuation
levels.

Default

8008h. This value corresponds to 0 dB attenuation and Mute `set'.

D15

D14

D13

D12

D11

D10

Mute

MM5

MM4

MM3

MM2

MM1

MM0

D15

D14

D13

D12

D11

D10

Mute

PV3

PV2

PV1

PV0

D15

D14

D13

D12

D11

D10

Mute

GN4

GN3

GN2

GN1

GN0

CS4202

DS549PP1

4.6

Microphone Volume Register (Index 0Eh)

Mute

Microphone Mute. Setting this bit mutes the MIC1 or MIC2 signal. The selection of the MIC1

or MIC2 input pin is controlled by the MS bit in the General Purpose Register (Index 20h).

20dB

Microphone 20 dB Boost. When `set', the 20dB bit enables the +20 dB microphone boost

block. In combination with the 10dB boost bit in the Misc. Crystal Control Register (Index 60h)
this bit allows for variable boost from 0 dB to +30 dB in steps of 10 dB. Table 3 summarizes
this behavior.

GN[4:0]

Microphone Volume Control. The GN[4:0] bits are used to control the gain level of the Micro-

phone input source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with
01000 = 0 dB. The total range is +12 dB to -34.5 dB gain. See Table 3 for further details.

Default

8008h. This value corresponds to 0 dB gain and Mute `set'.

D15

D14

D13

D12

D11

D10

Mute

20dB

GN4

GN3

GN2

GN1

GN0

GN4 - GN0

Gain Level

10dB = 0,

20dB = 0

10dB = 1,

20dB = 0

10dB = 0,

20dB = 1

10dB = 1,

20dB = 1

00000

+12.0 dB

+22.0 dB

+32.0 dB

+42.0 dB

00001

+10.5 dB

+20.5 dB

+30.5 dB

+40.5 dB

...

00111

+1.5 dB

+11.5 dB

+21.5 dB

+31.5 dB

01000

0.0 dB

+10.0 dB

+20.0 dB

+30.0 dB

01001

-1.5 dB

+8.5 dB

+18.5 dB

+28.5 dB

...

11111

-34.5 dB

-24.5 dB

-14.5 dB

-4.5 dB

Table 3. Microphone Input Gain Values

CS4202

DS549PP1

4.7

Analog Mixer Input Gain Registers (Index 10h - 18h)

Mute

Stereo Input Mute. Setting this bit mutes the respective input signal, both right and left inputs.

GL[4:0]

Left Volume Control. The GL[4:0] bits are used to control the gain level of the left analog input
source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with
01000 = 0 dB. The total range is +12 dB to -34.5 dB gain. See Table 4 for further details.

GR[4:0]

Right Volume Control. The GR[4:0] bits are used to control the gain level of the right analog
input source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with
01000 = 0 dB. The total range is +12 dB to -34.5 dB gain. See Table 4 for further details.

Default

8808h. This value corresponds to 0 dB gain and Mute `set'.

The Analog Mixer Input Gain Registers are listed in Table 5.

D15

D14

D13

D12

D11

D10

Mute

GL4

GL3

GL2

GL1

GL0

GR4

GR3

GR2

GR1

GR0

Gx4 - Gx0 Gain Level

00000

+12.0 dB

00001

+10.5 dB

...

00111

+1.5 dB

01000

0.0 dB

01001

-1.5 dB

...

11111

-34.5 dB

Table 4. Analog Mixer Input Gain Values

Register Index

Function

10h

Line In Volume

12h

CD Volume

14h

Video Volume

16h

Aux Volume

18h

PCM Out Volume

Table 5. Analog Mixer Input Gain Register Index

CS4202

DS549PP1

4.11

Powerdown Control/Status Register (Index 26h)

EAPD

External Amplifier Power Down. The EAPD pin follows this bit and is generally used to power
down external amplifiers. The EAPD bit is mutually exclusive with the SDSC bit in the Serial
Port Control Register (Index 6Ah). The SDSC bit must be `clear' before the EAPD bit may be
`set'. If the SDSC bit is `set', EAPD is a read-only bit and always returns `0'.

PR6

Headphone Amplifier Powerdown. When `set', the headphone amplifier is powered down.

PR5

Internal Clock Disable. When `set', the internal master clock is disabled (BIT_CLK running).
The only way to recover from setting this bit is through a Cold Reset (driving the RESET# sig-
nal active).

PR4

AC-link Powerdown. When `set', the AC-link is powered down (BIT_CLK off). The AC-link can
be restarted through a Warm Reset using the SYNC signal, or a Cold Reset using the RE-
SET# signal (primary audio codec only).

PR3

Analog Mixer Powerdown (Vref off). When `set', the analog mixer and voltage reference are
powered down. When clearing this bit, the ANL, ADC, and DAC bits should be checked be-
fore writing any mixer registers.

PR2

Analog Mixer Powerdown (Vref on). When `set', the analog mixer is powered down (the volt-
age reference is still active). When clearing this bit, the ANL bit should be checked before writ-
ing any mixer registers.

PR1

Front DACs Powerdown. When `set', the DACs are powered down. When clearing this bit, the
DAC bit should be checked before sending any data to the DACs.

PR0

L/R ADCs and Input Mux Powerdown. When `set', the ADCs and the ADC input muxes are
powered down. When clearing this bit, no valid data will be sent down the AC-link until the
ADC bit goes high.

REF

Voltage Reference Ready Status. When `set', the REF bit indicates the voltage reference is
at a nominal level.

ANL

Analog Ready Status. When `set', the analog output mixer, input multiplexer, and volume con-
trols are ready. When `clear', no volume control registers should be written.

DAC

Front DAC Ready Status. When `set', the DACs are ready to receive data across the AC-link.
When `clear', the DACs will not accept any valid data.

ADC

L/R ADCs Ready Status. When `set', the ADCs are ready to send data across the AC-link.
When `clear', no data will be sent to the controller.

Default

000Fh. This value indicates all blocks are powered on. The lower four bits will change as the
CS4202 finishes an initialization and calibration sequence.

The PR[6:0] and the EAPD bits are powerdown control for different sections of the CS4202 as well as external am-
plifiers. The REF, ANL, DAC, and ADC bits are read-only status bits which, when `set', indicate that a particular sec-
tion of the CS4202 is ready. After the controller receives the Codec Ready bit in input Slot 0, these status bits must
be checked before writing to any mixer registers. See Section 8, Power Management, for more information on the
powerdown functions.

D15

D14

D13

D12

D11

D10

EAPD

PR6

PR5

PR4

PR3

PR2

PR1

PR0

REF

ANL

DAC

ADC

CS4202

DS549PP1

4.12

Extended Audio ID Register (Index 28h)

ID[1:0]

Codec ID. These bits indicate the current codec configuration. When ID[1:0] = 00, the

CS4202 is the primary audio codec. When ID[1:0] = 01, 10, or 11, the CS4202 is a secondary
audio codec. The state of the ID[1:0] bits is determined at power-up from the ID[1:0]# pins
and the current clocking scheme, see Table 18 on page 49.

REV[1:0]

AC '97 Revision. The REV[1:0] bits indicate which version of the AC '97 specification the co-

dec complies with. These bits always return `01', indicating the CS4202 complies with
version 2.2 of the AC '97 specification.

AMAP

Audio Slot Mapping. The AMAP bit indicates whether the AC '97 2.2 compliant AC-link slot to

audio DAC mapping is supported. This bit always returns `1', indicating that audio slot map-
ping is supported. The PCM playback and capture slots are mapped according to Table 8 on
page 30.

DSA[1:0]

DAC Slot Assignment. The DSA[1:0] bits control the mapping of output slots to the DAC/SRC

block as well as the serial data port. To satisfy AC `97 2.2 AMAP requirements, the default for
these bits will depend on the Codec ID as shown in Table 9. See Table 8 for all available Slot
Map settings.

SPDIF

Sony/Philips Digital Interface. The SPDIF bit is `set', indicating that the optional S/PDIF trans-

mitter is supported.

VRA

Variable Rate PCM Audio. The VRA bit indicates whether variable rate PCM audio is support-

ed. This bit always returns `1', indicating that variable rate PCM audio is available.

Default

x605h. The Extended Audio ID Register (Index 28h) is a read-only register, except for the

DSA[1:0] bits which are read/write.

D15

D14

D13

D12

D11

D10

ID1

ID0

REV1 REV0 AMAP

DSA1 DSA0

SPDIF

VRA

Slot Assignment

Slot Mapping

DSA1

SPSA1

ASA1

DSA0

SPSA0

ASA0

DAC

SDOUT

SDO2

S/PDIF

ADC

Table 8. Slot Mapping for the CS4202

Codec ID

DSA[1:0]

default

SPSA[1:0]

default

ASA[1:0]

default

Table 9. Slot Assignment Defaults

CS4202

DS549PP1

4.13

Extended Audio Status/Control Register (Index 2Ah)

SPCV

S/PDIF Configuration Valid. This read-only bit indicates the status of the S/PDIF transmitter

subsystem, enabling the driver to determine if the currently programmed S/PDIF configura-
tion is supported. SPCV is always valid, independent of the S/PDIF enable bit status.

SPSA[1:0]

S/PDIF Slot Assignment. These bits control the mapping of output slots to the S/PDIF trans-

mitter. To satisfy AC `97 2.2 AMAP requirements, the default for these bits will depend on the
Codec ID as shown in Table 9 on page 30. See Table 8 on page 30 for all available Slot Map
settings.

SPDIF

Enable Sony/Philips Digital Interface. This bit enables S/PDIF data transmission on the

SPDIF_OUT pin. The SPDIF bit routes the left and right channel data from the AC '97 con-
troller or from the ADC output to the S/PDIF transmitter block. The actual data routed to the
S/PDIF block are controlled through the configuration of the SPSA[1:0] bits and the ASPM bit
in the AC Mode Control Register (Index 5Eh).

VRA

Enable Variable Rate Audio. When `set', the VRA bit allows access to the PCM Front DAC

Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h). This bit must
be `set' in order to use variable PCM playback or capture rates. The VRA bit also serves as
a powerdown for the DAC and ADC SRC blocks. Clearing VRA will reset the PCM Front DAC
Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h) to their default
values. The SRC data path is flushed and the Slot Request bits for the currently active DAC
slots will be fixed at `0'.

Default

0410h

D15

D14

D13

D12

D11

D10

SPCV

SPSA1 SPSA0

SPDIF

VRA

CS4202

DS549PP1

4.14

Audio Sample Rate Control Registers (Index 2Ch - 32h)

SR[15:0]

Sample Rate Select. The Audio Sample Rate Control Registers (Index 2Ch - 32h) control

playback and capture sample rates. The PCM Front DAC Rate Register (Index 2Ch) controls
the Front Left and Front Right DAC sample rates. The PCM L/R ADC Rate Register
(Index 32h) controls the Left and Right ADC sample rates. There are seven sample rates di-
rectly supported by this register, shown in Table 10. Any value written to this register not con-
tained in Table 10 is not directly supported and will be decoded according to the ranges
indicated in the table. The range boundaries have been chosen so that only bits SR[15:12] of
each register will have to be considered. All register read transactions will reflect the actual
value stored (column 2 in Table 10) and not the one attempted to be written.

Default

BB80h. This value corresponds to 48 kHz sample rate.

Writes to the PCM Front DAC Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h) are only
available in Variable Rate PCM Audio mode when the VRA bit in the Extended Audio Status/Control Register
(Index 2Ah) is `set'. If VRA = 0, writes to the register are ignored and the register will always read BB80h.

D15

D14

D13

D12

D11

D10

SR15

SR14

SR13

SR12

SR11

SR10

SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

Sample Rate

(Hz)

SR[15:0], register

content (hex value)

SR[15:0], decode

range (hex value)

SR[15:12], decode

range (bin value)

8,000

1F40

0000 - 1FFF

0000 - 0001

11,025

2B11

2000 - 2FFF

0010 - 0010

16,000

3E80

3000 - 3FFF

0011 - 0011

22,050

5622

4000 - 5FFF

0100 - 0101

32,000

7D00

6000 - 7FFF

0110 - 0111

44,100

AC44

8000 - AFFF

1000 - 1010

48,000

BB80

B000 - FFFF

1011 - 1111

Table 10. Directly Supported SRC Sample Rates for the CS4202

CS4202

DS549PP1

4.15

S/PDIF Control Register (Index 3Ah)

Validity. The V bit is mapped to the V bit (bit 28) of every sub-frame. If this bit is `clear', the
signal is suitable for conversion or processing.

DRS

Double Rate S/PDIF. The DRS bit is mapped to bit 27 of the channel status block. This bit
controls support for optional higher sample rate transmission. The CS4202 does not support
double rate S/PDIF transmission, therefore DRS is a read-only bit and always returns `0'.

SPSR[1:0]

S/PDIF Sample Rate. The SPSR[1:0] bits are mapped to bits 24 and 25 of the channel status
block. These bits control the S/PDIF transmitter clock rate. The CS4202 only supports trans-
mission at the standard 48 kHz rate, therefore SPSR[1:0] are read-only bits and always
return `10'.

Generation Status. The L bit is mapped to bit 15 of the channel status block. For category
codes 001xxxx, 0111xxx and 100xxxx, a value of `0' indicates original material and a value of
`1' indicates a copy of original material. For all other category codes the definition of the L bit
is reversed.

CC[6:0]

Category Code. The CC[6:0] bits are mapped to bits 8-14 of the channel status block.

PRE

Data Pre-emphasis. The PRE bit is mapped to bit 3 of the channel status block. If the PRE bit
is `set', 50/15 µs filter pre-emphasis is indicated. If the bit is `clear', no pre-emphasis is indi-
cated.

COPY

Copyright. The COPY bit is mapped to bit 2 of the channel status block. If the COPY bit is `set'
copyright is not asserted and copying is permitted.

/AUDIO

Audio / Non-Audio. The /AUDIO bit is mapped to bit 1 of the channel status block. If the
/AUDIO bit is `clear', the data transmitted over S/PDIF is assumed to be digital audio. If the
/AUDIO bit is `set', non-audio data is assumed.

PRO

Professional/Consumer. The PRO bit is mapped to bit 0 of the channel status block. If the

PRO bit is `clear', consumer use of the audio control block is indicated. If the bit is `set', pro-
fessional use is indicated.

Default

2000h

For a further discussion of the proper use of the channel status bits see application note AN22: Overview of Digital
Audio Interface Data Structures [3]

D15

D14

D13

D12

D11

D10

DRS SPSR1 SPSR0

CC6

CC5

CC4

CC3

CC2

CC1

CC0

PRE

COPY /AUDIO PRO

CS4202

DS549PP1

4.16

Extended Modem ID Register (Index 3Ch)

ID[1:0]

Codec ID. These bits indicate the current codec configuration. When ID[1:0] = 00, the

Default

x000h. This value indicates no supported modem functions.

The Extended Modem ID Register (Index 3Ch) is a read/write register that identifies the CS4202 modem capabilities.
Writing any value to this location issues a reset to modem registers (Index 3Ch-54h), including GPIO registers
(Index 4Ch - 54h). Audio registers are not reset by a write to this location.

4.17

Extended Modem Status/Control Register (Index 3Eh)

PRA

GPIO Powerdown. When `set', the PRA bit powers down the GPIO subsystem. When the
GPIO section is powered down, all outputs must be tri-stated and input Slot 12 should be
marked invalid when the AC-link is active. To use any GPIO functionality PRA must be
cleared first.

GPIO

GPIO. When `set', the GPIO bit indicates the GPIO subsystem is ready for use. When `set',
input Slot 12 will also be marked valid.

Default

0100h

4.18

GPIO Pin Configuration Register (Index 4Ch)

GC[4:0]

GPIO Pin Configuration. When `set', the GC[4:0] bits define the corresponding GPIO pin as
an input. When `clear', the corresponding GPIO pin is defined as an output. When the SDEN
bit in the Serial Port Control Register (Index 6Ah) is `set', the GC[1:0] bits are read-only bits
and always return `0'. When SDEN is `clear', the GC[1:0] bits function normally. Likewise,
when the SDO2 bit in the Serial Port Control Register (Index 6Ah) is 'set', the GC4 bit is a
read-only bit and always returns '0'. When SDO2 is 'clear', the GC4 bit functions normally.
The GC[3:2] bits have no such dependency.

Default

001Fh. This value corresponds to all GPIO pins configured as inputs.

After a Cold Reset or a modem Register Reset (see Extended Modem ID Register (Index 3Ch)), all GPIO pins are
configured as inputs. The upper 11 bits of this register always return `0'.

D15

D14

D13

D12

D11

D10

ID1

ID0

D15

D14

D13

D12

D11

D10

PRA

GPIO

D15

D14

D13

D12

D11

D10

GC4

GC3

GC2

GC1

GC0

CS4202

DS549PP1

4.19

GPIO Pin Polarity/Type Configuration Register (Index 4Eh)

GP[4:0]

GPIO Pin Configuration. This register defines the GPIO input polarity (0 = Active Low,
1 = Active High) when a GPIO pin is configured as an input. The GP[4:0] bits define the GPIO
output type (0 = CMOS, 1 = OPEN-DRAIN) when a GPIO pin is configured as an output. The
GC[4:0] bits in the GPIO Pin Configuration Register (Index 4Ch) define the GPIO pins as in-
puts or outputs. See Table 11 for the various GPIO configurations.

Default

FFFFh

After a Cold Reset or a modem Register Reset this register defaults to all 1's. The upper 11 bits of this register al-
ways return `1'.

4.20

GPIO Pin Sticky Register (Index 50h)

GS[4:0]

GPIO Pin Sticky. This register defines the GPIO input type (0 = not sticky, 1 = sticky) when a

GPIO pin is configured as an input. The GPIO pin status of an input configured as "sticky" is
`cleared' by writing a `0' to the corresponding bit of the GPIO Pin Status Register (Index 54h),
and by reset.

Default

0000h

After a Cold Reset or a modem Register Reset this register defaults to all 0's, specifying "non-sticky". "Sticky" is de-
fined as edge sensitive, "non-sticky" as level sensitive. The upper 11 bits of this register always return `0'.

D15

D14

D13

D12

D11

D10

GP4

GP3

GP2

GP1

GP0

GCx GPx Function

Configuration

Output

CMOS Drive

Output

Open Drain

Input

Active Low

Input

Active High (default)

Table 11. GPIO Input/Output Configurations

D15

D14

D13

D12

D11

D10

GS4

GS3

GS2

GS1

GS0

CS4202

DS549PP1

4.21

GPIO Pin Wakeup Mask Register (Index 52h)

GW[4:0]

GPIO Pin Wakeup. This register provides a mask for determining if an input GPIO change will
generate a wakeup event (0 = no, 1 = yes). When the AC-link is powered up, a wakeup event
will be communicated through the assertion of GPIO_INT = 1 in input Slot 12. When the
AC-link is powered down (Powerdown Control/Status Register (Index 26h) bit PR4 = 1 for pri-
mary codecs), a wakeup event will be communicated through a `0' to `1' transition on
SDATA_IN.

Default

0000h

GPIO bits which have been programmed as inputs, "sticky", and "wakeup", upon transition either (high-to-low) or
(low-to-high) depending on pin polarity, will cause an AC-link wakeup if and only if the AC-link was powered down.
Once the controller has re-established communication with the CS4202 following a Warm Reset, it will continue to
signal the wakeup event through the GPIO_INT bit of input Slot 12 until the AC '97 controller clears the inter-
rupt-causing bit in the GPIO Pin Status Register (Index 54h); or the "wakeup", config, or "sticky" status of that GPIO
pin changes.

After a Cold Reset or a modem Register Reset (see Extended Modem ID Register (Index 3Ch)) this register defaults
to all 0's, specifying no wakeup event. The upper 11 bits of this register always return `0'.

4.22

GPIO Pin Status Register (Index 54h)

GI[4:0]

GPIO Pin Status. This register reflects the state of all GPIO pin inputs and outputs. These
values are also reflected in Slot 12 of every SDATA_IN frame. GPIO inputs configured as
"sticky" are `cleared' by writing a `0' to the corresponding bit of this register. The GPIO_INT
bit in input Slot 12 is `cleared' by clearing all interrupt-causing bits in this register.

Default

0000h

GPIO pins which have been programmed as inputs and "sticky", upon transition either (high-to-low) or (low-to-high)
depending on pin polarity, will cause the individual GI bit to be `set', and remain `set' until `cleared'. GPIO pins which
have been programmed as outputs are controlled either through output Slot 12 or through this register, depending
on the state of the GPOC bit in the Misc. Crystal Control Register (Index 60h). If the GPOC bit is `cleared', the GI
bits in this register are read-only and reflect the status of the corresponding GPIO output pin `set' through output
slot 12. If the GPOC bit is `set', the GI bits in this register are read/write bits and control the corresponding GPIO
output pins.

The default value is always the state of the GPIO pin. The upper 11 bits of this register should be forced to zero in
this register and input Slot 12.

4.23

AC Mode Control Register (Index 5Eh)

ASPM

Analog S/PDIF Mode. The ASPM bit controls the input source to the S/PDIF transmitter block.

When `clear', the S/PDIF transmitter will receive data from the corresponding AC-link output
slots. The actual slots are determined by the state of the SPSA[1:0] bits in the Extended Audio
Status/Control Register (Index 2Ah). If `set', the S/PDIF transmitter block will receive data

D15

D14

D13

D12

D11

D10

GW4

GW3

GW2

GW1

GW0

D15

D14

D13

D12

D11

D10

GI4

GI3

GI2

GI1

GI0

D15

D14

D13

D12

D11

D10

ASPM

TMM

DDM

ASA1

ASA0

CS4202

DS549PP1

4.24

Misc. Crystal Control Register (Index 60h)

DPC

DAC Phase Control. This bit controls the phase of the PCM stream sent to the DACs (after
SRC). When `cleared' the phase of the signal will remain unchanged. When this bit is `set',
each PCM sample will be inverted before being sent to the DACs.

10dB

Microphone 10 dB Boost. When `set', the 10dB bit enables an additional boost of 10 dB on
the selected microphone input. In combination with the 20dB boost bit in the Microphone Vol-
ume Register (Index 0Eh) this bit allows for variable boost from 0 dB to +30 dB in steps of
10 dB.

CRST

Force Cold Reset. The CRST bit is used as an override to the New Warm Reset behavior
defined during PR4 powerdown. If this bit is `set', an active RESET# signal will force a Cold
Reset to the CS4202 during a PR4 powerdown.

GPOC

General Purpose Output Control. The GPOC bit specifies the mechanism by which the status
of a General Purpose Output pin can be controlled. If this bit is `cleared', the GPO status is
controlled through the standard AC '97 method of setting the appropriate bits in output
Slot 12. If this bit is `set', the GPO status is controlled through the GPIO Pin Status Register
(Index 54h).

LOSM

Loss of SYNC Mute Enable. The LOSM bit controls the loss of SYNC mute function. If this bit

is `set', the CS4202 will mute all analog outputs for the duration of loss of SYNC. If this bit is
`cleared', the mixer will continue to function normally during loss of SYNC. The CS4202 ex-
pects to sample SYNC `high' for 16 consecutive BIT_CLK periods and then `low' for 240 con-
secutive BIT_CLK periods, otherwise loss of SYNC becomes true.

Default

0003h

D15

D14

D13

D12

D11

D10

DPC

Reserved

10dB

CRST

GPOC

Reserved

LOSM

CS4202

DS549PP1

4.25

Serial Port Control Register (Index 6Ah)

SDEN

Serial Data Output Enable. The SDEN bit enables transmission of serial data on the SDOUT
pin. The SDEN bit routes the left and right channel data from the AC '97 controller to the serial
data port. The actual data routed to the serial data port are controlled through the DSA[1:0]
configuration in the Extended Audio ID Register (Index 28h). SDEN also functions as a mas-
ter control for the second serial data output port and the serial clock. Setting this bit also dis-
ables the GPIO[1:0] pins and clears the GC[1:0] bits in the GPIO Pin Configuration Register
(Index 4Ch). Clearing this bit re-enables the GPIO[1:0] pins and sets the GC[1:0] bits.

SDO2

Serial Data Output 2 Enable. The SDO2 bit enables transmission of serial data on the
GPIO4/SDO2 pin. The SDO2 bit routes the left and right channel data from the AC '97 con-
troller to the second serial data port. The actual slots routed to the second serial data port are
controlled through the DSA[1:0] configuration in the Extended Audio ID Register (Index 28h).
This bit can only be `set' if the SDEN bit is `1' and will be `cleared' automatically if SDEN re-
turns to `0'. Setting this bit also disables the GPIO4 pin and clears the GC4 bit in the GPIO
Pin Configuration Register (Index 4Ch). Clearing this bit re-enables the GPIO4 pin and sets
the GC4 bit.

SDSC

Serial Clock Enable. The SDSC bit enables transmission of a serial clock on the EAPD/SCLK
pin. Serial data can be routed to DACs that support internal SCLK mode without transmitting
a serial clock. For DACs that only support external SCLK mode, transmission of a serial clock
is required and this bit must be set to `1'. This bit can only be set if the SDEN bit is `1' and will
be cleared automatically if SDEN returns to `0'. Furthermore, the SDSC bit can only be `set'
if the EAPD bit in the Powerdown Control/Status Register (Index 26h) is `0'. If the SDEN bit
is `0' or the EAPD bit is `1', SDSC is a read-only bit and always returns `0'.

SDF[1:0]

Serial Data Format. The SDF[1:0] bits control the format of the serial data transmitted on the
two output ports. All ports will use the same format. See Table 12 for available formats.

Default

0000h

D15

D14

D13

D12

D11

D10

SDEN

SDO2 SDSC SDF1

SDF0

SDF1 SDF0

Serial Data Format

Left Justified

Right Justified, 20-bit data

Right Justified, 16-bit data

Table 12. Serial Data Format Selection

CS4202

DS549PP1

4.26

BIOS-Driver Interface Control Registers (Index 70h - 72h)

E[15:0]

Event Configuration. The E[15:0] bits control the BIOS-Driver Interface mechanism.

Default

0000h

The BDI Config Register (Index 70h) enables BIOS-Driver communication for each possible event. If a bit is `0', the

corresponding event will not be communicated. If a bit is `1', the corresponding event will be communicated by as-
serting the BDI bit in input slot 12. If an event occurs, the BIOS will `set' the corresponding bit in the BDI Status Reg-
ister (Index 7Ah). This bit remains `set' until it is cleared by the driver, acknowledging the event has been handled.
This behavior is equivalent to "non-sticky" (level sensitive) GPIO input pins.

The BDI Wakeup Register (Index 72h) provides a mask for determining if a BDI event will generate a wakeup or

GPIO_INT. If a bit is `0', the corresponding event will not generate an interrupt. If a bit is `1', the corresponding event
will generate an interrupt. Refer to the GPIO Pin Wakeup Mask Register (Index 52h) for details about wakeup inter-
rupts.

4.27

BIOS-Driver Interface Status Register (Index 7Ah)

E[15:0]

Event Status. This register, in conjunction with the BIOS-Driver Interface Control Registers
(Index 70h - 72h), controls the BIOS-Driver Interface mechanism.

Default

0000h

The BDI Status Register (Index 7Ah) reflects the state of all possible events. If a bit is `0', the corresponding event

has not occurred or has already been handled by the driver. If a bit is `1', the corresponding event has occurred and
has not been handled by the driver yet. The BDI bit in input slot 12 is a logic OR of all bits in this register ANDed
with their corresponding bit in the BDI Config Register (Index 70h). After handling an event, the driver should clear
it by writing a `0' to the corresponding bit of this register.

D15

D14

D13

D12

D11

D10

E15

E14

E13

E12

E11

E10

D15

D14

D13

D12

D11

D10

E15

E14

E13

E12

E11

E10

CS4202

DS549PP1

4.28

Vendor ID1 Register (Index 7Ch)

F[7:0]

First Character of Vendor ID. With a value of F[7:0] = 43h, these bits define the ASCII `C' char-

acter.

S[7:0]

Second Character of Vendor ID. With a value of S[7:0] = 52h, these bits define the ASCII `R'

character.

Default

4352h. This register contains read-only data.

4.29

Vendor ID2 Register (Index 7Eh)

T[7:0]

Third Character of Vendor ID. With a value of T[7:0] = 59h, these bits define the ASCII `Y'

character.

DID[2:0]

Device ID. With a value of DID[2:0] = 111, these bits specify the audio codec is a CS4202.

REV[2:0]

Revision. With a value of REV[2:0] = 001, these bits specify the audio codec revision is `A'.

Default

597xh. This register contains read-only data.

The two Vendor ID registers provide a means to determine the manufacturer of the AC '97 audio codec. The first
three bytes of the Vendor ID registers contain the ASCII code for the first three letters of Crystal (CRY). The final
byte of the Vendor ID registers is divided into a Device ID field and a Revision field. Table 13 lists the currently de-
fined Device ID's.

D15

D14

D13

D12

D11

D10

D15

D14

D13

D12

D11

D10

DID2

DID1

DID0

REV2 REV1

REV0

DID2 - DID0

Part Name

000

CS4297

001

CS4297A

010

CS4294/CS4298

011

CS4299

100

CS4201

101

CS4205

110

CS4291

111

CS4202

Table 13. Device ID with Corresponding Part Number

CS4202

DS549PP1

5. SERIAL DATA PORTS

5.1

Overview

The CS4202 implements two serial data output
ports that can be used for multi-channel expansion.
Each serial port consists of 4 signals: MCLK,
SCLK, LRCLK, and SDATA. The existing 256 Fs
BIT_CLK will be used as MCLK. The clock pins
are shared between all the serial ports with only the
SDATA pins being separate; SDOUT for the first
output port, and SDO2 for the second output port.
Serial data is transmitted on these ports every
AC-link frame.

The serial data port is controlled by the SDEN,
SDSC, and SDO2 bits in the Serial Port Control
Register (Index 6Ah). All the serial data port pins
are multiplexed with other functions and cannot be
used unless the other function is disabled or pow-
ered down; see Section 7, Exclusive Functions.
Some audio DACs can run in an internal SCLK
mode where SCLK is internally derived from
MCLK and LRCLK. In this case, SCLK generation
in the CS4202 is optional.

A feature has been designed into the CS4202 that
allows the phase of the internal DACs to be re-
versed. This DAC phase reversal is controlled by

the DPC bit in the Misc. Crystal Control Register
(Index 60h). This feature is necessary since the
phase response for external DACs is unknown and
the phase response of the internal DACs can vary
depending on the path determined by the DDM bit
in the AC Mode Control Register (Index 5Eh) and
the output (LINE_OUT or HP_OUT) being used.
This feature guarantees that all DACs in a system
have the same phase response, maintaining the ac-
curacy of spatial cues.

Please note the data sent to the serial ports is
straight from the AC-link. There is no SRC and no
volume control available on this data, so it is the re-
sponsibility of the controller or host software to
provide this functionality if desired.

5.2

Multi-Channel Expansion

For multi-channel expansion, the two serial data
output ports are used to send AC-link data to one or
two external stereo DACs to support up to a total of
six channels. The first serial port takes the digital
audio data from the SDOUT slots. The second seri-
al port takes the digital audio data from the SDO2
slots. See Table 8 on page 30 for the actual slots
used depending on configuration. Figure 10 shows
a six channel application using the CS4202.

AOUTL

AOUTR

SDATA

DEM#/SCLK

LRCK
MCLK

GPIO1/SDOUT

GPIO4/SDO2

47
43

EAPD/SCLK

GPIO0/LRCLK

LINE_OUT_L

LINE_OUT_R

BIT_CLK

CS4334

AOUTL

AOUTR

SDATA
DEM#/SCLK
LRCK
MCLK

CS4334

270K

10uF

ELEC

10uF

ELEC

47K

560

2700pF 2700pF

Left Surround

Right Surround

270K

10uF

ELEC

10uF

ELEC

47K

560

2700pF 2700pF

Center

LFE

AGND

Left Front

Right Front

AGND

10uF

ELEC

10uF

ELEC

1000pF

AGND

220K

AGND

1000pF

Figure 10. Serial Data Port: Six Channel Circuit

CS4202

DS549PP1

5.3

Serial Data Formats

In order to support a wide variety of serial audio
DACs, the CS4202 can transmit serial data in four
different formats. The desired format is selected
through the SDF[1:0] bits in the Serial Port Control
Register (Index 6Ah). All serial ports use the same
serial data format when enabled. In all cases, LR-
CLK will be synchronous with Fs, and SCLK will

be 64 Fs (BIT_CLK/4). Serial data is transitioned by
the CS4202 on the falling edge of SCLK and latched
by the DACs on the next rising edge. Serial data is
shifted out MSB first in all supported formats, but
LRCLK polarity as well as data justification, align-
ment, and resolution vary. Table 14 shows the prin-
cipal characteristics of each serial format.

SDF[1:0]

LRCLK

Polarity

Data

Justification

Data Alignment

(MSB vs. LRCLK)

Data

Resolution

Timing

Diagram

Recommended

DAC

0 0

negative

left justified

1 SCLK delayed

20-bit

Figure 11

CS4334

0 1

positive

left justified

not delayed

20-bit

Figure 12

CS4335

1 0

positive

right justified

not delayed

20-bit

Figure 13

CS4337

1 1

positive

right justified

not delayed

16-bit

Figure 14

CS4338

Table 14. Serial Data Formats and Compatible DACs for the CS4202

L R C K

S C L K

L eft C ha n ne l

R ig h t C h a n ne l

S D A T A

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4 -5

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4

Figure 11. Serial Data Format 0 (I

L R C K

S C L K

L eft C ha n ne l

R ig h t C h a n ne l

S D A T A

+3 +2 +1 LSB

+5 +4

MSB-1 -2 -3 -4 -5

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4

Figure 12. Serial Data Format 1 (Left Justified)

L R C K

S C L K

Le ft C h ann el

R ight C ha nne l

S D A T A

15 14 13 12 11 10

17 16

19 18

Figure 13. Serial Data Format 2 (Right Justified, 20-bit data)

L R C K

S C L K

L e ft C ha n n e l

R ig h t C h a n n e l

S D A T A

15 14 13 12 11 10

Figure 14. Serial Data Format 3 (Right Justified, 16-bit data)

CS4202

DS549PP1

6. SONY/PHILIPS DIGITAL

INTERFACE (S/PDIF)

The S/PDIF digital output is used to interface the
CS4202 to consumer audio equipment external to
the PC. This output provides an interface for stor-
ing digital audio data or playing digital audio data
to digital speakers. Figure 15 illustrates the circuits
necessary for implementing the IEC-958 optical or
consumer interface. For further information on
S/PDIF operation see application note AN22: Over-
view of Digital Audio Interface Data Structures [3].
For further information on S/PDIF recommended
transformers see application note AN134: AES and
S/PDIF Recommended Transformers [4].

7. EXCLUSIVE FUNCTIONS

Some of the digital pins on the CS4202 have mul-
tiplexed functionality. These functions are mutual-
ly exclusive and cannot be requested at the same
time. The following pairs of functions are mutually
exclusive:

GPIO and Serial Data Port (GPIO0 pin is
shared with LRCLK pin, GPIO1 pin is shared

with SDOUT pin, and GPIO4 pin is shared with
SDO2 pin)

EAPD and Serial Data Port Serial Clock
(EAPD pin is shared with SCLK pin)

Use of the GPIO0/LRCLK, GPIO1/SDOUT, and
GPIO4/SDO2 pins for serial data port has priority
over their GPIO functionality. There is no priority
assigned to the other exclusive function. A function
currently in use must be disabled or powered down
before the corresponding exclusive function can be
enabled. The following control bits for these func-
tions will behave differently than normal bits: the
EAPD bit in the Powerdown Control/Status Regis-
ter (Index 26h), the GC[4,1:0] bits in the GPIO Pin
Configuration Register (Index 4Ch), and the
SDO2, and SDSC bits in the Serial Port Control
Register (Index 6Ah). These bits can become
read-only bits if they control a feature that is cur-
rently unavailable because the corresponding ex-
clusive

feature

already

use,

the

corresponding master control for this feature is not
set.

0.1

µF

DGND

DVdd

SPDIF_OUT

TOTX-173

SPDIF_OUT

+5V_PCI

DGND

8.2 k

DGND

3.3V

247.5

107.6

375

93.75

Figure 15. S/PDIF Output

CS4202

DS549PP1

8. POWER MANAGEMENT

8.1

AC '97 Reset Modes

The CS4202 supports four reset methods, as de-
fined in the AC '97 Specification: Cold Reset,
Warm Reset, New Warm Reset, and Register Reset.
A Cold Reset results in all AC '97 logic (registers
included) initialized to its default state. A Warm
Reset or New Warm Reset leaves the contents of
the AC '97 register set unaltered. A Register Reset
initializes only the AC '97 registers to their default
states.

8.1.1

Cold Reset

A Cold Reset is achieved by asserting RESET# for
a minimum of 1 µs after the power supply rails
have stabilized. This is done in accordance with the
minimum timing specifications in the AC '97 Seri-
al Port Timing section on page 9. Once de-asserted,
all of the CS4202 registers will be reset to their de-
fault power-on states and the BIT_CLK and
SDATA_IN signals will be reactivated.

8.1.2

Warm Reset

A Warm Reset allows the AC-link to be reactivated
without losing information in the CS4202 registers.
A Warm Reset is required to resume from a D3

hot

state where the AC-link had been halted yet full
power had been maintained. A primary codec
Warm Reset is initiated when the SYNC signal is
driven high for at least 1 µs and then driven low in
the absence of the BIT_CLK clock signal. The
BIT_CLK clock will not restart until at least 2 nor-

mal BIT_CLK clock periods (162.8 ns) after the
SYNC signal is de-asserted. A Warm Reset of the
secondary codec is recognized when the primary
codec on the AC-link resumes BIT_CLK genera-
tion. The CS4202 will wait for BIT_CLK to be sta-
ble to restore SDATA_IN activity, S/PDIF and/or
serial data port transmission on the following
frame.

8.1.3

New Warm Reset

The New Warm Reset also allows the AC-link to
be reactivated without losing information in the
registers. A New Warm Reset is required to resume
from a D3

cold

state where AC-link power has been

removed. New Warm Reset is recognized by the
low-high transition of RESET# after the AC-link
has been programmed into PR4 powerdown. The
New Warm Reset functionality can be disabled by
setting the CRST bit in the Misc. Crystal Control
Register (Index 60h).

8.1.4

Register Reset

The last reset mode provides a Register Reset to the
CS4202. This is available only when the CS4202
AC-link is active and the Codec Ready bit is `set'.
The audio (including extended audio) control reg-
isters (Index 00h - 3Ah) and the vendor specific
registers (Index 5Ah - 7Ah) are reset to their de-
fault states by a write of any value to the Reset Reg-
ister (Index 00h). The modem (including GPIO)
registers (Index 3Ch - 56h) are reset to their default
states by a write of any value to the Extended Mo-
dem ID Register (Index 3Ch).

CS4202

DS549PP1

8.2

Powerdown Controls

The

Powerdown

Control/Status

Register

(Index 26h) controls the power management func-
tions. The PR[6:0] bits in this register control the
internal powerdown states of the CS4202. Power-
down control is available for individual subsections
of the CS4202 by asserting any PRx bit or any com-
bination of PRx bits. All powerdown states except
PR4 and PR5 can be resumed by clearing the cor-
responding PRx bit. Table 15 shows the mapping
of the power control bits to the functions they man-
age.

When PR0 is `set', the L/R ADCs and the Input
Mux are shut down and the ADC bit in the Power-
down Control/Status Register (Index 26h) is
`cleared' indicating the ADCs are no longer in a
ready state. The same is true for PR1 and the
DACs, PR2 and the analog mixer, PR3 and the
voltage reference (Vrefout), and PR6 and the head-
phone amplifier. When one of these bits is
`cleared', the corresponding subsystem will begin a
power-on process, and the associated status bit will
be `set' when the hardware is ready.

In a primary codec the PR4 bit powers down the
AC-link, but all other analog and digital sub-

systems continue to function. The required resume

sequence from a PR4 state is either a Warm Reset

or a New Warm Reset, depending on whether a

hot

or D3

cold

state has been entered.

The PR5 bit disables all internal clocks and powers

down the DACs and the ADCs, but maintains oper-

ation of the BIT_CLK and the analog mixer. A

Cold Reset is the only way to restore operation to

the CS4202 after asserting PR5. To achieve a com-

plete digital powerdown, PR4 and PR5 must be as-

serted within a single AC output frame. This will

also drive BIT_CLK `low'.

The CS4202 does not automatically mute any input

or output when the powerdown bits are `set'. The

software driver controlling the AC '97 device must

manage muting the input and output analog signals

before putting the part into any power management

state. The definition of each PRx bit may affect a

single subsection or a combination of subsections

within the CS4202. Table 16 contains the matrix of

subsections affected by the respective PRx func-

tion. Table 17 shows the different operating power

consumptions levels for different powerdown func-

tions.

PR Bit

Function

PR0

L/R ADCs and Input Mux Powerdown

PR1

Front DACs Powerdown

PR2

Analog Mixer Powerdown (Vref on)

PR3

Analog Mixer Powerdown (Vref off)

PR4

AC-link Powerdown (BIT_CLK off)*

PR5

Internal Clock Disable

PR6

Headphone Out Powerdown

* Applies only to primary codec

Table 15. Powerdown PR Bit Functions

CS4202

DS549PP1

9. CLOCKING

The CS4202 may be operated as a primary or sec-
ondary codec. As a primary codec, the system clock
for the AC-link may be generated from an external
24.576 MHz clock source, a 24.576 MHz crystal, or
the internal Phase Locked Loop (PLL). The PLL al-
lows the CS4202 to accept external clock frequen-
cies other than 24.576 MHz. As a secondary codec,
the system clock is derived from BIT_CLK, which is
generated by the primary codec. The CS4202 uses
the presence or absence of a valid clock on the
XTL_IN pin in conjunction with the state of the
ID[1:0]# pins to determine the clocking configura-
tion. See Table 18 for all available CS4202 clocking
modes.

9.1

PLL Operation (External Clock)

The PLL mode is activated if a valid clock is present
on XTL_IN before the rising edge of RESET#. Once
PLL mode is entered, the XTL_OUT pin is redefined
as the PLL loop filter, as shown in Figure 16. The
ID[1:0]# inputs determine the configuration of the
internal divider ratios required to generate the
12.288 MHz BIT_CLK output; see Table 18 on
page 49 for additional details. In PLL mode, the
CS4202 is configured as a primary codec indepen-
dent of the state of the ID[1:0]# pins. If 24.576 MHz
is chosen as the external clock input (ID[1:0]# inputs
both pulled high or left floating), the PLL is disabled
and the clock is used directly. The loop filter is not
required and XTL_OUT is left unconnected. For all
other clock input choices, the loop filter is required.
The ID[1:0] bits of the Extended Audio ID Register
(Index 28h) and the Extended Modem ID Register
(Index 3Ch) will always report `00' in PLL mode.

9.2

24.576 MHz Crystal Operation

If a valid clock is not present on XTL_IN during the
rising edge of RESET#, the device disables the PLL
input and latches the state of the ID[1:0]# inputs. If
the ID[1:0]# inputs are both pulled high or left float-
ing, the device is configured as a primary codec. An
external 24.576 MHz crystal is used as the system
clock as shown in Figure 17.

9.3

Secondary Codec Operation

If a valid clock is not present on XTL_IN and either
ID[1:0]# input is pulled low during the rising edge of
RESET#, the device is determined to be a secondary
codec. The BIT_CLK pin is configured as an input
and the CS4202 is driven from the 12.288 MHz
BIT_CLK of the primary codec. The ID[1:0] bits of
the Extended Audio ID Register (Index 28h) and the
Extended Modem ID Register (Index 3Ch) will re-
port the state of the ID[1:0]# inputs.

Figure 16. PLL External Loop Filter

XTL_OUT

XTL_IN

2.2 k

0.022 uF

220 pF

Clock Source

DGND

CS4202

DS549PP1

10. ANALOG HARDWARE

DESCRIPTION

The analog input section consists of four stereo
line-level

inputs

(LINE_L/R,

CD_L/C/R,

VIDEO_L/R, and AUX_L/R), two selectable
mono microphone inputs (MIC1 and MIC2), and
two mono inputs (PC_BEEP and PHONE). The an-
alog output section consists of a mono output
(MONO_OUT),

stereo

headphone

output

(HP_OUT_L/R), and a stereo line-level output
(LINE_OUT_L/R). This section describes the ana-
log hardware needed to interface with these pins.
The designs presented in this section are compliant
with Chapter 17 of Microsoft's

PC 99 System De-

sign Guide [7] (referred to as PC 99) and Chapter
11 of Microsoft's

PC 2001 System Design Guide

[8] (referred to as PC 2001). For information on
EMI reduction techniques refer to the application
note AN165: CS4297A/CS4299 EMI Reduction
Techniques [5].

10.1

Analog Inputs

All analog inputs to the CS4202, including CD_C,
should be capacitively coupled to the input pins.
Unused analog inputs should be tied together and
connected through a capacitor to analog ground or
tied to the Vrefout pin directly. The maximum al-
lowed voltage for analog inputs, except the micro-
phone input, is 1 V

RMS

. The maximum allowed

voltage for the microphone input depends on the
selected boost setting.

10.1.1

Line Inputs

Figure 18 shows circuitry for a line-level stereo in-
put. Replicate this circuit for the Video and Aux in-
puts. This design attenuates the input by 6 dB,
bringing the signal from the PC 99 specified
2 V

RMS

, to the CS4202 maximum allowed 1 V

RMS

10.1.2

CD Input

The CD line-level input has an extra pin, CD_C,
providing a pseudo-differential input for both

CD_L

and

CD_R.

This

takes

the

common-mode noise out of the CD inputs when
connected to the CD analog source ground. Follow-
ing the reference design in Figure 19 provides extra
attenuation of common mode noise coming from
the CD-ROM drive, thereby producing a higher
quality signal. One percent resistors are recom-
mended since closely matched resistor values pro-
vide better common-mode attenuation of unwanted
signals. The circuit shown in Figure 19 can be used
for a 1 V

RMS

CD input signal.

10.1.3

Microphone Inputs

Figure 20 illustrates an input circuit suitable for dy-
namic and electret microphones. Electret, also
known as phantom-powered, microphones use the
right channel (ring) of the jack for power. The de-
sign also supports the recommended advanced fre-
quency response for voice recognition as specified
in PC 99 and PC 2001. The microphone input of the
CS4202 has an integrated pre-amplifier. Using
combinations of the 10dB bit in the Misc. Crystal
Control Register (Index 60) and the 20dB bit in the

LINE_IN_R

LINE_IN_L

6.8 k

1.0

µ F

1.0

µ F

AGND

6.8 k

Figure 18. Line Input (Replicate for Video and AUX)

100

CD_L

CD_COM

CD_R

1.0

µ F

CD_L

CD_R

CD_C

100

1.0

µF

100

47 k

2.2

µ F

47 k

AGND

Figure 19. Differential 1 V

RMS

CD Input

CS4202

DS549PP1

Mic Volume Register (Index 0Eh) the pre-amplifier

gain can be set to 0 dB, 10 dB, 20 dB, or 30 dB.

10.1.4

PC Beep Input

The PC_BEEP input is useful for mixing the output

of the "beeper" (timer chip), provided in most PCs,

with the other audio signals. When the CS4202 is

held in reset, PC_BEEP is passed directly to the line

output. This allows the system sounds or "beeps" to

be available before the AC '97 interface has been ac-

tivated. Figure 21 illustrates a typical input circuit for

the PC_BEEP input. If PC_BEEP is driven from a

CMOS gate, the 4.7 k

resistor should be tied to an-

alog ground instead of +5VA. Although this input is

described for a low-quality "beeper", it is of the same

high-quality as all other analog inputs and may be

used for other purposes.

10.1.5

Phone Input

One application of the PHONE input is to interface
to the output of a modem analog front end (AFE) de-
vice so that modem dialing signals and protocol ne-
gotiations may be monitored through the audio
system. Figure 22 shows a design for a modem con-
nection where the output is fed from the CS4202
MONO_OUT pin through a divider. The divider ra-
tio shown does not attenuate the signal, providing an
output voltage of 1 V

RMS

. If a lower output voltage

is desired, the resistors can be replaced with appro-
priate values, as long as the total load on the output
is kept greater than 10 k

. The PHONE input is di-

vided by 6 dB to accommodate a line-level source of
2 V

RMS

10.2

Analog Outputs

The analog output section provides a stereo, a head-
phone, and a mono output. The MONO_OUT,
LINE_OUT_L, and LINE_OUT_R pins require
680 pF to 1000 pF NPO dielectric capacitors be-
tween the corresponding pin and analog ground.
Each analog output is DC-biased up to the Vrefout
voltage signal reference, nominally 2.4 V. This re-
quires the outputs be AC-coupled to external circuit-
ry (AC loads must be greater than 10 k

for the line

output or 32

for the headphone output). The head-

phone coupling capacitors should be 220

µF or great-

er to minimize low frequency roll-off.

10.2.1

Stereo Outputs

The LINE_OUT and HP_OUT stereo outputs de-
pend on the configuration of the HPCFG pin. As
shown in Figure 23, if the HPCFG pin is left floating,

0.1

µ F

X7R

100

0.1

µF

X7R

MIC1/MIC2

µ F

ELEC

AGND

+5VA

2.2 k

1.5 k

AGND

Figure 20. Microphone Input

4.7 k

PC_BEEP

+5VA (Low Noise) or

AGND if CMOS Source

PC-BEEP-BUS

47 k

2.7 nF

X7R

0.1

µF

X7R

AGND

Figure 21. PC_BEEP Input

PHONE

MONO_OUT

PHONE

MONO_OUT

6.8 k

1.0

µ F

6.8 k

1.0

µ F

47 k

AGND

1000 pF

Figure 22. Modem Connection

CS4202

DS549PP1

the part behaves as specified in AC '97. As shown in
Figure 24, if the HPCFG pin is grounded, the part be-
haves as if HP_OUT was the only output. In this
case, LINE_OUT will be muted, the Master Volume
Register (Index 02h) will control HP_OUT and
PC_BEEP will be routed to HP_OUT during RE-
SET.

10.2.2

Mono Output

The mono output, MONO_OUT, can be either a sum
of the left and right output channels, attenuated by
6 dB to prevent clipping at full scale, or the selected
Mic signal. The mono out channel can drive the PC
internal mono speaker using an appropriate buffer
circuit.

10.3

Miscellaneous Analog Signals

The AFLT1 and AFLT2 pins must have a 1000 pF
NPO capacitor to analog ground. These capacitors
provide a single-pole low-pass filter at the inputs to
the ADCs. This makes low-pass filters at each analog
input pin unnecessary.

The REFFLT pin must have a short, wide trace to a
2.2

µF and a 0.1 µF capacitor connected to analog

ground (see Figure 26 in Section 11, Grounding and
Layout, for an example). The 2.2

µF capacitor must

not be replaced by any other value (it may be re-
placed with two 1 µF capacitors in parallel) and must
be ceramic with low leakage current. Electrolytic ca-
pacitors should not be used. No other connection
should be made, as any coupling onto this pin will
degrade the analog performance of the CS4202.
Likewise, digital signals should be kept away from
REFFLT for similar reasons.

10.4

Power Supplies

The power supplies providing analog power should
be as clean as possible to minimize coupling into the
analog section which could degrade analog perfor-
mance. The +5 V analog supply should be generated
from a voltage regulator (7805 type) connected to a
+12 V supply. This helps isolate the analog circuitry
from noise typically found on +5 V digital supplies.
A typical voltage regulator circuit for analog power
using an MC78M05CDT is shown in Figure 25. One
analog power pin, AVdd2, supplies power to the
headphone amplifier on the CS4202. The other ana-
log power pin, AVdd1, supplies power to the rest of
the CS4202 analog circuitry. The digital power pins,
DVdd1 and DVdd2, should be connected to the same

HP_OUT_R

HP_OUT_C

HP_OUT_L

220

µ F

ELEC

220

µ F

ELEC

µF

ELEC

10 k

AGND

LINE_OUT_R

LINE_OUT_L

µ F

ELEC

µ F

ELEC

220 k

AGND

Headphone
Jack

Line Out
Jack

HPCFG

1000 pF

AGND

Figure 23. Line Out and Headphone Out Setup

HP_OUT_R

HP_OUT_C

HP_OUT_L

220

µ F

ELEC

220

µ F

ELEC

µF

ELEC

10 k

AGND

LINE_OUT_R

LINE_OUT_L

Line Out/
Headphone
Jack

HPCFG

AGND

Figure 24. Line Out/Headphone Out Setup

CS4202

DS549PP1

11. GROUNDING AND LAYOUT

Figure 26 on page 55 shows the conceptual layout
for the CS4202 in XTAL or OSC clocking modes.
The decoupling capacitors should be located phys-
ically as close to the pins as possible. Also, note the
connection of the REFFLT decoupling capacitors
to the ground return trace connected directly to the
ground return pin, AVss1.

It is strongly recommended that separate analog
and digital ground planes be used. Separate ground
planes keep digital noise and return currents from
modulating the CS4202 ground potential and de-
grading performance. The digital ground pins
should be connected to the digital ground plane and
kept separate from the analog ground connections
of the CS4202 and any other external analog cir-
cuitry. All analog components and traces should be
located over the analog ground plane and all digital
components and traces should be located over the
digital ground plane.

The common connection point between the two
ground planes (required to maintain a common
ground voltage potential) should be located under
the CS4202. The AC-link digital interface connec-

tion traces should be routed such that the digital
ground plane lies underneath these signals (on the
internal ground layer). This applies along the entire
length of these traces from the AC '97 controller to
the CS4202.

Refer to the Application Note AN18: Layout and
Design Rules for Data Converters and Other
Mixed Signal Devices [2] for more information on
layout and design rules.

CS4202

DS549PP1

Audio I/O Pins

PC_BEEP - Analog Mono Source, Input, Pin 12

The PC_BEEP input is intended to allow the PC system POST (Power On Self-Test) tones to pass
through to the audio subsystem. The PC_BEEP input has two connections: the first connection is to the
analog output mixer, the second connection is directly to the LINE_OUT stereo outputs (if HPCFG is
floating) or through the headphone amplifier to the HP_OUT pins (if HPCFG is tied low). While the
RESET# pin is actively being asserted to the CS4202, the PC_BEEP bypass path to the LINE_OUT or
HP_OUT outputs is enabled. While the CS4202 is in normal operation mode with RESET# de-asserted,
PC_BEEP is a monophonic source to the analog output mixer. The maximum allowable input is 1 V

RMS

(sinusoidal). This input is internally biased at the Vrefout voltage reference and requires AC-coupling to
external circuitry. If this input is not used, it should be connected to the Vrefout pin or AC-coupled to
analog ground.

PHONE - Analog Mono Source, Input, Pin 13

This analog input is a monophonic source to the output mixer. It is intended to be used as a modem
subsystem input to the audio subsystem. The maximum allowable input is 1 V

RMS

(sinusoidal). This

input is internally biased at the Vrefout voltage reference and requires AC-coupling to external circuitry.
If this input is not used, it should be connected to the Vrefout pin or AC-coupled to analog ground.

MIC1 - Analog Mono Source, Input, Pin 21

This analog input is a monophonic source to the analog output mixer. It is intended to be used as a
desktop microphone connection to the audio subsystem. The CS4202 internal mixer's microphone input
is MUX selectable with either MIC1 or MIC2 as the input.The maximum allowable input is 1 V

RMS

MIC2 - Analog Mono Source, Input, Pin 22

This analog input is a monophonic source to the analog output mixer. It is intended to be used as an
alternate microphone connection to the audio subsystem. The CS4202 internal mixer's microphone input
is MUX selectable with either MIC1 or MIC2 as the input. The maximum allowable input is 1 V

RMS

LINE_IN_L, LINE_IN_R - Analog Line Source, Inputs, Pins 23 and 24

These inputs form a stereo input pair to the CS4202. The maximum allowable input is 1 V

RMS

(sinusoidal). These inputs are internally biased at the Vrefout voltage reference and require AC-coupling
to external circuitry. If these inputs are not used, they should both be connected to the Vrefout pin or
AC-coupled to analog ground.

CD_L, CD_R - Analog CD Source, Inputs, Pins 18 and 20

These inputs form a stereo input pair to the CS4202. It is intended to be used for the Red Book CD
audio connection to the audio subsystem. The maximum allowable input is 1 V

RMS

(sinusoidal). These

inputs are internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry.
If these inputs are not used, they should both be connected to the Vrefout pin or AC-coupled to analog
ground.

CD_C - Analog CD Common Source, Input, Pin 19

This analog input is used to remove common mode noise from Red Book CD audio signals. The
impedance on the input signal path should be one half the impedance on the CD_L and CD_R input
paths. This pin requires AC-coupling to external circuitry. If this input is not used, it should be connected
to the Vrefout pin or AC-coupled to analog ground.

CS4202

DS549PP1

VIDEO_L, VIDEO_R - Analog Video Audio Source, Inputs, Pins 16 and 17

These inputs form a stereo input pair to the CS4202. It is intended to be used for the audio signal
output of a video device. The maximum allowable input is 1 V

RMS

(sinusoidal). These inputs are

internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. If these
inputs are not used, they should both be connected to the Vrefout pin or AC-coupled to analog ground.

AUX_L, AUX_R - Analog Auxiliary Source, Inputs, Pins 14 and 15

These inputs form a stereo input pair to the CS4202. The maximum allowable input is 1 V

RMS

LINE_OUT_L, LINE_OUT_R - Analog Line-Level, Outputs, Pins 35 and 36

These signals are analog outputs from the stereo output mixer. The full-scale output voltage for each
output is nominally 1 V

RMS

(sinusoidal). These outputs are internally biased at the Vrefout voltage

reference and require either AC-coupling to external circuitry or DC-coupling to a buffer op-amp biased
at the Vrefout voltage. These pins need a 680-1000 pF NPO capacitor attached to analog ground.

HP_OUT_L, HP_OUT_R - Analog Headphone, Outputs, Pins 39 and 41

These signals are analog outputs from the stereo output mixer. The full-scale output voltage for each
output is nominally 4 V

. These outputs are internally biased at the Vrefout voltage reference and

require AC-coupling to external circuitry. The HP_OUT pins can directly drive resistive loads as low as
32

(such as standard consumer headphones). Capacitive loading must not exceed 200 pF per pin.

The outputs are short circuit protected for infinite duration.

HP_OUT_C - Analog Headphone Output Common Source, Input, Pin 40

This analog input is used to remove common mode noise from the headphone outputs. This is achieved
by biasing the headphone amplifier with the common mode noise on the headphone amplifier ground
plane. This pin should be AC-coupled through a 1

µF electrolytic capacitor to analog ground (AVss2)

near the headphone jack.

MONO_OUT - Analog Mono Line-Level, Output, Pin 37

This signal is an analog output from the stereo-to-mono mixer. The full-scale output voltage for this
output is nominally 1 V

RMS

(sinusoidal). This output is internally biased at the Vrefout voltage reference

and requires either AC-coupling to external circuitry or DC-coupling to a buffer op-amp biased at the
Vrefout voltage. This pin needs a 680-1000 pF NPO capacitor attached to analog ground.

Analog Reference, Filter, and Configuration Pins

REFFLT - Internal Reference Voltage, Input, Pin 27

This signal is the voltage reference used internal to the CS4202. A 0.1

µF and a 2.2 µF ceramic

capacitor with short, wide traces must be connected to this pin. No other connections should be made
to this pin. Do not use an electrolytic 2.2

µF capacitor, use a type Z5U or Y5V ceramic capacitor.

Vrefout - Voltage Reference, Output, Pin 28

All analog inputs and outputs are centered around Vrefout, nominally 2.4 Volts. This pin may be used to
bias external amplifiers. It can also drive up to 5 mA of DC which can be used for microphone bias.

CS4202

DS549PP1

AFLT1 - Left ADC Channel Antialiasing Filter, Input, Pin 29

This pin needs a 1000 pF NPO capacitor connected to analog ground.

AFLT2 - Right ADC Channel Antialiasing Filter, Input, Pin 30

This pin needs a 1000 pF NPO capacitor connected to analog ground.

HPCFG - Headphone Configuration, Input, Pin 31

This pin is the configuration control for the signal routing to the headphone amplifier. If this pin is left
floating, the LINE_OUT and HP_OUT pins function as defined in the AC '97 specification. If the HPCFG
pin is grounded, the HP_OUT pins behave as a buffered line output. In addition, the LINE_OUT pins are
muted, the control register for the headphone output will be the Master Output Volume Register (Index
02h), and PC_BEEP is routed to the HP_OUT pins during RESET. The HPCFG pin is internally pulled
up to the analog supply voltage.

AC-Link Pins

RESET# - AC '97 Chip Reset, Input, Pin 11

This active low signal is the asynchronous Cold Reset input to the CS4202. The CS4202 must be reset
before it can enter normal operating mode.

SYNC - AC-Link Serial Port Sync Pulse, Input, Pin 10

SYNC is the serial port timing signal for the AC-link. Its period is the reciprocal of the maximum sample
rate, 48 kHz. The signal is generated by the controller and is synchronous to BIT_CLK. SYNC is an
asynchronous input when the CS4202 is configured as a primary codec and is in a PR4 powerdown
state. A series terminating resistor of 47

should be connected on this signal close to the controller.

BIT_CLK - AC-Link Serial Port Master Clock, Input/Output, Pin 6

This input/output signal controls the master clock timing for the AC-link. In primary mode, this signal is a
12.288 MHz output clock derived from either a 24.576 MHz crystal or from the internal PLL based on
the XTL_IN input clock. When the CS4202 is in secondary mode, this signal is an input which controls
the AC-link serial interface and generates all internal clocking including the AC-link serial interface
timing and the analog sampling clocks. A series terminating resistor of 47

should be connected on

this signal close to the CS4202 in primary mode or close to the BIT_CLK source in secondary mode.

SDATA_OUT - AC-Link Serial Data Input Stream to AC '97, Input, Pin 5

This input signal receives the control information and digital audio output streams. The data is clocked
into the CS4202 on the falling edge of BIT_CLK. A series terminating resistor of 47

should be

connected on this signal close to the controller.

SDATA_IN - AC-Link Serial Data Output Stream from AC '97, Output, Pin 8

This output signal transmits the status information and digital audio input streams from the ADCs. The
data is clocked out of the CS4202 on the rising edge of BIT_CLK. A series terminating resistor of 47

should be connected on this signal close to the CS4202.

CS4202

DS549PP1

Clock and Configuration Pins

XTL_IN - Crystal Input / Clock Input, Pin 2

This pin requires either a 24.576 MHz crystal, with the other pin attached to XTL_OUT, or an external
CMOS clock. XTL_IN must have a crystal or clock source attached for proper operation except when
operating in secondary codec mode. The crystal frequency must be 24.576 MHz and designed for
fundamental mode, parallel resonance operation. If an external CMOS clock is used to drive this pin, it
must run at one of these acceptable frequencies: 14.31818, 24.576, 27, or 48 MHz. When configured as
a secondary codec, all timing is derived from the BIT_CLK input signal and this pin should be left
floating. See Section 9, Clocking, for additional details.

XTL_OUT - Crystal Output / PLL Loop Filter, Pin 3

This pin is used for a crystal placed between this pin and XLT_IN. If an external 24.576 MHz clock is
used on XTL_IN, this pin must be left floating with no traces or components connected to it. If one of
the other acceptable clocks is used on XTL_IN, this pin must be connected to a loop filter circuit. See
Section 9, Clocking, for additional details.

ID1#, ID0# - Codec ID, Inputs, Pins 45 and 46

These pins select the Codec ID for the CS4202, as well as determine the rate of the incoming clock in
PLL mode. They are only sampled after the rising edge of RESET#. These pins are internally pulled up
to the digital supply voltage and should be left floating for logic `0' or tied to digital ground for logic `1'.

Misc. Digital Interface Pins

SPDIF_OUT - Sony/Philips Digital Interface, Output, Pin 48

This pin generates the S/PDIF digital output from the CS4202 when the SPDIF bit in the Extended
Audio Status/Control Register (Index 2Ah) is `set'. This output may be used to directly drive a resistive
divider and coupling transformer to an RCA-type connector for use with consumer audio equipment.
When this function is not being used this output is driven to a logic `0'.

EAPD/SCLK - External Amplifier Powerdown / Serial Clock, Output, Pin 47

This pin is used to control the powerdown state of an audio amplifier external to the CS4202. The
output is controlled by the EAPD bit in the Powerdown Ctrl/Stat Register (Index 26h). It is driven as a
normal CMOS output and defaults low (`0') upon power-up. This pin also provides the serial clock for
both serial data ports when the SDSC bit in the Serial Port Control Register (Index 6Ah) is `set'.

GPIO0/LRCLK - General Purpose I/O / Left-Right Clock, Input/Output, Pin 43

This pin is a general purpose I/O pin that can be used to interface with various external circuitry. When
configured as an input, it functions as a Schmitt triggered input with 350 mV hysteresis at 5 V and
220 mV hysteresis at 3.3 V. When configured as an output, it can function as a normal CMOS output
(4 mA drive) or as an open drain output. This pin also provides the L/R clock for both serial data ports
when the SDEN bit in the Serial Port Control Register (Index 6Ah) is `set'. This pin powers up in the
high impedance state for backward compatibility.

GPIO1/SDOUT - General Purpose I/O / Serial Data Output, Input/Output, Pin 44

This pin is a general purpose I/O pin that can be used to interface with various external circuitry. When
configured as an input, it functions as a Schmitt triggered input with 350 mV hysteresis at 5 V and
220 mV hysteresis at 3.3 V. When configured as an output, it can function as a normal CMOS output
(4 mA drive) or as an open drain output. This pin also provides the serial data for the first serial data
port when the SDEN bit in the Serial Port Control Register (Index 6Ah) is `set'. This pin powers up in
the high impedance state for backward compatibility.

CS4202

DS549PP1

GPIO2 - General Purpose I/O, Input/Output, Pin 32

This pin is a general purpose I/O pin that can be used to interface with various external circuitry. When
configured as an input, it functions as a Schmitt triggered input with 350 mV hysteresis at 5 V and
220 mV hysteresis at 3.3 V. When configured as an output, it can function as a normal CMOS output
(4 mA drive) or as an open drain output. This pin powers up in the high impedance state for backward
compatibility.

GPIO3 - General Purpose I/O, Input/Output, Pin 33

This pin is a general purpose I/O pin that can be used to interface with various external circuitry. When
configured as an input, it functions as a Schmitt triggered input with 350 mV hysteresis at 5 V and
220 mV hysteresis at 3.3 V. When configured as an output, it can function as a normal CMOS output
(4 mA drive) or as an open drain output. This pin powers up in the high impedance state for backward
compatibility.

GPIO4/SDO2 - General Purpose I/O / Serial Data Output 2, Input/Output, Pin 34

This pin is a general purpose I/O pin that can be used to interface with various external circuitry. When
configured as an input, it functions as a Schmitt triggered input with 350 mV hysteresis at 5 V and
220 mV hysteresis at 3.3 V. When configured as an output, it can function as a normal CMOS output
(4 mA drive) or as an open drain output. This pin also provides the serial data for the second serial data
port when the SDO2 bit in the Serial Port Control Register (Index 6Ah) is `set'. This pin powers up in the
high impedance state for backward compatibility.

Power Supply Pins

DVdd1, DVdd2 - Digital Supply Voltage, Pins 1 and 9

Digital supply voltage for the AC-link section of the CS4202. These pins can be tied to +5 V digital or to
+3.3 V digital. The CS4202 and controller's AC-link should share a common digital supply.

DVss1, DVss2 - Digital Ground, Pins 4 and 7

Digital ground connection for the AC-link section of the CS4202. These pins should be isolated from
analog ground currents.

AVdd1, AVdd2 - Analog Supply Voltage, Pins 25 and 38

Analog supply voltage for the analog and mixed signal section of the CS4202 (AVdd1) as well as the
headphone amplifier (AVdd2). These pins must be tied to the analog +5 V power supply. It is strongly
recommended that +5 V be generated from a voltage regulator to ensure proper supply currents and
noise immunity from the rest of the system.

AVss1, AVss2 - Analog Ground, Pins 26 and 42

Ground connection for the analog, mixed signal, and substrate sections of the CS4202 (AVss1) as well
as the headphone amplifier (AVss2). These pins should be isolated from digital ground currents.

CS4202

DS549PP1

13. PARAMETER AND TERM DEFINITIONS

AC '97 Specification

Refers to the Audio Codec '97 Component Specification Ver 2.2 published by the Intel

Corporation [6].

AC '97 Controller or Controller

Refers to the control chip which interfaces to the audio codec AC-link. This has been also called DC '97
for Digital Controller '97 [6].

AC '97 Registers or Codec Registers

Refers to the 64-field register map defined in the AC '97 Specification.

ADC

Refers to a single Analog-to-Digital converter in the CS4202. "ADCs" refers to the stereo pair of
Analog-to-Digital converters. The CS4202 ADCs have 18-bit resolution.

Codec

Refers to the chip containing the ADCs, DACs, and analog mixer. In this data sheet, the codec is the
CS4202.

DAC

Refers to a single Digital-to-Analog converter in the CS4202. "DACs" refers to the stereo pair of
Digital-to-Analog converters. The CS4202 DACs have 20-bit resolution.

dB FS A

dB FS is defined as dB relative to full-scale. The "A" indicates an A weighting filter was used.

Differential Nonlinearity

The worst case deviation from the ideal code width. Units in LSB.

Dynamic Range (DR)

DR is the ratio of the RMS full-scale signal level divided by the RMS sum of the noise floor, in the
presence of a signal, available at any instant in time (no change in gain settings between
measurements). Measured over a 20 Hz to 20 kHz bandwidth with units in dB FS A.

FFT

Fast Fourier Transform.

Frequency Response (FR)

FR is the deviation in signal level verses frequency. The 0 dB reference point is 1 kHz. The amplitude
corner, Ac, lists the maximum deviation in amplitude above and below the 1 kHz reference point. The
listed minimum and maximum frequencies are guaranteed to be within the Ac from minimum frequency
to maximum frequency inclusive.

Sampling Frequency.

Interchannel Gain Mismatch

For the ADCs, the difference in input voltage to get an equal code on both channels. For the DACs, the
difference in output voltages for each channel when both channels are fed the same code. Units are in
dB.

CS4202

DS549PP1

Interchannel Isolation

The amount of 1 kHz signal present on the output of the grounded AC-coupled line input channel with 1
kHz, 0 dB, signal present on the other line input channel. Units are in dB.

Line-level

Refers to a consumer equipment compatible, voltage driven interface. The term implies a low driver
impedance and a minimum 10 k

load impedance.

PATHS

A-D: Analog in, through the ADCs, onto the serial link.

D-A: Serial interface inputs through the DACs to the analog output.

A-A: Analog in to Analog out (analog mixer).

PC 99

Refers to the PC 99 System Design Guide published by the Microsoft

Corporation [7].

PC 2001

Refers to the PC 2001 System Design Guide published by the Microsoft

Corporation [8].

PLL

Phase Lock Loop. Circuitry for generating a desired clock from an external clock source.

Resolution

The number of bits in the output words to the DACs, and in the input words to the ADCs.

Signal to Noise Ratio (SNR)

SNR, similar to DR, is the ratio of an arbitrary sinusoidal input signal to the RMS sum of the noise floor,
in the presence of a signal. It is measured over a 20 Hz to 20 kHz bandwidth with units in dB.

S/PDIF

Sony/Phillips Digital Interface. This interface was established as a means of digitally interconnecting
consumer audio equipment. The documentation for S/PDIF has been superseded by the IEC-958
consumer digital interface document.

SRC

Sample Rate Converter. Converts data derived at one sample rate to a differing sample rate. The
CS4202 operates at a fixed sample frequency of 48 kHz. The internal sample rate converters are used
to convert digital audio streams playing back at other frequencies to 48 kHz.

Total Harmonic Distortion plus Noise (THD+N)

THD+N is the ratio of the RMS sum of all non-fundamental frequency components, divided by the RMS
full-scale signal level. It is tested using a -3 dB FS input signal and is measured over a 20 Hz to 20 kHz
bandwidth with units in dB FS.

CS4202

DS549PP1

14. REFERENCE DESIGN

R18

C23

R14

.
8

C31

22pF

C22

1uF

C32

22pF

.
8

220K

2uF

10uF

24.

100K

1uF

10uF

ND_

I
E

050

i
n

100K

1uF

10K

.
8

2700pF

1uF

220uF

4202

dd2

I
O

/
S

ss2

I
O

/
S

GPIO

I
O

dd1

L_IN

L_OU

ss1

ss2

I
N

SYN

dd2

ESET

BEEP

CD_

dd1

ss1

r
ef

out

SPD

I
F

EAPD

/
S

ID1

ID0

1uF

47K

1uF

100K

1uF

220uF

1uF

CDT

GND

1000pF

1uF

.
8

1000pF

1uF

.
2

1000pF

1uF

10uF

220K

1uF

.
1

ESET

SYN

SEN

.
3

BEEP

I
N

EAD

S/PD

i
e

one

poi

onl

under

t
he

odec

(
5

PPM

)

I
N

udi

ont

r
o

l
l
e

I
C

ont

r
o

l
l
e

I
N

hannel

onf

i
gur

i
o

I
O

(
pi

33)

i
s

2uF

apac

i
t
o

r
epl

t
w

1uF

apac

i
t
or

i
gu

28.

202

e
n

e
s
ign

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CS4202

Document Outline

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Document Outline

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