Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 1999
(All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CS4227
Six Channel, 20-Bit Codec
Features
l
Stereo 20-bit A/D Converters
l
Six 20-bit D/A Converters
l
108 dB DAC Signal-to-Noise Ratio (EIAJ)
l
Mono 20-bit A/D Converter
l
Programmable Input Gain & Output
Attenuation
l
On-chip Anti-aliasing and Output Smoothing
Filters
l
De-emphasis for 32 kHz, 44.1 kHz, 48 kHz
Description
The CS4227 is a single-chip codec providing stereo an-
alog-to-digital and six digital-to-analog converters using
delta-sigma conversion techniques. This +5 V device
also contains volume controls that are independently se-
lectable for each of the six D/A channels. Applications
include Dolby
Pro-logicTM, THX
, and Dolby Digital AC-
3TM home theater systems, DSP based car audio sys-
tems, and other multi-channel applications.
ORDERING INFORMATION
CS4227-KQ
-10 to +70 C 44-pin TQFP
CS4227-BQ
-40 to +85 C 44-pin TQFP
CDB4227
Evaluation Board
I
SCL/CCLK
DEM
SDA/CDOUT
VD+
AOUT1
LRCK
SCLK
SDIN1
SDOUT1
Se
ri
al
Au
di
o
Data I
n
terfa
c
e
Control Port
D
i
g
i
t
a
l F
ilt
e
r
s
DAC#1
Right
ADC
Left
ADC
Volume
Control
Anal
og L
o
w Pas
s
and
Output Stag
e
VA+
AOUT2
AIN1L
AIN1R
SDIN2
SDOUT2
OVL
DAC#4
DAC#2
DAC#3
DEM
MUX
Clock Osc/
Divider
CLKOUT XTI
XTO
Volume
Control
Volume
Control
Volume
Control
LRCKAUX
SCLKAUX
DGND1
DGND2
Auxiliary Input
Input
Gain
AOUT3
AOUT4
Voltage
Reference
AIN2L
AIN2R
AIN3L
AIN3R
Inp
u
t MUX
AGND2
SDIN3
PDN
AD1/CDIN AD0/CS SPI/I
2
C
CMOUT
DAC#6
DAC#5
Volume
Control
Volume
Control
AOUT5
AOUT6
Mono
ADC
AINAUX
AGND1
DATAUX
HOLD
Di
g
i
t
a
l F
i
lt
e
r
s
SEP `99
DS281PP2
CS4227
2
DS281PP2
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
ANALOG CHARACTERISTICS ................................................................................................ 4
SWITCHING CHARACTERISTICS .......................................................................................... 6
SWITCHING CHARACTERISTICS - CONTROL PORT........................................................... 8
ABSOLUTE MAXIMUM RATINGS ......................................................................................... 10
RECOMMENDED OPERATING CONDITIONS ..................................................................... 10
DIGITAL CHARACTERISTICS ............................................................................................... 10
2. FUNCTIONAL DESCRIPTION ............................................................................................... 12
2.1 Overview .......................................................................................................................... 12
2.2 Analog Inputs ................................................................................................................... 12
2.2.1 Line Level Inputs ................................................................................................. 12
2.2.2 Adjustable Input Gain .......................................................................................... 13
2.2.3 High Pass Filter ................................................................................................... 13
2.3 Analog Outputs ................................................................................................................ 13
2.3.1 Line Level Outputs .............................................................................................. 13
2.3.2 Output Level Attenuator ...................................................................................... 14
2.4 Clock Generation ............................................................................................................. 14
2.4.1 Clock Source ....................................................................................................... 14
2.4.2 Master Clock Output ........................................................................................... 14
2.4.3 Synchronization ................................................................................................... 14
2.5 Digital Interfaces .............................................................................................................. 15
2.5.1 Audio DSP Serial Interface Signals ..................................................................... 15
2.5.2 Audio DSP Serial Interface Formats ................................................................... 15
2.5.3 Auxiliary Audio Port Signals ................................................................................ 15
2.5.4 Auxiliary Audio Port Formats ............................................................................... 15
2.6 Control Port Signals ......................................................................................................... 17
2.6.1 SPI Mode ............................................................................................................ 17
2.6.2 I
2
C
Mode ........................................................................................................... 18
2.6.3 Control Port Bit Definitions .................................................................................. 18
2.7 Power-up/Reset/Power Down Mode ................................................................................ 18
2.8 DAC Calibration ............................................................................................................... 19
2.9 De-Emphasis ................................................................................................................... 19
2.10 Hold Function ................................................................................................................. 19
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Dolby is a registered trademark of Dolby Labratories Licensing Corporation.
Pro Logic, and AC-3 are trademarks of Dolby Labratories Licensing Corporation.
THX is a registered trademark of LucasArts Entertainment Company.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.
CS4227
DS281PP2
3
2.11 Power Supply, Layout, and Grounding .......................................................................... 19
2.12 ADC and DAC Filter Response Plots ............................................................................ 20
3. PIN DESCRIPTIONS .............................................................................................................. 29
4. PARAMETER DEFINITIONS .................................................................................................. 33
5. PACKAGE DIMENSIONS ...................................................................................................... 34
LIST OF FIGURES
Figure 1. Audio Ports Master Mode Timing..................................................................................... 7
Figure 2. Audio Ports Slave Mode and Data I/O Timing ................................................................. 7
Figure 3. Control Port SPI Mode ..................................................................................................... 8
Figure 4. Control Port I
2
C Mode...................................................................................................... 9
Figure 5. Recommended Connection Diagram............................................................................. 11
Figure 6. Optional Line Intput Buffer ............................................................................................. 12
Figure 7. Butterworth Filters.......................................................................................................... 13
Figure 8. Audio DSP and Auxiliary Port Data Input Formats ........................................................ 16
Figure 9. Audio DSP Port Data Output Formats ........................................................................... 16
Figure 10. One Data Line Modes .................................................................................................. 16
Figure 11. Control Port Timing, SPI Mode .................................................................................... 17
Figure 12. Control Port Timing, I
2
C
Mode................................................................................... 18
Figure 13. De-emphasis Curve. .................................................................................................... 19
Figure 14. Suggested Layout Guideline........................................................................................ 20
Figure 15. 20-bit ADC Filter Response ......................................................................................... 21
Figure 16. 20-bit ADC Passband Ripple ....................................................................................... 21
Figure 17. 20-bit ADC Transition Band ......................................................................................... 21
Figure 18. DAC Frequency Response .......................................................................................... 21
Figure 19. DAC Passband Ripple ................................................................................................. 21
Figure 20. DAC Transition Band ................................................................................................... 21
LIST OF TABLES
Table 1. Single-ended vs Differential Input Pin Assignments .............................................................. 12
Table 2. High Pass Filter Characteristics ............................................................................................ 13
Table 3. DSP Serial Input Ports........................................................................................................... 15
CS4227
4
DS281PP2
1.
CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS
(T
A
= 25 C; VA+, VD+ = +5 V; Full Scale Input Sine wave, 997 kHz;
Fs = 44.1 kHz; Measurement Bandwidth is 20 Hz to 20 kHz; Local components as shown in Figure 5; SPI mode,
Format 3, unless otherwise specified.)
Notes: 1. Referenced to typical full-scale differential input voltage (2Vrms).
2. Input resistance is for the input selected. Non-selected inputs have a very high (>1M
) input resistance.
The input resistance will vary with gain value selected, but will always be greater than the min. value
specified.
3. Filter characteristics scale with output sample rate.
4. The analog modulator samples the input at 5.6448 MHz for an output sample rate of 44.1 kHz. There is
no rejection of input signals which are multiples of the sampling frequency (n x 5.6448 MHz 20.0 kHz
where n = 0,1,2,3...).
5. Group delay for Fs = 44.1 kHz, t
gd
= 15/44.1 kHz = 340 s
Parameter
Symbol
CS4227-KQ
CS4227-BQ
Units
Min
Typ
Max
Min
Typ
Max
Analog Input Characteristics
- Minimum gain setting (0 dB) Differential Input; unless otherwise specified.
ADC Resolution
Stereo Audio channels
Mono channel
16
16
-
-
20
20
16
16
-
-
20
20
Bits
Bits
Total Harmonic Distortion
THD
0.003
-
0.003
-
%
Dynamic Range
(A weighted, Stereo)
(unweighted, Stereo)
(A weighted, Mono)
92
-
89
95
92
-
-
-
-
90
-
87
93
90
-
-
-
-
dB
dB
dB
Total Harmonic
-1 dB, Stereo
(Note 1)
Distortion + Noise -1 dB, Mono
(Note 1)
THD+N
-
-
-88
-
-82
-72
-
-
-86
-
-80
-70
dB
dB
Interchannel Isolation
-
90
-
-
90
-
dB
Interchannel Gain Mismatch
-
0.1
-
-
0.1
-
dB
Programmable Input Gain Span
8
9
10
8
9
10
dB
Gain Step Size
2.7
3
3.3
2.7
3
3.3
dB
Offset Error (with high pass filter)
-
-
0
-
-
0
LSB
Full Scale Input Voltage (Single Ended):
0.90
1.0
1.10
0.90
1.0
1.10
Vrms
Gain Drift
-
100
-
-
100
-
ppm/C
Input Resistance
(Note 2)
10
-
-
10
-
-
k
Input Capacitance
-
-
15
-
-
15
pF
CMOUT Output Voltage
-
2.3
-
-
2.3
-
V
A/D Decimation Filter Characteristics
Passband
(Note 3)
0.02
-
20.0
0.02
-
20.0
kHz
Passband Ripple
-
-
0.01
-
-
0.01
dB
Stopband
(Note 3)
27.56
-
5617.2 27.56
-
5617.2
kHz
Stopband Attenuation
(Note 4)
80
-
-
80
-
-
dB
Group Delay (Fs = Output Sample Rate) (Note 5)
t
gd
-
15/Fs
-
-
15/Fs
-
s
Group Delay Variation vs. Frequency
t
gd
-
-
0
-
-
0
s
CS4227
DS281PP2
5
ANALOG CHARACTERISTICS
(Continued)
Notes: 6. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 44.1 kHz,
the 0.05 dB passband edge is 0.4535xFs and the stopband edge is 0.5465xFs.
7. Digital filter characteristics.
8. Measurement bandwidth is 10 Hz to 3Fs.
Specifications are subject to change without notice
Parameter
Symbol
CS4227-KQ
CS4227-BQ
Units
Min
Typ
Max
Min
Typ
Max
High Pass Filter Characteristics
Frequency Response:
-3 dB
(Note 3)
-0.13 dB
-
-
3.4
20
-
-
-
-
3.4
20
-
-
Hz
Hz
Phase Deviation
@ 20 Hz
(Note 3)
-
10
-
-
10
-
Deg.
Passband Ripple
-
-
0
-
-
0
dB
Analog Output Characteristics
- Minimum Attenuation, 10 k, 100 pF load; unless otherwise specified.
DAC Resolution
16
-
20
16
-
20
Bits
Signal-to-Noise/Idle
(DAC muted, A weighted)
Channel Noise
101
108
-
99
106
-
dB
Dynamic Range
(DAC not muted, A weighted)
(DAC not muted, unweighted)
93
-
98
95
-
-
91
-
96
93
-
-
dB
dB
Total Harmonic Distortion
THD
-
0.003
-
-
0.003
-
%
Total Harmonic Distortion + Noise
(Stereo) THD+N
-
-88
-83
-
-86
-81
dB
Interchannel Isolation
-
90
-
-
90
-
dB
Interchannel Gain Mismatch
-
0.1
-
-
0.1
-
dB
Attenuation Step Size
(All Outputs)
0.7
1
1.3
0.7
1
1.3
dB
Programmable Output Attenuation Span
-84
-86
-
-84
-86
-
dB
Offset Voltage
(relative to CMOUT)
-
15
-
-
15
-
mV
Full Scale Output Voltage
0.92
1.0
1.08
0.92
1.0
1.08
Vrms
Gain Drift
-
100
-
-
100
-
ppm/C
Out-of-Band Energy
(Fs/2 to 2Fs)
-
-60
-
-
-60
-
dBFs
Analog Output Load
Resistance:
Capacitance:
10
-
-
-
-
100
10
-
-
-
-
100
k
pF
Combined Digital and Analog Filter Characteristics
Frequency Response
10 Hz to 20 kHz
-
0.1
-
-
0.1
-
dB
Deviation from Linear Phase
-
0.5
-
-
0.5
-
Deg.
Passband: to 0.01 dB corner
(Notes 6, 7)
0
-
20.0
0
-
20.0
kHz
Passband Ripple
(Note 7)
-
-
0.01
-
-
0.01
dB
Stopband
(Notes 6 ,7)
24.1
-
-
24.1
-
-
kHz
Stopband Attenuation
(Note 8)
70
-
-
70
-
-
dB
Group Delay (Fs = Input Word Rate)
(Note 5)
tgd
-
16/Fs
-
-
16/Fs
-
s
Analog Loopback Performance
Signal-to-noise Ratio (CCIR-2K weighted, -20 dB input) CCIR-2K
-
71
-
-
71
-
dB
Power Supply
Power Supply Current
Operating
Power Down
-
-
90
1
113
3
-
-
90
1
115
3
mA
mA
Power Supply Rejection
(1 kHz, 10 mV
rms
)
-
45
-
-
45
-
dB
CS4227
6
DS281PP2
SWITCHING CHARACTERISTICS
(T
A
= 25 C; VA+, VD+ = +5 V 5%; outputs loaded with 30 pF.)
Notes: 9. CLKOUT Jitter is for 256x Fs selected as output frequency measured from falling edge to falling edge.
Jitter is greater for 384x Fs and 512x Fs as selected output frequency.
10. For CLKOUT frequency equal to 1x Fs, 384x Fs, and 512x Fs. See Master Clock Output section.
11. After powering up the CS4227, PDN should be held low for 1 ms to allow the power supply to settle.
12.
13.
14.
Parameter
Symbol Min Typ
Max
Unit
Audio ADC's and DAC's Sample Rate
Fs
4
-
50
kHz
XTI Frequency
XTI = 256, 384, or 512 Fs
1.024
-
26
MHz
XTI Pulse Width High
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
10
21
31
-
-
-
-
-
-
ns
XTI Pulse Width Low
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
10
21
31
-
-
-
-
-
-
ns
XTI Jitter Tolerance
-
500
-
ps
CLKOUT Jitter
(Note 9)
-
200
-
psRMS
CLKOUT Duty Cycle (high timer/cycle time)
(Note 10)
40
50
60
%
PDN Low Time
(Note 11)
500
-
-
ns
SCLK Falling Edge to SDOUT Output Valid
DSCK = 0
t
dpd
-
-
Note 12
ns
LRCK edge to MSB valid
t
lrpd
-
-
40
ns
SDIN Setup Time Before SCLK Rising Edge
DSCK = 0
t
ds
-
-
25
ns
SDIN Hold Time After SCLK Rising Edge
DSCK = 0
t
dh
-
-
25
ns
Master Mode
SCLK Falling to LRCK Edge
DSCK = 0
t
mslr
-
10
-
ns
SCLK Period
(Note 14)
-
-
-
-
-
SCLK Duty Cycle
-
50
-
%
Slave Mode
SCLK Period
t
sckw
Note 13
-
-
ns
SCLK High Time
t
sckh
40
-
-
ns
SCLK Low Time
t
sckl
40
-
-
ns
SCLK Rising to LRCK Edge
DSCK = 0
t
lrckd
20
-
-
ns
LRCK Edge to SCLK Rising
DSCK = 0
t
lrcks
40
-
-
ns
1
384
(
)
Fs
---------------------
20
+
1
128
(
)
Fs
---------------------
1
256
(
)
Fs
-------------------
CS4227
DS281PP2
7
t
mslr
SCLK*
SCLKAUX*
(output)
LRCK
LRCKAUX
(output)
SDOUT1
SDOUT2
sckh
sckl
sckw
t
t
t
MSB
MSB-1
*SCLK, SCLKAUX shown for DSCK = 0 and ASCK = 0.
SCLK & SCLKAUX inverted for DSCK = 1 and ASCK = 1, respectively.
tdpd
SDOUT1
SDOUT2
LRCKAUX
(input)
LRCK
SCLK*
SCLKAUX*
(input)
SDIN1
SDIN2
DATAUX
dh
t
ds
t
lrpd
t
lrcks
t
lrckd
t
SDIN3
Figure 1. Audio Ports Master Mode Timing
Figure 2. Audio Ports Slave Mode and Data I/O Timing
CS4227
8
DS281PP2
SWITCHING CHARACTERISTICS - CONTROL PORT
(T
A
= 25 C; VA+, VD+ = +5 V 5%;
Inputs: logic 0 = DGND, logic 1 = VD+; C
L
= 30 pF)
Notes: 15. Data must be held for sufficient time to bridge the transition time of CCLK.
16. For F
SCK
< 1 MHz.
Parameter
Symbol
Min
Max
Unit
SPI Mode (SPI/I2C = 0)
CCLK Clock Frequency
f
sck
-
6
MHz
CS High Time Between Transmissions
t
csh
1.0
-
s
CS Falling to CCLK Edge
t
css
20
-
ns
CCLK Low Time
t
scl
66
-
ns
CCLK High Time
t
sch
66
-
ns
CDIN to CCL Rising Setup Time
t
dsu
40
-
ns
CCLK Rising to DATA Hold Time
(Note 15)
t
dh
15
-
ns
CCLK Falling to CDOUT stable
t
pd
-
45
ns
Rise Time of CDOUT
t
r1
-
25
ns
Fall Time of CDOUT
t
f1
-
25
ns
Rise Time of CCLK and CDIN
(Note 16)
t
r2
-
100
ns
Fall Time of CCLK and CDIN
(Note 16)
t
f2
-
100
ns
t r2
t f2
t dsu t dh
t sch
t scl
CS
CCLK
CDIN
t css
t pd
CDOUT
t csh
Figure 3. Control Port SPI Mode
CS4227
DS281PP2
9
SWITCHING CHARACTERISTICS - CONTROL PORT
(T
A
= 25 C; VA+, VD+ = +5 V 5%;
Inputs: logic 0 = DGND, logic 1 = VD+; C
L
= 30 pF)
Notes: 17. I
2
C
is a registered trademark of Philips Semiconductors.
18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Parameter
Symbol
Min
Max
Unit
I
2
C
Mode (SPI/I2C = 1)
(Note 17)
SCL Clock Frequency
f
scl
-
100
kHz
Bus Free Time Between Transmissions
t
buf
4.7
-
s
Start Condition Hold Time (prior to first clock pulse)
t
hdst
4.0
-
s
Clock Low Time
t
low
4.7
-
s
Clock High Time
t
high
4.0
-
s
Setup Time for Repeated Start Condition
t
sust
4.7
-
s
SDA Hold Time for SCL Falling
(Note 18)
t
hdd
0
-
s
SDA Setup Time to SCL Rising
t
sud
250
-
ns
Rise Time of Both SDA and SCL Lines
t
r
-
1
s
Fall Time of Both SDA and SCL Lines
t
f
-
300
ns
Setup Time for Stop Condition
t
susp
4.7
-
s
t
buf
t
hdst
t
hdst
t
low
t r
t f
t
hdd
t
high
t sud
t sust
t susp
Stop
Start
Start
Stop
Repeated
SDA
SCL
Figure 4. Control Port I
2
C Mode
CS4227
10
DS281PP2
ABSOLUTE MAXIMUM RATINGS
(AGND, DGND = 0 V, all voltage with respect to 0 V.)
Notes: 19. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause
SCR latch-up.
20. The maximum over or under voltage is limited by the input current.
WARNING: WARNING:Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND = 0 V, all voltage with respect to
0 V.)
DIGITAL CHARACTERISTICS
(T
A
= 25 C; VA+, VD+ = +5 V 5%)
Parameter
Symbol
Min
Max
Unit
Power Supplies
Digital
Analog
VD+
VA+
-0.3
-0.3
6.0
6.0
V
Input Current
(Note 19)
-
10
mA
Analog Input Voltage
(Note 20)
-0.7
(VA+) + 0.7
V
Digital Input Voltage
(Note 20)
-0.7
(VD+) + 0.7
V
Ambient Temperature
(Power Applied)
-55
+125
C
Storage Temperature
-65
+150
C
Parameter
Symbol Min Typ
Max
Unit
Power Supplies
Digital
|VA+ - VD+| < 0.4 V
Analog
VD+
VA+
4.75
4.75
5.0
5.0
5.25
5.25
V
Operating Ambient Temperature
T
A
-10
25
70
C
Parameter
Symbol
Min
Max
Unit
High-level Input Voltage
(Except XTI)
V
IH
2.8
(VD+) + 0.3
V
Low-level Input Voltage
(Except XTI)
V
IL
-0.3
0.8
V
High-level Output Voltage
(Except XTO)
V
OH
(VD+) - 1.0
-
V
Low-level Output Voltage
(Except XTO)
V
OL
-
0.4
V
Input Leakage Current
(Digital Inputs)
-
10
A
Output Leakage Current
(High-Impedance Digital Outputs)
-
10
A
CS4227
DS281PP2
11
+5V
Supply
Ferrite Bead
+ 1
F
0.1
F
19
2.0
+ 1
F
0.1
F
40
VA+
VD+
AGND1, 2 DGND1, 2
NC
XTO
XTI
17
C1**
C2**
29
28
External
Clock Input
39
41
20
18
21
* Optional if analog inputs biased
to within 1% of CMOUT
AOUT1
22
AOUT2
23
AOUT3
24
AOUT4
25
AOUT5
26
AOUT6
3
4
6
5
Microcontroller
SCL/CCLK
SDA/CDOUT
AD0/CS
AD1/CDIN
34
33
32
36
Audio
DSP
SDIN1
SDIN2
SDIN3
SDOUT1
35
37
38
31
30
SDOUT2
LRCK
SCLK
CLKOUT
OVL
R
S
R
S
16
15
10
F
1
F
CMOUT
14
10
F
To Optional
Input and
Output Buffers
AIN1L
13
10
F
AIN1R
11
10
F
AIN2L
12
10
F
AIN2R
10
10
F
AIN3L
9
10
F
AIN3R
1
44
43
DATAUX
LRCKAUX
SCLKAUX
R
S
R
S
AINAUX
Digital
Audio
Source
8
PDN
7
SPI/I2C
Mode
Setting
All unused digital inputs
should be tied to 0V.
Unused analog inputs
should be left unconnected.
CS4227
2
HOLD
27
DEM
ANALOG
FILTER
ANALOG
FILTER
ANALOG
FILTER
ANALOG
FILTER
ANALOG
FILTER
ANALOG
FILTER
*
*
*
*
*
*
*
F
r
om
O
p
t
i
o
n
a
l
In
put
B
u
f
f
er
+
R = 50
S
Figure 5. Recommended Connection Diagram
(Also see recommended layout diagrams, Figure 14)
CS4227
12
DS281PP2
2. FUNCTIONAL DESCRIPTION
2.1
Overview
The CS4227 has 2 channels of 20-bit analog-to-
digital conversion and 6 channels of 20-bit digital-
to-analog conversion. A mono 20-bit ADC is also
provided. All ADCs and DACs are delta-sigma
converters. The stereo ADC inputs have adjustable
input gain, while the DAC outputs have adjustable
output attenuation.
Digital audio data received by the DACs and trans-
mitted from the ADCs is communicated over sepa-
rate serial ports, allowing concurrent writing to and
reading from the device. The CS4227 functions are
controlled via a serial microcontroller interface.
Figure 1 shows the recommended connection dia-
gram for the CS4227.
2.2
Analog Inputs
2.2.1
Line Level Inputs
AIN1R, AIN1L, AIN2R, AIN2L, AIN3R, AIN3L
and AINAUX are the line level input pins (See Fig-
ure 5). These pins are internally biased to the
CMOUT voltage (nominally 2.3 V). A 10 F DC
blocking capacitor allows signals centered around
0 V to be input. Figure 6 shows an optional dual op
amp buffer which combines level shifting with a
gain of 0.5 to attenuate the standard line level of
2 V
rms
to 1 V
rms
. The CMOUT reference level is
used to bias the op-amps to approximately one half
the supply voltage. With this input circuit, the
10 F DC blocking caps in Figure 5 may be omit-
ted. Any remaining DC offset will be removed by
the internal high-pass filters.
Selection of the stereo input pair for the 20-bit
ADC's is accomplished by setting the AIS1/0 bits,
which are accessible in the ADC Control Byte. On-
chip anti-aliasing filters follow the input mux, pro-
viding anti-aliasing for all input channels.
The analog inputs may also be configured as differ-
ential inputs. This is enabled by setting bits
AIS1/0 = 3. In the differential configuration, the
left channel inputs reside on pins 10 and 11, and the
right channel inputs reside on pins 12 and 13 as de-
scribed in the table below. In differential mode, the
full scale input level is 2 V
rms
.
Table 1. Single-ended vs Differential Input Pin
Assignments
The analog signal is input to the mono ADC via the
AINAUX pin.
Independent Muting of both the stereo ADC's and
the mono ADC is possible through the ADC Con-
trol Byte (#11) with the MUTR, MUTL and
MUTM bits.
Single-ended
Pin #
Differential Inputs
AIN3L
Pin 10
AINL+
AIN3R
Pin 9
unused
AIN2L
Pin 11
AINL-
AIN2R
Pin 12
AINR-
AIN1L
Pin 14
unused
AIN1R
Pin 13
AINR+
+
-
100 pF
10 k
20 k
+
-
10 k
100 pF
5 k
20 k
Line In
Right
Line In
Left
CMOUT
AINxR
AINxL
0.47
F
3.3
F
3.3
F
Example
Op-Amps are
MC34074 or
MC33078
Figure 6. Optional Line Intput Buffer
CS4227
DS281PP2
13
2.2.2
Adjustable Input Gain
The signals from the line inputs are routed to a pro-
grammable gain circuit which provides up to 9 dB
of gain in 3 dB steps, adjustable through the Input
Control Byte. Right and left channel gain settings
are controlled independently with the GNR1/0 and
GNL1/0 bits. To minimize audible artifacts, level
changes should be done with the channel muted, as
the changes occur immediately on register updates.
The ADC Status Report Byte provides feedback of
input level for each ADC channel. This register
continously monitors the ADC output and records
the peak output level since the last register read.
Reading this register causes it to reset to 0, where-
upon peak monitoring begins again.
2.2.3
High Pass Filter
The operational amplifiers in the input circuitry
driving the CS4227 may generate a small DC offset
into the A/D converter. The CS4227 includes a
high pass filter after the decimator to remove any
DC offset which could result in recording a DC lev-
el, possibly yielding "clicks" when switching be-
tween devices in a multichannel system.
The characteristics of this first-order high pass fil-
ter are outlined below for an output sample rate of
44.1 kHz. This filter response scales linearly with
sample rate.
Table 2. High Pass Filter Characteristics
2.3
Analog Outputs
2.3.1
Line Level Outputs
The CS4227 contains an on-chip buffer amplifier
producing single-ended outputs capable of driving
10 k
loads. Each output (AOUT 1-6) will produce
a nominal 2.83 V
pp
(1 V
rms
) output with a 2.3 volt
quiescent voltage for a full scale digital input. The
recommended off-chip analog filter is a 2nd order
Butterworth with a -3 dB corner at Fs (see
Figure 7). This filter provides out-of-band noise at-
tenuation along with a gain of 2, providing a 2 V
rms
output signal. A 3rd order Butterworth filter with a
-3 dB corner at 0.75 Fs can be used if greater out of
band noise filtering is desired. The CS4227 DAC
interpolation filter is a linear phase design which
has been pre-compensated for an external 2nd or-
der Butterworth filter to provide a flat frequency re-
sponse and linear phase response over the
passband. If this filter is not used, small frequency
response magnitude and phase errors will occur.
Frequency Response
-3dB @ 3.4 Hz
-0.13 dB @ 20 Hz
Phase Deviation
10 degrees @ 20 Hz
Passband Ripple
None
_
22 k
150pF
3.9 k
11 k
1000pF
+
C
MOUT
5 k
0.47
F
Example
Op-Amps
are
MC33078
_
5.85 k
560 pF
1.21 k
1.1 k
5600 pF
+
C
MOUT
5 k
0.47
F
A
OUT
4.75 k
5600 pF
2-Pole Butterworth Filter
3-Pole Butterworth Filter
Figure 7. Butterworth Filters
CS4227
14
DS281PP2
2.3.2
Output Level Attenuator
The DAC outputs are each routed through an atten-
uator which is adjustable in 1 dB steps. Output at-
tenuation is available through the Output
Attenuator Data Bytes. Level changes are imple-
mented such that the noise is attenuated by the
same amount as the signal (equivalent to using an
analog attenuator after the signal source) until the
residual output noise is equal to the noise floor in
the mute state. Level changes only take effect on
zero crossings to minimize audible artifacts. If
there is no zero crossing, then the requested level
change will occur after a time-out period between
512 and 1024 frames (11.6 ms to 23.2 ms at
44.1 kHz frame rate). There is a separate zero
crossing detector for each channel. Each ACC bit
in the DAC Status Report Byte provides informa-
tion on when a volume control change has taken ef-
fect. This bit goes high when a new setting is
loaded and returns low when it has taken effect.
Volume control changes can be instantaneous by
setting the Zero Crossing Disable (ZCD) bit in the
DAC Control Byte (#3) to 1.
Each output can be independently muted via mute
control bits, MUT6-1, in the DAC Control Byte
(#3). The mute also takes effect on a zero-crossing
or after a timeout. In addition, the CS4227 has an
optional mute on consecutive zeros feature, where
all DAC outputs will mute if they receive between
512 and 1024 consecutive zeros (or -1 code) on all
six channels. A single non-zero value will unmute
the DAC outputs. This feature can be disabled with
the MUTC bit in the DAC Control Byte (#3).
2.4
Clock Generation
The master clock to operate the CS4227 may be
generated by using the on-chip inverter and an ex-
ternal crystal or by using an external clock source.
If the active clock source stops for 10 s, the
CS4227 will enter a power down state. In all modes
it is required to have SCLK and LRCK synchro-
nous to the selected master clock.
2.4.1
Clock Source
The CS4227 requires a high frequency master
clock to run the internal logic. The clock enable bit
(CE) must be set to 0 after power-up of the device
(see Power-up/Reset/Power Down Mode section).
A high frequency crystal can be connected to XTI
and XTO, or a high frequency clock can be applied
to XTI. This high frequency clock can be 256 Fs,
384 Fs or 512 Fs; this is set by the CI0/1 bits in the
Clock Mode Byte (#1). When using the on-chip
crystal oscillator, external loading capacitors are
required (see Figure 5). High frequency crystals
(>8 MHz) should be parallel resonant, fundamental
mode and designed for 20 pF loading (equivalent to
40 pF to ground on each leg).
2.4.2
Master Clock Output
CLKOUT is a master clock output provided to al-
low synchronization of external components.
Available CLKOUT frequencies of 1 Fs, 256 Fs,
384 Fs, and 512 Fs, are selectable by the CO0/1 bits
of the Clock Mode Byte.
Generation of CLKOUT for 384 Fs and 512 Fs is
accomplished with an on chip clock multiplier and
may contain clock jitter. The source of the 256 Fs
CLKOUT is a divided down clock from the
XTI/XTO input. If 384 Fs is chosen as the input
clock at XTI and 256 Fs is chosen as the output,
CLKOUT will have approximately a 33% duty cy-
cle. In all other cases CLKOUT will typically have
a 50% duty cycle.
2.4.3
Synchronization
The DSP port and Auxiliary port must operate syn-
chronously to the CS4227 clock source. The serial
port will force a reset of the data paths in an attempt
to resynchronize if non-synchronous data is input
to the CS4227. It is advisable to mute the DACs
when changing from one clock source to another to
avoid the output of undesirable audio signals as the
CS4227 resynchronizes.
CS4227
DS281PP2
15
2.5
Digital Interfaces
There are 2 digital audio interface ports: the audio
DSP port and the auxiliary digital audio port. The
serial data is represented in 2's complement format
with the MSB-first in all formats.
2.5.1
Audio DSP Serial Interface Signals
The serial interface clock, SCLK, is used for trans-
mitting and receiving audio data. The active edge
of SCLK is chosen by setting the DSCK bit in the
DSP Port Mode Byte (#14). SCLK can be generat-
ed by the CS4227 (master mode) or it can be input
from an external SCLK source (slave mode). Mode
selection is set with the DMS1/0 bits in the DSP
Port Mode Byte (#14). The number of SCLK cy-
cles in one system sample period is programmable
to be 32, 48, 64, or 128 by setting the DCK1/0 bits
in the DSP Port Mode Byte (#14). When SCLK is
an input, 64 SCLK's per system sample period is
not recommended, due to potential interference ef-
fects; if possible 128 SCLK's per sample period
should be used instead. For master mode, bursting
of a 128 Fs clock is preferrable over evenly distrib-
uted clocks.
The Left/Right clock (LRCK) is used to indicate
left and right data and the start of a new sample pe-
riod. It may be output from the CS4227, or it may
be generated from an external controller. The fre-
quency of LRCK must be equal to the system sam-
ple rate, Fs.
SDIN1, SDIN2, and SDIN3 are the data input pins,
each of which drives a pair of DACs. SDOUT1 and
SDOUT2 can carry the output data from the two
20-bit ADC's, the mono ADC and the auxiliary dig-
ital audio port. Selection depends on the IS1/0 bits
in the ADC control byte (#11). The audio DSP port
may also be configured so that all 6 DAC's data is
input on SDIN1, and all 3 ADC's data is output on
SDOUT1. Table 3 outlines the serial interface
ports.
Table 3. DSP Serial Input Ports
2.5.2
Audio DSP Serial Interface Formats
The audio DSP port supports 7 alternate formats,
shown in Figures 8, 9, and 10. These formats are
chosen through the DSP Port Mode Byte (#14) with
the DDF2/1/0 bits.
Formats 5 and 6 are single line data modes where
all DAC channels are combined onto a single input
and all ADC channels are combined onto a single
output. Format 6 is available in master mode only.
See Figure 10.
2.5.3
Auxiliary Audio Port Signals
The auxiliary port provides an alternate way to in-
put digital audio signals into the CS4227. This port
consists of clock, data and left/right clock pins
named, SCLKAUX, DATAUX and LRCKAUX.
The Auxiliary Audio Port input is output on
SDOUT1 when IS is set to 1 or 2 in the ADC Con-
trol Byte. Additionally, setting IS to 2 routes the
stereo ADC outputs to SDOUT2. There is approx-
imately a two frame delay from DATAUX to
SDOUT1. When the auxiliary port is used, the fre-
quency of LRCKAUX must be equal to the system
sample rate, Fs, but no particular phase relationship
is required.
De-emphasis can be performed on input data to the
auxiliary audio port; this is controlled by the Aux-
iliary Port Control Byte (#16).
2.5.4
Auxiliary Audio Port Formats
Input data on DATAUX is clocked into the part by
SCLKAUX using the format selected in the Auxil-
iary Port Mode Byte. The auxiliary audio port sup-
DAC Inputs
SDIN1
left channel
right channel
single line
DAC #1
DAC #2
All 6 DAC channels
SDIN2
left channel
right channel
DAC #3
DAC #4
SDIN3
left channel
right channel
DAC #5
DAC #6
CS4227
16
DS281PP2
LRCK
FORMAT 0, 1, 2:
SCLK
SDIN
Format 0: M = 20
Format 1: M = 18
Format 2: M = 16
LSB
LSB
MSB
LSB
MSB
Left
Right
M SCLKs
M SCLKs
LRCK
FORMAT 3:
SCLK
SDIN
MSB
LSB
Left
Right
MSB
LSB
MSB
LRCK
FORMAT 4:
SCLK
SDIN
MSB
LSB
Left
Right
MSB
LSB
Note: SCLK shown for DSCK = 0. SCLK inverted for DSCK = 1.
Figure 8. Audio DSP and Auxiliary Port Data Input Formats
LRCK
FORMAT 0, 1, 2:
SCLK
SDOUT
Format 0: M = 20
Format 1: M = 18
Format 2: M = 16
LSB
LSB
MSB
LSB
MSB
Left
Right
M SCLKs
M SCLKs
LRCK
FORMAT 3:
SCLK
SDOUT
MSB
LSB
Left
Right
MSB
LSB
MSB
LRCK
FORMAT 4:
SCLK
SDOUT
MSB
LSB
Left
Right
MSB
LSB
Note: SCLK shown for DSCK = 0. SCLK inverted for DSCK = 1.
Figure 9. Audio DSP Port Data Output Formats
LRCK
FORMAT 5:
SCLK
SDIN1
LSB
MSB
20 clks
64 SCLKS
64 SCLKS
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
MSB
DAC #1
DAC #3
DAC #5
DAC #2
DAC #4
DAC #6
20 clks
20 clks
20 clks
20 clks
20 clks
20 clks
SDOUT1
SDOUT2
SDOUT1
SDOUT2
20 clks
20 clks
20 clks
SDOUT1
LRCK
FORMAT 6:
SCLK
SDIN1
LSB
MSB
32 clks
128 SCLKS
128 SCLKS
DAC #1
DAC #3
DAC #5
32 clks
32 clks
32 clks
SDOUT1
SDOUT2
32 clks
SDOUT1
LSB
MSB
LSB
MSB
LSB
MSB
32 clks
DAC #2
DAC #4
DAC #6
32 clks
32 clks
32 clks
SDOUT1
SDOUT2
32 clks
LSB
MSB
LSB
MSB
(Master Mode Only)
Figure 10. One Data Line Modes
CS4227
DS281PP2
17
ports the same 5 formats as the audio DSP port in
multi-data line mode. LRCKAUX is used to indi-
cate left and right data samples, and the start of a
new sample period. SCLKAUX and LRCKAUX
may be output from the CS4227, or they may be
generated from an external source, as set by the
AMS1/0 control bits in the Auxiliary Port Mode
Byte (#15).
2.6
Control Port Signals
The control port is used to load all the internal set-
tings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference prob-
lems, the control port pins should remain static if
no operation is required.
The control port has 2 modes: SPI and I
2
C
, with
the CS4227 as a slave device. The SPI mode is se-
lected by setting the SPI/I2C pin low, and I
2
C
is
selected by setting the SPI/I2C pin high. The state
of this pin is continuously monitored.
2.6.1
SPI Mode
In SPI mode, CS is the CS4227 chip select signal,
CCLK is the control port bit clock, (input into the
CS4227 from the microcontroller), CDIN is the in-
put data line from the microcontroller, CDOUT is
the output data line to the microcontroller, and the
chip address is 0010000. Data is clocked in on the
rising edge of CCLK and out on the falling edge.
Figure 11 shows the operation of the control port in
SPI mode. To write to a register, bring CS low. The
first 7 bits on CDIN form the chip address, and they
must be 0010000. The eighth bit is a read/write in-
dicator (R/W), which should be low to write. The
next 8 bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next 8 bits are the data
which will be placed into register designated by the
MAP. During writes, the CDOUT output stays in
the high impedance state. It may be externally
pulled high or low with a 47 k
resistor.
The CS4227 has a MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is a zero, then the MAP will stay constant for
successive reads or writes. If INCR is set to a 1,
then MAP will auto increment after each byte is
read or written, allowing block reads or writes of
successive registers.
To read a register, the MAP has to be set to the cor-
rect address by executing a partial write cycle
which finishes (CS high) immediately after the
MAP byte. The auto MAP increment bit (INCR)
may be set or not, as desired. To begin a read, bring
CS low, send out the chip address and set the
read/write bit (R/W) high. The next falling edge of
CCLK will clock out the MSB of the addressed
register (CDOUT will leave the high impedance
state). If the MAP auto increment bit is set to 1, the
data for successive registers will appear consecu-
tively.
MAP
MSB
LSB
DATA
byte 1
byte n
R/W
R/W
High Impedance
MAP = Memory Address Pointer
ADDRESS
CHIP
ADDRESS
CHIP
CDIN
CCLK
CS
CDOUT
MSB
LSB MSB
LSB
0010000
0010000
Figure 11. Control Port Timing, SPI Mode
CS4227
18
DS281PP2
2.6.2
I
2
C
Mode
In I
2
C
mode, SDA is a bidirectional data line.
Data is clocked into and out of the part by the clock,
SCL, with the clock to data relationship as shown
in Figure 12. There is no CS pin. Pins AD0, AD1
form the partial chip address. The upper 5 bits of
the 7 bit address field must be 00100. To commu-
nicate with a CS4227, the LSBs of the chip address
field, which is the first byte sent to the CS4227,
should match the settings of the AD1, AD0 pins.
The eighth bit of the address bit is the R/W bit (high
for a read, low for a write). If the operation is a
write, the next byte is the Memory Address Pointer
which selects the register to be read or written. If
the operation is a read, the contents of the register
pointed to by the Memory Address Pointer will be
output. Setting the auto increment bit in MAP, al-
lows successive reads or writes of consecutive reg-
isters. Each byte is separated by an acknowledge
bit. Use of the I
2
C bus
compatible interface re-
quires a license from Philips. I
2
C bus
is a regis-
tered trademark of Philips Semiconductors.
2.6.3
Control Port Bit Definitions
All registers can be written and read back, except
the DAC Status Report Byte (#10) and ADC Status
Report Byte (#13), which are read only. See the fol-
lowing bit definition tables for bit assignment in-
formation.
2.7
Power-up/Reset/Power Down Mode
Upon power up, the user should hold PDN = 0 for
approximately 1ms. In this state, the control port is
reset to its default settings. At the end of the PDN,
the device remains in a low power mode in which
CMOUT will not supply current, but the control
port is active. The desired settings should be loaded
while keeping the RS bit set to 1. Normal operation
is achieved by setting the CE bit to zero in the
Clock Mode Byte (#1) and the RS bit to zero in the
Converter Control Byte (#2). Once done, the part
powers up and an offset calibration occurs. This
process lasts approximately 50 ms.
Reset/power down is achieved by lowering the
PDN pin causing the part to enter power down.
Once PDN goes high, the control port is functional
and the desired settings should be loaded in while
keeping the RS bit set to 1. The remainder of the
chip remains in a low power reset state until the RS
bit in the Convertor Control Byte is set to 0. After
clearing the RS bit, the CE bit (Clock Enable) in the
Clock Mode Byte (#1) should also be set to zero.
The CS4227 will also enter a stand by mode if the
master clock source stops for approximately 10 s
or if the LRCK is not synchronous to the master
clock. The control port will retain its current set-
tings.
SDA
SCL
00100
ADDR
AD1-0
R/W
Start
ACK
DATA
1-8
ACK
DATA
1-8
ACK
Stop
Note 1: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Note 1
Figure 12. Control Port Timing, I
2
C
Mode
CS4227
DS281PP2
19
2.8
DAC Calibration
Output offset voltage is minimized by an internal
calibration cycle. A calibration will automatically
occur anytime the part comes out of reset, includ-
ing the power-up reset, or when the master clock
source to the part changes by changing the CE or CI
bits in the Clock Mode Byte.
The CS4227 can be re-calibrated whenever de-
sired. A control bit, CAL, in the Converter Control
Byte, is provided to initiate a calibration. The se-
quence is:
1) Set CAL to 1, the CS4227 sets CALP to 1 and
begins to calibrate.
2) CALP will go to 0 when the calibration is com-
pleted.
Additional calibrations can be implemented by set-
ting CAL to 0 and then to 1.
2.9
De-Emphasis
The CS4227 is capable of digital de-emphasis for
32, 44.1, or 48 kHz sample rates. Implementation
of digital de-emphasis requires reconfiguration of
the digital filter to maintain the filter response
shown in Figure 13 at multiple sample rates. The
Auxiliary Port Control Byte selects the de-empha-
sis control method. De-emphasis may be enabled
under hardware control, using the DEM pin
(DEM2/1/0=4,5,6), or by software control using
the DEM bit (DEM2/1/0=0,1,2,3)
2.10
Hold Function
If the digital audio source presents invalid data to
the CS4227, the CS4227 may be configured to
cause the last valid digital input level to be held
constant (this sounds much better than a potentially
random output level). Holding the previous output
sample occurs when the user asserts the HOLD pin
(HOLD = 1) at any time during the stereo sample
period. During a HOLD condition, AUXPort input
data is ignored. DAC outputs can be automatically
muted after an extended HOLD period (>15 sam-
ples) by setting the MOH bit = 0 in the Auxiliary
Port Control Byte. DACs will not be automatically
muted when MOH = 1. When the HOLD pin is de-
asserted (HOLD = 0), the DAC outputs will return
to one of two different states controlled by the
UMV (Unmute on Valid Data) bit in the Auxiliary
Port Control Byte. When UMV = 0, the DAC out-
puts will unmute when the HOLD is removed.
When UMV = 1, the DACs must be unmuted in the
DAC Control Byte after the HOLD is removed.
This allows the user to unmute the DAC after the
invalid data has passed through the DSP.
2.11
Power Supply, Layout, and
Grounding
The CS4227, along with associated analog circuit-
ry, should be positioned near the split between
ground planes, and have its own, separate, ground
plane (see Figure 14). Preferably, it should also
have its own power plane. The +5 V supply must be
connected to the CS4227 via a ferrite bead, posi-
tioned closer than 1" to the device. A single con-
nection between the CS4227 ground and the board
ground should be positioned as shown in Figure 14.
The location of the 1 F CMOUT filtering capica-
tor should be as close to the CS4227 as possible.
See Crystal's layout Applications Note, and the
CDB4227 evaluation board data sheet for recom-
mended layout of the decoupling components.
Gain
dB
-10dB
0dB
Frequency
T2 = 15
s
T1=50
s
F1
F2
Figure 13. De-emphasis Curve.
CS4227
20
DS281PP2
The CS4227 will mute the analog outputs and enter
the Power Down Mode if the supply drops below
approximately 4 volts.
2.12
ADC and DAC Filter Response Plots
Figures 15 through 20 show the overall frequency
response, passband ripple and transition band for
the CS4227 ADC's and DAC's.
Digital
Ground
Plane
Note that the CS4227
is oriented with its
digital pins towards the
digital end of the board.
CPU & Digital
Logic
Codec
digital
signals
Analog
Ground
Plane
1/8"
>
CS4227
+5V
Ferrite
Bead
Ground
Connection
Codec
analog
signals &
components
Figure 14. Suggested Layout Guideline
CS4227
DS281PP2
21
Figure 15. 20-bit ADC Filter Response
Figure 16. 20-bit ADC Passband Ripple
Figure 17. 20-bit ADC Transition Band
Figure 18. DAC Frequency Response
Figure 19. DAC Passband Ripple
Figure 20. DAC Transition Band
CS4227
22
DS281PP2
2.13
Memory Address Pointer (MAP)
MAP4-MAP0
Register Pointer
INCR
Auto Increment Control Bit
0 - No auto increment
1 - Auto increment on
This register defaults to 01h.
2.14
Reserved Byte (0)
This byte is reserved for internal use and must be set to 00h for normal operation.
This register defaults to 00h.
2.15
Clock Mode Byte (1)
CE
Master clock enable
0 - Clock Enabled
1 - Clock Disabled
CI1-CI0
Determines frequency of XTI
0 - 256 Fs
1 - 384 Fs
2 - 512 Fs
3 - not used
CO1-CO0
Sets CLKOUT frequency
0 - 256 Fs
1 - 384 Fs
2 - 512 Fs
3 - 1 Fs
This register defaults to 01h.
7
6
5
4
3
2
1
0
INCR
0
0
MAP4
MAP3
MAP2
MAP1
MAP0
7
6
5
4
3
2
1
0
0
CO1
CO0
CI1
CI0
0
0
CE
CS4227
DS281PP2
23
2.16
Converter Control Byte (2)
RS
Chip reset
0 - No Reset
1 - Reset
CAL
Calibration control bit
0 - Normal operation
1 - Rising edge initiates calibration
The following bits are read only:
DU
Shows selected De-Emphasis setting used by DAC's
0 - Normal Flat DAC frequency response
1 - De-Emphasis selected
CLKE
Clocking system status
0 - No errors
1 - Crystal is not oscillating, or requesting clock change in progress
CALP
Calibration status
0 - Calibration done
1 - Calibration in progres
This register defaults to 01h.
2.17
DAC Control Byte (3)
MUT6-MUT1
Mute control bits
0 - Normal output level
1 - Selected DAC output muted
MUTC
Controls mute on consecutive zeros function
0 - 512 consecutive zeros will mute DAC
1 - DAC output will not mute on zeros
ZCD
Zero crossing disable
0 - DAC mutes and volume control changes occur on zero-crossings
1 - DAC mutes and volume control changes occur immediately.
This register defaults to 3Fh.
7
6
5
4
3
2
1
0
CALP
CLKE
DU
0
0
0
CAL
RS
7
6
5
4
3
2
1
0
ZCD
MUTC
MUT6
MUT5
MUT4
MUT3
MUT2
MUT1
CS4227
24
DS281PP2
2.18
Output Attenuator Data Byte (4, 5, 6, 7, 8, 9)
ATT6-ATT0
Sets attenuator level
0 - No attenuation
127 - 127 dB attenuation
ATT0 represents 1.0 dB of attenuation
This register defaults to 7Fh.
2.19
DAC Status Report Byte (Read Only) (10)
ACC6-ACC1
Acceptance Bit
0 - ATT6-ATT0 has been accepted.
1 - New setting is waiting for zero-crossing to be accepted.
This register is read-only.
2.20
ADC Control Byte (11)
MUTL, MUTR, MUTM - Left, right and mono channel mute control
0 - Normal output level
1 - Selected ADC output muted
AIS1-AIS0
ADC analog input mux control
0 - Selects stereo pair 1
1 - Selects stereo pair 2
2 - Selects stereo pair 3
3 - Differential Input
IS1-IS0
Input mux selection
0 - Stereo ADC output to SDOUT1, Mono ADC output to SDOUT2
1 - Auxiliary Digital Input Port to SDOUT1, Mono ADC output to SDOUT2
2 - Auxiliary Digital Input Port to SDOUT1, Stereo ADC output to SDOUT2
3 - Not used.
This register defaults to 00h.
7
6
5
4
3
2
1
0
0
ATT6
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
7
6
5
4
3
2
1
0
0
-
ACC6
ACC5
ACC4
ACC3
ACC2
ACC1
7
6
5
4
3
2
1
0
IS1
IS0
0
AIS1
AIS0
MUTM
MUTR
MUTL
CS4227
DS281PP2
25
2.21
Input Control Byte (12)
GNL1-GNL0
Sets left input gain
0 - 0 dB
1 - 3 dB
2 - 6 dB
3 - 9 dB
GNR1-GNR0
Sets right input gain
0 - 0 dB
1 - 3 dB
2 - 6 dB
3 - 9 dB
OVRM
ADC Overflow Mask
This register defaults to 00h.
2.22
ADC Status Report Byte (Read Only) (13)
LVL2-LVL0, LVR2-0 Left and Right ADC output level
0 - Normal output levels
1 - -6 dB level
2 - -5 dB level
3 - -4 dB level
4 - -3 dB level
5 - -2 dB level
6 - -1 dB level
7 - Clipping
LVLM1-LVLM0
Mono ADC output level
0 - Normal output level
1 - -6 dB level
2 - -3 dB level
3 - Clipping
These bits are 'sticky'. They constantly monitor the ADC output for the peak levels and hold the max-
imum output. They are reset to 0 when read.
This register is read only.
7
6
5
4
3
2
1
0
OVRM
0
0
0
GNR1
GNR0
GNL1
GNL0
7
6
5
4
3
2
1
0
LVM1
LVM0
LVR2
LVR1
LVR0
LVL2
LVL1
LVL0
CS4227
26
DS281PP2
2.23
DSP Port Mode Byte (14)
DDF2-DDF0
Data format
0 - Right justified, 20-bit
1 - Right justified, 18-bit
2 - Right justified, 16-bit
3 - Left justified, 20-bit in / 24-bit out
4 - I
2
S compatible, 20-bit in / 24-bit out
5 - One Data Line Mode (Figure 10)
6 - One Data Line (Master Mode only, Figure 10)
7 - Not used
DSCK
Set the polarity of clocking data
0 - Data clocked in on rising edge, out on falling edge
1 - Data clocked in on falling edge, out on rising edge
DMS1-DMS0
Sets the mode of the port
0 - Slave
1 - Master Burst - SCLKs are gated 128 Fs clocks
2 - Master Non-Burst - SCLKs are evenly distributed (No 48 Fs SCLK)
3 - not used - default to Slave
DCK1-DCK0*
Set number of bit clocks per Fs period
0 - 128
1 - 48 - Master Burst or Slave mode only
2 - 32 - All formats will default to 16 bits
3 - 64
This register defaults to 00h.
* Ignored in data formats 5 and 6.
7
6
5
4
3
2
1
0
DCK1
DCK0
DMS1
DMS0
DSCK
DDF2
DDF1
DDF0
CS4227
DS281PP2
27
2.24
Auxiliary Port Mode Byte (15)
ADF2-ADF0
Data format
0 - Right justified, 20-bit data
1 - Right justified, 18-bit data
2 - Right justified, 16-bit data
3 - Left justified, 20-bit
4 - I
2
S compatible, 20-bit
5 - Not used
6 - Not used
7 - Not used
ASCK
Sets the polarity of clocking data
0 - Data clocked in on rising edge
1 - Data clocked in on falling edge
AMS1-AMS0
Sets the mode of the port.
0 - Slave
1 - Master Burst - SCLKAUXs are gated 128 Fs clocks
2 - Master Non-Burst - SCLKAUXs are evenly distributed in LRCKAUX frame
3 - Not used - default to slave
ACK1-ACK0
Set number of bit clocks per Fs period.
0 - 128
1 - 48 - Master Burst or Slave mode only
2 - 32 - All input formats will default to 16 bits.
3 - 64
This register defaults to 00h.
7
6
5
4
3
2
1
0
ACK1
ACK0
AMS1
AMS0
ASCK
ADF2
ADF1
ADF0
CS4227
28
DS281PP2
2.25
Auxilliary Port Control Byte (16)
DEM 2-0
Selects de-emphasis response/source
0 - De-emphasis off
1 - De-emphasis on 32 kHz
2 - De-emphasis on 44.1 kHz
3 - De-emphasis on 48 kHz
4 - De-emphasis pin 32 kHz
5 - De-emphasis pin 44.1 kHz
6 - De-emphasis pin 48 kHz
7 - Reserved
MOH
Mute On Hold
0 - Extended Hold (16 frames) mutes DAC outputs
1 - DACs not muted
UMV
Unmute on Valid Data
0 - DACs unmute when HOLD is removed
1 - DACs must be unmuted in DAC control byte after HOLD is removed.
This register defaults to 00h.
7
6
5
4
3
2
1
0
0
0
UMV
MOH
0
DEM2
DEM1
DEM0
CS4227
DS281PP2
29
3.
PIN DESCRIPTIONS
Power Supply
VA+ - Analog Power Input
+5 V analog supply.
AGND1, AGND2 - Analog Ground
Analog grounds.
VD+ - Digital Power Input
+ 5 V digital supply.
DGND1, DGND2 - Digital Ground
Digital grounds.
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34
CS4227-KQ
44-pin TQFP
Top View
AD0/CS
AD1/CDIN
XTI
SDA/CDOUT
SCL/CCLK
HOLD
DATAUX
LRCKAUX
SCLKAUX
NC
DGND1
VD+
DGND2
CMOUT
AINAUX
AIN1L
AIN1R
AIN2R
AIN2L
AIN3L
AIN3R
PDN
SPI/I2C
XTO
OVL
CLKOUT
SDIN3
SDIN2
SDIN1
SDOUT2
SDOUT1
LRCK
SCLK
NC
AGND1
VA+
AGND2
AOUT1
AOUT2
AOUT3
AOUT4
AOUT5
AOUT6
DEM
CS4227
30
DS281PP2
Analog Inputs
AIN1L, AIN1R - Left and Right Channel Mux Input 1
Analog signal input connections for the right and left channels for multiplexer input 1.
AIN2L, AIN2R - Left & Right Channel Mux Input 2
Analog signal input connections for the right and left channels for multiplexer input 2.
AIN3L, AIN3R - Left & Right Channel Mux Input 3
Analog signal input connections for the right and left channels for multiplexer input 3.
AINAUX - Auxiliary Line Level Input
Analog signal input for the mono A/D converter.
Analog Outputs
AOUT1, AOUT2, AOUT3, AOUT4, AOUT5, AOUT6 - Audio Outputs
The analog outputs from the 6 D/A converters. Each output can be independently controlled for output
amplitude.
CMOUT - Common Mode Output
This common mode voltage output may be used for level shifting when DC coupling is desired. The load
on CMOUT must be DC only, with an impedance of not less than 50 k
. CMOUT should be bypassed
with a 1.0 F to AGND.
Digital Audio Interface Signals
SDIN1 - Serial Data Input 1
Digital audio data for the DACs 1 and 2 is presented to the CS4227 on this pin. This pin is also used for
one-line data input modes.
SDIN2 - Serial Data Input 2
Digital audio data for the DACs 3 and 4 is presented to the CS4227 on this pin.
SDIN3 - Serial Data Input 3
Digital audio data for the DACs 5 and 6 is presented to the CS4227 on this pin.
SDOUT1- Serial Data Output 1
Digital audio data from the 20-bit stereo audio ADCs is output from this pin. When IS = 1 or 2,
DATAAUX is output on SDOUT1. This pin is also used for one line data output modes.
SDOUT2 - Serial Data Output 2
Digital audio data from the mono audio ADC is output from this pin. When IS = 2, the stereo audio
ADC's are output from this pin
SCLK - DSP Serial Port Clock I/O
SCLK clocks digital audio data into the DACs via SDIN1/2/3, and clocks data out of the ADCs on
SDOUT1/2. Active clock edge depends on the DSCK bit.
CS4227
DS281PP2
31
LRCK - Left/Right Select Signal I/O
The Left/Right select signal. This signal has a frequency equal to the sample rate. The relationship of
LRCK to the left and right channel data depends on the selected format.
DEM - De-emphasis Control
When low, DEM controls the activation of the standard 50/15 us de-emphasis filter for either 32, 44.1 or
48 kHz sample rates. This pin is enabled by the DEM2-0 bits in the Auxiliary Port Control Byte.
OVL - Overload Indicator
This pin goes high if either of the stereo audio ADCs or the mono ADC is clipping.
Auxillary Digital Audio Signals
DATAUX - Auxiliary Data Input
DATAUX is the auxiliary audio data input line, usually connected to an external digital audio source.
LRCKAUX - Auxiliary Word Clock Input or Output
In auxiliary slave mode, LRCKAUX is a word clock (at Fs) from an external digital audio source. In
auxiliary master mode, LRCKAUX is a word clock output (at Fs) to clock an external digital audio
source.
SCLKAUX - Auxiliary Bit Clock Input or Output
In auxiliary slave mode, SCLKAUX is the serial data bit clock from an external digital audio source, used
to clock in data on DATAAUX. In auxiliary master mode, SCLKAUX is a serial data bit clock output.
HOLD - HOLD Control
This pin is sampled on the active edge of SCLKAUX. If it is high any time during the frame, DATAUX
data is ignored and the previous "good" sample is output to the serial output port.
Control Port Signals
SPI/I2C - Control Port Format
Setting this pin low configures the control port for the SPI interface; a high state configures the control
port for the I
2
C interface. The state of this pin sets the function of the control port input/output pins .
SCL/CCLK - Serial Control Interface Clock
SCL/CCLK is the serial control interface clock, and is used to clock control bits into and out of the
CS4227.
AD0/CS - Address Bit / Control Port Chip Select
In I
2
C
mode, AD0 is a chip address bit. In SPI software control mode, CS is used to enable the control
port interface on the CS4227.
AD1/CDIN - Address Bit / Serial Control Data In
In I
2
C
mode, AD1 is a chip address bit. In SPI software control mode, CDIN is the input data line for
the control port interface.
SDA/CDOUT - Serial Control Data Out
In I
2
C
mode, SDA is the control data I/O line. In SPI software control mode, CDOUT is the output data
from the control port interface on the CS4227.
CS4227
32
DS281PP2
Clock and Crystal Pins
XTI, XTO - Crystal connections
Input and output connections for the crystal which may be used to operate the CS4227. Alternatively, a
clock may be input into XTI.
CLKOUT - Master Clock Output
CLKOUT allows external circuits to be synchronized to the CS4227. Alternate output frequencies are
selectable by the control port.
Miscellaneous Pins
PDN - Powerdown Pin
When low, the CS4227 enters a low power mode and all internal states are reset, including the control
port. When high, the control port becomes operational and the RS bit must be cleared before normal
operation will occur.
NC - No Connect
CS4227
DS281PP2
33
4.
PARAMETER DEFINITIONS
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over
the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dbFs signal. 60 dB is then added to the resulting measurement to refer the
measurement to full scale. This technique ensures that the distortion components are below the noise
level and do not effect the measurement. This measurement technique has been accepted by the Audio
Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth (typically 20 Hz to 20 kHz), including distortion components. Expressed in decibels.
ADCs are measured at -1 dBFs as suggested in AES 17-1991 Annex A.
Idle Channel Noise / Signal-to-Noise-Ratio
The ratio of the rms analog output level with 1kHz full scale digital input to the rms analog output level
with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz bandwidth. Units in
decibels. This specification has been standardized by the Audio Engineering Society, AES17-1991, and
referred to as Idle Channel Noise. This specification has also been standardized by the Electronic
Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio.
Total Harmonic Distortion (THD)
THD is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the test
signal. Units in decibels.
Interchannel Isolation
A measure of crosstalk between channels. Measured for each channel at the converter's output with no
signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Frequency Response
A measure of the amplitude response variation from 20 Hz to 20 kHz relative to the amplitude response
at 1 kHz. Units in decibels.
Interchannel Gain Mismatch
For the ADCs, the difference in input voltage that generates the full scale code for each channel. For
the DACs, the difference in output voltages for each channel with a full scale digital input. Units are in
decibels.
Gain Error
The deviation from the nominal full scale output for a full scale input.
Gain Drift
The change in gain value with temperature. Units in ppm/C.
Offset Error
For the ADCs, the deviation in LSB's of the output from mid-scale with the selected input grounded. For
the DAC's, the deviation of the output from zero (relative to CMOUT) with mid-scale input code. Units
are in volts.
CS4227
34
DS281PP2
5.
PACKAGE DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
A
0.000
0.065
0.00
1.60
A1
0.002
0.006
0.05
0.15
B
0.012
0.018
0.30
0.45
D
0.478
0.502
11.70
12.30
D1
0.404
0.412
9.90
10.10
E
0.478
0.502
11.70
12.30
E1
0.404
0.412
9.90
10.10
e
0.029
0.037
0.70
0.90
L
0.018
0.030
0.45
0.75
0.000
7.000
0.00
7.00
TYP
MAX
TYP
MAX
Coplanarity
.001
.004
.025
.10
JEDEC # : MS-026
44L TQFP PACKAGE DRAWING
E1
E
D1
D
1
e
L
B
A1
A
Notes
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