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Электронный компонент: CS42432-CMZR

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Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
Cirrus Logic, Inc. 2005
(All Rights Reserved)
Cirrus Logic, Inc.
http://www.cirrus.com
FEATURES
Four 24-bit A/D, Six 24-bit D/A Converters
ADC Dynamic Range
105 dB Differential
102 dB Single-ended
DAC Dynamic Range
108 dB Differential
105 dB Single-ended
ADC/DAC THD+N
-98 dB Differential
-95 dB Single-ended
Compatible with Industry-standard Time
Division Multiplexed (TDM) Serial Interface
DAC Sampling Rates up to 192 kHz
ADC Sampling Rates up to 96 kHz
Programmable ADC High-pass Filter for DC
Offset Calibration
Logarithmic Digital Volume Control
Hardware Mode or Software IC & SPI
TM
Supports Logic Levels Between 5 V and
1.8 V
GENERAL DESCRIPTION
The CS42432 CODEC provides
four
multi-bit analog-to-dig-
ital and
six
multi-bit digital-to-analog Delta-sigma
converters. The CODEC is capable of operation with either
differential or single-ended inputs and outputs, in a
52
-pin
M
QFP package.
Four
fully differential, or single-ended, inputs are available
on stereo ADC1and ADC
2
. Digital volume control is provid-
ed for each ADC channel, with selectable overflow
detection.
All
six
DAC channels provide digital volume control and can
operate with differential or single-ended outputs.
An auxiliary serial input is available for an additional two
channels of PCM data.
The CS42432 is ideal for audio systems requiring wide dy-
namic range, negligible distortion and low noise, such as
A/V receivers, DVD receivers, and automotive audio
systems.
ORDERING INFORMATION
See page 59
.
Control Port & Serial
Audio Port Supply =
1.8 V to 5 V
Register
Configuration
Internal Voltage
Reference
Reset
TD
M Seria
l
In
te
r
f
a
c
e
Level Trans
lat
o
r
Le
v
e
l Trans
lat
o
r
TDM Serial Audio
Input
Digital Supply =
3.3 V
Hardware Mode or
I
2
C/SPI Software Mode
Control Data
Analog Supply =
3.3 V to 5 V
Differential or
Single-Ended
Outputs
6
Input Master
Clock
6
TDM Serial Audio
Output
Multibit
Oversampling
ADC1
High Pass
Filter
Differential or
Single-Ended
Analog Inputs
2
Digital
Filters
2
Multibit
Oversampling
ADC2
High Pass
Filter
2
Digital
Filters
2
Auxilliary Serial
Audio Input
Volume
Controls
Digital
Filters
Multibit
DAC1-3 and
Analog Filters
Modulators
CS42432
FEB `05
DS673PP2
108 dB, 192 kHz 4-in, 6-out TDM CODEC
2
DS673PP2
TABLE OF CONTENTS
1 PIN DESCRIPTION - SOFTWARE MODE ................................................................................ 6
1.1 Digital I/O Pin Characteristics ............................................................................................ 7
2 PIN DESCRIPTIONS - HARDWARE MODE ............................................................................ 8
3 TYPICAL CONNECTION DIAGRAMS .................................................................................... 10
4 CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 12
SPECIFIED OPERATING CONDITIONS ............................................................................... 12
ABSOLUTE MAXIMUM RATINGS ......................................................................................... 12
ANALOG INPUT CHARACTERISTICS (CS42432-CMZ)....................................................... 13
ANALOG INPUT CHARACTERISTICS (CS42432-DMZ)....................................................... 14
ADC DIGITAL FILTER CHARACTERISTICS ......................................................................... 15
ANALOG OUTPUT CHARACTERISTICS (CS42432-CMZ)................................................... 16
ANALOG OUTPUT CHARACTERISTICS (CS42432-DMZ)................................................... 18
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ................ 20
SWITCHING SPECIFICATIONS - ADC/DAC PORT .............................................................. 21
SWITCHING CHARACTERISTICS - AUX PORT................................................................... 22
SWITCHING SPECIFICATIONS - CONTROL PORT - IC MODE......................................... 23
SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT ................................... 24
DC ELECTRICAL CHARACTERISTICS................................................................................. 25
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ....................................... 25
5 APPLICATIONS ....................................................................................................................... 26
5.1 Overview .......................................................................................................................... 26
5.2 Analog Inputs ................................................................................................................... 27
5.2.1 Line Level Inputs ................................................................................................. 27
5.2.2 High Pass Filter and DC Offset Calibration ....................................................... 27
5.3 Analog Outputs ................................................................................................................ 28
5.3.1 Initialization ......................................................................................................... 28
5.3.2 Line-level Outputs and Filtering .......................................................................... 28
5.3.3 Digital Volume Control ........................................................................................ 30
5.3.4 De-Emphasis Filter .............................................................................................. 30
5.4 System Clocking .............................................................................................................. 31
5.5 CODEC Digital Interface .................................................................................................. 31
5.5.1 TDM .................................................................................................................... 31
5.5.2 I/O Channel Allocation ........................................................................................ 32
5.6 AUX Port Digital Interface Formats .................................................................................. 33
5.6.1 IS ........................................................................................................................ 33
5.6.2 Left Justified ........................................................................................................ 33
5.7 Control Port Description and Timing ................................................................................ 34
5.7.1 SPI Mode ............................................................................................................ 34
5.7.2 I
2
C Mode ............................................................................................................. 35
5.8 Recommended Power-up Sequence ............................................................................... 36
5.8.1 Hardware Mode ................................................................................................... 36
5.8.2 Software Mode .................................................................................................... 36
5.9 Reset and Power-up ....................................................................................................... 36
5.10 Power Supply, Grounding, and PCB layout ................................................................... 37
6 REGISTER QUICK REFERENCE ........................................................................................... 38
7 REGISTER DESCRIPTION ..................................................................................................... 40
7.1 Memory Address Pointer (MAP) ....................................................................................... 40
7.2 Chip I.D. and Revision Register (address 01h) (Read Only) ............................................ 40
7.3 Power Control (address 02h) ............................................................................................ 41
7.4 Functional Mode (address 03h) ........................................................................................ 42
7.5 Miscellaneous Control (address 04h) ............................................................................... 42
DS673PP2
3
7.6 ADC Control & DAC De-emphasis (address 05h) ............................................................ 43
7.7 Transition Control (address 06h) ...................................................................................... 44
7.8 DAC Channel Mute (address 07h) ................................................................................... 45
7.9 AOUTX Volume Control (addresses 08h-0D) ............................................................... 45
7.10 DAC Channel Invert (address 10h) ................................................................................ 46
7.11 AINX Volume Control (address 11h-14h) ....................................................................... 46
7.12 ADC Channel Invert (address 17h) ................................................................................ 47
7.13 Status (address 19h) (Read Only)................................................................................. 47
7.14 Status Mask (address 1Ah) ............................................................................................ 47
8 APPENDIX A: EXTERNAL FILTERS ...................................................................................... 49
8.1 ADC Input Filter ............................................................................................................... 49
8.1.1 Passive Input Filter ............................................................................................. 50
8.1.2 Passive Input Filter w/Attenuation ....................................................................... 50
8.2 DAC Output Filter ............................................................................................................ 51
9 APPENDIX B: ADC FILTER PLOTS ....................................................................................... 52
10 APPENDIX C: DAC FILTER PLOTS ..................................................................................... 54
11 PARAMETER DEFINITIONS ................................................................................................. 56
12 REFERENCES ....................................................................................................................... 57
13 PACKAGE INFORMATION ................................................................................................... 58
13.1 Thermal Characteristics ................................................................................................ 58
14 ORDERING INFORMATION ................................................................................................. 59
15 REVISION HISTORY ............................................................................................................. 60
4
DS673PP2
LIST OF FIGURES
Figure 1. Typical Connection Diagram (Software Mode) .............................................................. 10
Figure 2. Typical Connection Diagram (Hardware Mode) ............................................................. 11
Figure 3. Output Test Load ........................................................................................................... 19
Figure 4. Maximum Loading.......................................................................................................... 19
Figure 5. TDM Serial Audio Interface Timing ................................................................................ 21
Figure 6. Serial Audio Interface Slave Mode Timing ..................................................................... 22
Figure 7. Control Port Timing - IC Format.................................................................................... 23
Figure 8. Control Port Timing - SPI Format................................................................................... 24
Figure 9. Full-Scale Input .............................................................................................................. 27
Figure 10. Audio Output Initialization Flow Chart .......................................................................... 29
Figure 11. Full-Scale Output ......................................................................................................... 30
Figure 12. De-Emphasis Curve ..................................................................................................... 31
Figure 13. TDM Serial Audio Format............................................................................................. 32
Figure 14. AUX IS Format............................................................................................................ 33
Figure 15. AUX Left Justified Format ............................................................................................ 33
Figure 16. Control Port Timing in SPI Mode.................................................................................. 34
Figure 17. Control Port Timing, IC Write ...................................................................................... 35
Figure 18. Control Port Timing, IC Read...................................................................................... 35
Figure 19. Single to Differential Active Input Filter ........................................................................ 49
Figure 20. Single-Ended Active Input Filter................................................................................... 49
Figure 21. Passive Input Filter....................................................................................................... 50
Figure 22. Passive Input Filter w/Attenuation................................................................................ 50
Figure 23. Active Analog Output Filter .......................................................................................... 51
Figure 24. Passive Analog Output Filter........................................................................................ 51
Figure 25. SSM Stopband Rejection ............................................................................................. 52
Figure 26. SSM Transition Band ................................................................................................... 52
Figure 27. SSM Transition Band (Detail)....................................................................................... 52
Figure 28. SSM Passband Ripple ................................................................................................. 52
Figure 29. DSM Stopband Rejection............................................................................................. 52
Figure 30. DSM Transition Band ................................................................................................... 52
Figure 31. DSM Transition Band (Detail) ...................................................................................... 53
Figure 32. DSM Passband Ripple ................................................................................................. 53
Figure 33. SSM Stopband Rejection ............................................................................................. 54
Figure 34. SSM Transition Band ................................................................................................... 54
Figure 35. SSM Transition Band (detail) ....................................................................................... 54
Figure 36. SSM Passband Ripple ................................................................................................. 54
Figure 37. DSM Stopband Rejection............................................................................................. 54
Figure 38. DSM Transition Band ................................................................................................... 54
Figure 39. DSM Transition Band (detail) ....................................................................................... 55
Figure 40. DSM Passband Ripple ................................................................................................. 55
Figure 41. QSM Stopband Rejection............................................................................................. 55
Figure 42. QSM Transition Band................................................................................................... 55
Figure 43. QSM Transition Band (detail)....................................................................................... 55
Figure 44. QSM Passband Ripple................................................................................................. 55
DS673PP2
5
LIST OF TABLES
Table 1. I/O Power Rails........................................................................................................................ 7
Table 2. Hardware Configurable Settings............................................................................................ 26
Table 3. MCLK Frequency Settings..................................................................................................... 31
Table 4. Serial Audio Interface Channel Allocations ........................................................................... 32
Table 5. MCLK Frequency Settings..................................................................................................... 42
Table 7. Example AIN Volume Settings .............................................................................................. 46
Table 6. Example AOUT Volume Settings .......................................................................................... 46
Table 8. Revision History..................................................................................................................... 60