Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 2003
(All Rights Reserved)
Cirrus Logic, Inc.
www.cirrus.com
CS4271
24-Bit, 192 kHz Stereo Audio CODEC
D/A Features
!
High performance
114 dB dynamic range
-100 dB THD+N
!
Up to 192 kHz sampling rates
!
Differential analog architecture
!
Volume control with soft ramp
1 dB step size
Zero crossing click-free transitions
!
Selectable digital filters
Fast and slow roll-off
!
ATAPI mixing functions
!
Selectable serial audio interface formats
Left justified up to 24-bit
I
2
S up to 24-bit
Right justified 16, 18, 20, and 24-bit
!
Control output for external muting
!
Selectable 50/15
s de-emphasis
A/D Features
!
High performance
108 dB dynamic range
-98 dB THD+N
!
Up to 192 kHz sampling rates
!
Single-Ended Analog Architecture
!
Multi-bit Delta Sigma conversion
!
High pass filter or DC offset calibration
!
Linear phase digital anti-alias filtering
!
Automatic dithering of 16-bit data
!
Selectable serial audio interface formats
Left justified up to 24-bit
I
2
S up to 24-bit
System Features
!
Direct interface with 5V to 2.5V logic levels
!
Internal digital loopback
!
On-chip oscillator
!
Stand-Alone or control port functionality
2.5 V to 5 V
Left and
Right Mute
C ontrols
Modulator
Modulator
Linear Phase
Anti-Alias F ilter
E xternal
Mute C ontrol
Register / Hardware
C onfiguration
Internal Voltage
Reference
Internal
O scillator
Volume
C ontrol
Mi
xe
r
Selectable
Interpolation
F ilter
Selectable
Interpolation
F ilter
Reset
Left
Differential
O utput
Right
Differential
O utput
Switched C apacitor
DAC and F ilter
Multibit
O versampling
ADC
Multibit
O versampling
ADC
Linear Phase
Anti-Alias F ilter
High Pass F ilter &
DC O ffset C alibration
High Pass F ilter &
DC O ffset C alibration
P
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M
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Left Input
Right Input
Volume
C ontrol
L
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Serial
Audio
Input
Serial
Audio
O utput
3.3 V to 5 V
5 V
Hardware or
I
2
C /SPI
C ontrol Data
Switched C apacitor
DAC and F ilter
MAR `03
DS592PP1
CS4271
2
Stand-Alone Mode Feature Set
!
System features
Serial audio port master or slave operation
Internal oscillator for master clock
!
D/A features
Auto-mute on static samples
44.1 kHz 50/15
s de-emphasis available
Selectable serial audio interface formats
"
Left justified up to 24-bit
"
I
2
S up to 24-bit
!
A/D features
Automatic dithering for 16-bit data
High-pass filter
Selectable serial audio interface formats
"
Left justified up to 24-bit
"
I
2
S up to 24-bit
Software Mode Feature Set
!
System features
Serial audio port master or slave operation
Internal oscillator for master clock
Internal digital loopback available
!
D/A features
Selectable auto-mute
Selectable interpolation filters
Selectable 32, 44.1, and 48 kHz de-emphasis
filters
Configurable ATAPI mixing functions
Configurable volume and muting controls
Selectable serial audio interface formats
"
Left justified up to 24-bit
"
I
2
S up to 24-bit
"
Right justified 16, 18, 20, and 24-bit
!
A/D Features
Selectable dithering for 16-bit data
Selectable high-pass filter or DC offset
calibration
Selectable serial audio interface formats
"
Left justified up to 24-bit
"
I
2
S up to 24-bit
General Description
The CS4271 is a high-performance, integrated audio
CODEC. The CS4271 performs stereo analog-to-digital
(A/D) and digital-to-analog (D/A) conversion of up to
24-bit serial values at sample rates up to 192 kHz.
The D/A offers a volume control that operates with a
1 dB step size. It incorporates selectable soft ramp and
zero crossing transition functions to eliminate clicks and
pops.
The D/A's integrated digital mixing functions allow a va-
riety of output configurations ranging from a channel
swap to a stereo-to-mono downmix.
Standard 50/15
s de-emphasis is available for sam-
pling rates of 32, 44.1, and 48 kHz for compatibility with
digital audio programs mastered using the 50/15
s pre-
emphasis technique.
Integrated level translators allow easy interfacing be-
tween the CS4271 and other devices operating over a
wide range of logic levels.
An on-chip oscillator eliminates the need for an external
crystal oscillator circuit. This can reduce overall design
cost and conserve circuit board space. The CS4271 au-
tomatically uses the on-chip oscillator in the absence of
an applied master clock, making this feature easy to
use.
Independently addressable high-pass filters are avail-
able for the right and left channel of the A/D. This allows
the A/D to be used in a wide variety of applications
where one audio channel and one DC measurement
channel is desired.
The CS4271's wide dynamic range, negligible distor-
tion, and low noise make it ideal for applications such as
A/V receivers, DVD-R, CD-R, digital mixing consoles,
effects processors, set-top box systems, and automo-
tive audio systems.
ORDERING INFORMATION
CS4271-CZ
-10 to 70 C
28-pin TSSOP
CS4271-DZ
-40 to 85 C
28-pin TSSOP
CDB4271
Evaluation Board
CS4271
3
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - SOFTWARE MODE ............................................................................. 6
2. PIN DESCRIPTIONS - STAND-ALONE MODE ....................................................................... 8
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................... 10
SPECIFIED OPERATING CONDITIONS ............................................................................... 10
ABSOLUTE MAXIMUM RATINGS ......................................................................................... 10
DAC ANALOG CHARACTERISTICS - (CS4271-CZ) ............................................................ 11
DAC ANALOG CHARACTERISTICS - (CS4271-DZ) ............................................................ 12
DAC ANALOG FILTER RESPONSE...................................................................................... 13
ADC ANALOG CHARACTERISTICS - (CS4271-CZ) ............................................................ 15
ADC ANALOG CHARACTERISTICS - (CS4271-DZ) ............................................................ 16
ADC DIGITAL FILTER CHARACTERISTICS......................................................................... 17
DC ELECTRICAL CHARACTERISTICS - (CS4271-CZ)........................................................ 18
DC ELECTRICAL CHARACTERISTICS - (CS4271-DZ)........................................................ 18
DIGITAL CHARACTERISTICS............................................................................................... 19
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT................................................. 20
SWITCHING CHARACTERISTICS - I2C MODE CONTROL PORT ...................................... 23
SWITCHING CHARACTERISTICS - SPI CONTROL PORT ................................................. 24
4. TYPICAL CONNECTION DIAGRAM ..................................................................................... 25
5. APPLICATIONS ..................................................................................................................... 26
5.1 Stand-Alone Mode ........................................................................................................... 26
5.1.1 Recommended Power-Up Sequence ................................................................. 26
5.1.2 Master/Slave Mode ............................................................................................. 26
5.1.3 System Clocking ................................................................................................. 26
5.1.3.1 Crystal Applications (XTI/XTO) ........................................................... 26
5.1.3.2 Clock Ratio Selection .......................................................................... 27
5.1.4 16-Bit Auto-Dither ............................................................................................... 28
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to
www.cirrus.com
IIMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its
subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without
notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to
verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of
third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask
work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained here-
in and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of
Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for
resale.
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terial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANT-
ED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS
OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE
SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOM-
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MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF
THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER
AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM
ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-
marks or service marks of their respective owners.
I2C is a registered trademark of Philips Semiconductor. Purchase of I2C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies
conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system.
CS4271
4
5.1.5 Auto-Mute ............................................................................................................ 28
5.1.6 High Pass Filter ................................................................................................... 28
5.1.7 Interpolation Filter .............................................................................................. 28
5.1.8 Mode Selection & De-Emphasis ......................................................................... 28
5.1.9 Serial Audio Interface Format Selection .............................................................. 28
5.2 Control Port Mode ............................................................................................................ 29
5.2.1 Recommended Power-Up Sequence - Access to Control Port Mode ................. 29
5.2.2 Master / Slave Mode Selection ........................................................................... 29
5.2.3 System Clocking ................................................................................................. 29
5.2.3.1 Crystal Applications (XTI/XTO) ........................................................... 29
5.2.3.2 Clock Ratio Selection .......................................................................... 30
5.2.4 Internal Digital Loopback ..................................................................................... 32
5.2.5 Dither for 16-Bit Data .......................................................................................... 32
5.2.6 Auto-Mute ............................................................................................................ 32
5.2.7 High Pass Filter and DC Offset Calibration ......................................................... 32
5.2.8 Interpolation Filter .............................................................................................. 33
5.2.9 De-Emphasis ....................................................................................................... 33
5.2.10 Oversampling Modes ........................................................................................ 33
5.3 De-Emphasis Filter .......................................................................................................... 33
5.4 Analog Connections ......................................................................................................... 34
5.4.1 Input Connections ............................................................................................... 34
5.4.2 Output Connections ............................................................................................ 35
5.5 Mute Control .................................................................................................................... 36
5.6 Synchronization of Multiple Devices ................................................................................ 36
5.7 Grounding and Power Supply Decoupling ....................................................................... 36
6. CONTROL PORT INTERFACE .............................................................................................. 37
6.1 SPI Mode ......................................................................................................................... 37
6.2 I2C Mode ......................................................................................................................... 38
7. REGISTER QUICK REFERENCE .......................................................................................... 39
8. REGISTER DESCRIPTION .................................................................................................... 40
8.1 Mode Control 1 - Address 01h ......................................................................................... 40
8.1.1 Functional Mode (Bits 7:6) .................................................................................. 40
8.1.2 Ratio Select (Bits 5:4) ......................................................................................... 40
8.1.3 Master / Slave Mode (Bit 3) ................................................................................. 40
8.1.4 DAC Digital Interface Format (Bits 2:0) ............................................................... 40
8.2 DAC Control - Address 02h ............................................................................................. 41
8.2.1 Auto-Mute (Bit 7) ................................................................................................. 41
8.2.2 Interpolation Filter Select (Bit 6) .......................................................................... 41
8.2.3 De-Emphasis Control (Bits 5:4) ........................................................................... 41
8.2.4 Soft Volume Ramp-Up After Error (Bit 3) ............................................................ 42
8.2.5 Soft Ramp-Down Before Filter Mode Change (Bit 2) .......................................... 42
8.2.6 Invert Signal Polarity (Bits 1:0) ............................................................................ 42
8.3 DAC Volume & Mixing Control - Address 03h ................................................................. 42
8.3.1 Channel B Volume = Channel A Volume (Bit 6) ................................................. 42
8.3.2 Soft Ramp or Zero Cross Enable (Bits 5:4) ......................................................... 42
8.3.3 ATAPI Channel Mixing and Muting (Bits 3:0) ...................................................... 43
8.4 DAC Channel A Volume Control - Address 04h .............................................................. 44
8.5 DAC Channel B Volume Control - Address 05h .............................................................. 44
8.5.1 Mute (Bit 7) .......................................................................................................... 44
8.5.2 Volume Control (Bits 6:0) .................................................................................... 44
8.6 ADC Control - Address 06h ............................................................................................. 45
8.6.1 Dither for 16-Bit Data (Bit 5) ................................................................................ 45
8.6.2 ADC Digital Interface Format (Bit 4) .................................................................... 45
CS4271
5
8.6.3 ADC Channel A & B Mute (Bits 3:2) ................................................................... 45
8.6.4 Channel A & B High Pass Filter Disable (Bits 1:0) .............................................. 45
8.7 Mode Control 2 - Address 07h ......................................................................................... 45
8.7.1 Digital Loopback (Bit 4) ....................................................................................... 45
8.7.2 AMUTEC = BMUTEC (Bit 3) ............................................................................... 45
8.7.3 Freeze (Bit 2) ...................................................................................................... 46
8.7.4 Control Port Enable (Bit 1) .................................................................................. 46
8.7.5 Power Down (Bit 0) ............................................................................................. 46
8.8 Chip ID - Register 08h ..................................................................................................... 46
9. PARAMETER DEFINITIONS .................................................................................................. 47
10. ORDERING INFORMATION ................................................................................................ 47
11. PACKAGE DIMENSIONS .................................................................................................... 48
12. APPENDIX ............................................................................................................................ 49
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