Preliminary Product Information

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright

Cirrus Logic, Inc. 2001

P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com

JUN `01

DS318PP5

CS4297A

Features

AC '97 2.1 Compatible

Industry Leading Mixed Signal Technology

20-bit Stereo Digital-to-Analog Converters

18-bit Stereo Analog-to-Digital Converters

Four Analog Line-level Stereo Inputs for
LINE_IN, CD, VIDEO, and AUX

Two Analog Line-level Mono Inputs for
Modem and Internal PC Beep

Dual Stereo Line-level Outputs for
LINE_OUT and ALT_LINE_OUT

Dual Microphone Inputs

High Quality Pseudo-Differential CD Input

Extensive Power Management Support

Meets or Exceeds the Microsoft

PC 99

Audio Performance Requirements

S/PDIF Digital Audio Output

CrystalClear

3D Stereo Enhancement

Description

The CS4297A is an AC '97 2.1 compatible stereo audio
codec designed for PC multimedia systems. Using the
industry leading CrystalClear

delta-sigma and mixed

signal technology, the CS4297A enables the design of
PC 99-compliant desktop, portable, and entertainment
PCs.

Coupling the CS4297A with a PCI audio accelerator or
core logic supporting the AC '97 interface, implements a
cost effective, superior quality, audio solution. The
CS4297A surpasses PC 99 and AC '97 2.1 audio quality
standards.

ORDERING INFO

CS4297A-KQ 48-pin TQFP

9x9x1.4 mm

CS4297A-JQ 48-pin TQFP

9x9x1.4 mm

AC'97

REGISTERS

LINE
CD
AUX
VIDEO

MIC1

MIC2

PHONE

PC_BEEP

LINE_OUT
ALT_LINE_OUT
MONO_OUT

ANALOG INPUT MUX

AND OUTPUT MIXER

AC-LINK AND AC'97

REGISTERS

GAIN / MUTE CONTROLS

INPUT

MUX

OUTPUT

MIXER

MIXER / MUX SELECTS

AC-

LINK

PWR

MGT

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

PCM_DATA

DAC

20 bits

ADC

18 bits

S/PDIF

PCM_DATA

CrystalClear

SoundFusion

Audio Codec '97

CS4297A

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS .................................................................5

Analog Characteristics ........................................................................................................5
Mixer Characteristics ..........................................................................................................6
Absolute Maximum Ratings ................................................................................................6
Recommended Operating Conditions.................................................................................6
Digital Characteristics .........................................................................................................6
AC '97 Serial Port Timing....................................................................................................7

2. GENERAL DESCRIPTION ...............................................................................................10

2.1 AC-Link ....................................................................................................................10
2.2 Control registers ......................................................................................................10
2.3 Output Mixer .............................................................................................................11
2.4 Input Mux .................................................................................................................11
2.5 Volume Control ........................................................................................................11

3. AC LINK FRAME DEFINITION .........................................................................................13

3.1 AC-Link Serial Data Output Frame ..........................................................................14

3.1.1 Serial Data Output Slot Tags (Slot 0) ...........................................................14
3.1.2 Command Address Port (Slot 1) ..................................................................15
3.1.3 Command Data Port (Slot 2) ........................................................................15
3.1.4 PCM Playback Data (Slots 3-10) .................................................................15

3.2 AC-Link Audio Input Frame ......................................................................................16

3.2.5 Serial Data Input Slot Tag Bits (Slot 0) .......................................................16
3.2.6 Status Address Port (Slot 1) .........................................................................16
3.2.7 Status Data Port (Slot 2) ..............................................................................17
3.2.8 PCM Capture Data (Slot 3-10) .....................................................................17

3.3 AC-Link Protocol Violation - Loss of SYNC ..............................................................18

4. REGISTER INTERFACE ..................................................................................................19

4.3 Reset Register (Index 00h) ......................................................................................20
4.4 Master Volume Register (Index 02h) .......................................................................20
4.5 Alternate Volume Register (Index 04h) ....................................................................21
4.6 Mono Volume Register (Index 06h) .........................................................................21
4.7 PC_BEEP Volume Register (Index 0Ah) .................................................................22
4.8 Phone Volume Register (Index 0Ch) ........................................................................22
4.9 Microphone Volume Register (Index 0Eh) ................................................................23

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm

Microsoft is a registered trademark of Microsoft Corporation in the United States and/or other countries.
Intel is a registered trademark of Intel Corporation.
Crystal Clear and Sound Fusion are trademarks of Cirrus Logic.

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the infor-
mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without
warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or
other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets.
No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, pho-
tographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user.
However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (elec-
tronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a
basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors
and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list
of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

CS4297A

4.10 Stereo Analog Mixer Input Gain Registers (Index 10h - 18h) ................................. 24
4.11 Input Mux Select Register (Index 1Ah) ................................................................... 25
4.12 Record Gain Register (Index 1Ch) ......................................................................... 25
4.13 General Purpose Register (Index 20h) ................................................................... 26
4.14 3D Control Register (Index 22h) ............................................................................. 26
4.15 Powerdown Control/Status Register (Index 26h) ................................................... 27
4.16 Extended Audio ID Register (Index 28h) ................................................................ 28
4.17 PCM Front DAC Rate Register (Index 2Ch) ........................................................ 28
4.18 PCM L/R ADC Rate Register (Index 32h) .............................................................. 28
4.19 AC Mode Control Register (Index 5Eh) .................................................................. 29
4.20 Misc. Crystal Control Register (Index 60h) ............................................................. 29
4.21 S/PDIF Control Register (Index 68h) ..................................................................... 30
4.22 Vendor ID1 Register (Index 7Ch) ........................................................................... 31
4.23 Vendor ID2 Register (Index 7Eh) ........................................................................... 31

5. POWER MANAGEMENT ................................................................................................. 32

5.1 AC '97 Reset Modes ................................................................................................ 32

5.1.1 Cold AC `97 Reset ....................................................................................... 32
5.1.2 Warm AC '97 Reset ..................................................................................... 32
5.1.3 Register AC '97 Reset ................................................................................. 32

5.2 Powerdown Controls ................................................................................................ 33

6. ANALOG HARDWARE DESCRIPTION ......................................................................... 35

6.1 Analog Inputs ........................................................................................................... 35

6.1.4 Line-Level Inputs ........................................................................................ 35
6.1.5 CD Input ..................................................................................................... 35
6.1.6 Microphone Inputs ...................................................................................... 36
6.1.7 PC Beep Input ............................................................................................ 36
6.1.8 Phone Input ................................................................................................ 37

6.2 Analog Outputs ........................................................................................................ 37

6.2.9 Stereo Outputs ........................................................................................... 37
6.2.10 Mono Output ............................................................................................. 37

6.3 Miscellaneous Analog Signals ................................................................................. 38
6.4 Power Supplies ........................................................................................................ 38
6.5 Reference Design .................................................................................................... 38

7. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) ............................................................ 39
8. GROUNDING AND LAYOUT .......................................................................................... 39
9. PIN DESCRIPTIONS

10. PARAMETER AND TERM DEFINITIONS .................................................................... 46
11. REFERENCE DESIGN ................................................................................................. 48
12. REFERENCES .............................................................................................................. 49
13. PACKAGE DIMENSIONS ............................................................................................. 50

LIST OF FIGURES

Figure 1. Power Up Timing ....................................................................................................... 8
Figure 2. Codec Ready from Startup or Fault Condition ........................................................... 8
Figure 3. Clocks ........................................................................................................................ 8
Figure 4. Data Setup and Hold.................................................................................................. 9
Figure 5. PR4 Powerdown and Warm Reset ............................................................................ 9
Figure 6. Test Mode .................................................................................................................. 9
Figure 7. AC-link Connections ................................................................................................ 10
Figure 8. Mixer Diagram.......................................................................................................... 12
Figure 9. AC-link Input and Output Framing ........................................................................... 13
Figure 10. Line Input (Replicate for Video and Aux) ............................................................... 35

CS4297A

Figure 11. Differential 2 VRMS CD Input ................................................................................35
Figure 12. Differential 1 VRMS CD Input ................................................................................35
Figure 13. Microphone Input ...................................................................................................36
Figure 14. Microphone Pre-amplifier .......................................................................................36
Figure 15. PC_BEEP Input......................................................................................................36
Figure 16. Modem Connection ................................................................................................37
Figure 17. Alternate Line Output as Headphone Output .........................................................37
Figure 18. Stereo Output.........................................................................................................37
Figure 19. Voltage Regulator ..................................................................................................38
Figure 20. S/PDIF Output........................................................................................................39
Figure 21. Conceptual Layout for the CS4297A......................................................................40
Figure 22. Pin Locations for the CS4297A ..............................................................................41
Figure 23. CS4297A Reference Design ..................................................................................48

LIST OF TABLES

Table 1. Mixer Registers .........................................................................................................19
Table 2. Analog Mixer Output Attenuation ..............................................................................21
Table 3. Microphone Input Gain Values ..................................................................................23
Table 4. Analog Mixer Input Gain Values................................................................................24
Table 5. Stereo Volume Register Index ..................................................................................24
Table 6. Input Mux Selection...................................................................................................25
Table 7. Slot Mapping ............................................................................................................29
Table 8. Device ID with Corresponding Part Number .............................................................31
Table 9. Revision Values.........................................................................................................31
Table 10. Powerdown PR Bit Functions..................................................................................33
Table 11. Powerdown PR Function Matrix ..............................................................................34
Table 12. Power Consumption by Powerdown Mode .............................................................34

CS4297A

1. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS

Standard test conditions unless otherwise noted: T

ambient

= 25° C,

AVdd = 5.0 V ±5%, DVdd = 3.3 V ±5%; 1 kHz Input Sine wave; Sample Frequency, Fs = 48 kHz; Z

=100 k

1000 pF load, C

= 18 pF load (Note 1); Measurement bandwidth is 20 Hz - 20 kHz, 18-bit linear coding for ADC

functions, 20-bit linear coding for DAC functions; Mixer registers set for unity gain.

Notes: 1. Z

refers to the analog output pin loading and C

refers to the digital output pin loading.

2. Parameter definitions are given in the Section 10, Parameter and Term Definitions.

3. Path refers to the signal path used to generate this data. These paths are defined in the Section 10,

Parameter and Term Definitions.

4. This specification is guaranteed by silicon characterization, it is not production tested.

Parameter

(Note 2)

Symbol

Path

(Note 3)

CS4297A-KQ

CS4297A-JQ

Unit

Min Typ

Max

Min Typ

Max

Full Scale Input Voltage
Line Inputs
Mic Inputs
Mic Inputs

(20 dB internal gain)

A-D
A-D
A-D

0.91
0.91

0.091

1.00
1.00
0.10

-
-
-

0.91
0.91

0.091

1.00
1.00
0.10

-
-
-

RMS

Full Scale Output Voltage
Line,Alternate Line, and Mono Outputs

D-A

0.91

1.0

1.13

0.91

1.0

1.13

RMS

Frequency Response

(Note 4)

Analog

Ac = ± 0.25 dB

DAC

Ac = ± 0.25 dB

ADC

Ac = ± 0.25 dB

A-A

D-A
A-D

20
20
20

-
-
-

20,000
20,000
20,000

20
20
20

-
-
-

20,000
20,000
20,000

Hz
Hz
Hz

Dynamic Range
Stereo Analog inputs to LINE_OUT
Mono Analog inputs to LINE_OUT
DAC Dynamic Range
ADC Dynamic Range

A-A
A-A

D-A
A-D

90
85
85
85

95
90
90
90

-
-
-
-

90
85
87
85

-
-
-
-

dB FS A
dB FS A
dB FS A
dB FS A

DAC SNR (-20 dB FS input w/
CCIR-RMS filter on output)

SNR

D-A

Total Harmonic Distortion + Noise
(-3 dB FS input signal):
Line/Alternate Line Output
DAC
ADC

(all inputs except phone/mic)

ADC

(phone/mic)

THD+N

A-A

D-A
A-D
A-D

-
-
-
-

-90
-91
-88
-84

-80
-80
-80
-74

-
-
-
-

-74
-74
-74
-74

dB FS
dB FS
dB FS
dB FS

Power Supply Rejection Ratio
(1 kHz, 0.5 V

RMS

w/ 5 V DC offset)(Note 4)

Interchannel Isolation

Spurious Tone

(Note 4)

-100

dB FS

Input Impedance

(Note 4)

External Load Impedance

Output Impedance

(Note 4)

730

Input Capacitance

(Note 4)

Vrefout

2.0

2.28

2.5

2.0

2.28

2.5

CS4297A

MIXER CHARACTERISTICS

(for

CS4297A

-KQ only)

ABSOLUTE MAXIMUM RATINGS

(AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

RECOMMENDED OPERATING CONDITIONS

(AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

DIGITAL CHARACTERISTICS

(AVss = DVss = 0 V)

Parameter

Min Typ

Max

Unit

Mixer Gain Range Span
Line In, Aux, CD, Video, Mic1, Mic2, Phone, PC Beep
Mono Out, Alternate Line Out
Line Out

-
-
-

46.5
46.5
94.5

-
-
-

dB
dB
dB

Step Size
All volume controls except PC Beep
PC Beep

-
-

1.5
3.0

-
-

dB
dB

Parameter

Min Typ

Max

Unit

Power Supplies

+3.3 V Digital

+5 V Digital

Analog

-0.3
-0.3
-0.3

-
-
-

6.0
6.0
6.0

V
V
V

Total Power Dissipation

(Supplies, Inputs, Outputs)

1.25

Input Current per Pin

(Except Supply Pins)

-10

Output Current per Pin

(Except Supply Pins)

-15

Analog Input voltage

-0.3

AVdd+

0.3

Digital Input voltage

-0.3

DVdd +

0.3

Ambient Temperature

(Power Applied)

-55

110

°C

Storage Temperature

-65

150

°C

Parameter

Symbol

Min Typ

Max

Unit

Power Supplies

+3.3 V Digital

+5 V Digital

Analog

DVdd1, DVdd2
DVdd1, DVdd2

AVdd1, AVdd2

3.135

4.75
4.75

3.3

5
5

3.465

5.25
5.25

V
V
V

Operating Ambient Temperature

°C

Parameter

Symbol

Min

Typ

Max

Unit

Low level input voltage

0.8

High level input voltage

0.65 x DVdd

High level output voltage

0.90 x DVdd

0.99 x DVdd

Low level output voltage

0.03

0.10 x DVdd

Input Leakage Current (AC-link inputs)

-10

µA

Output Leakage Current (Tri-stated AC-link outputs)

-10

µA

Output buffer drive current
BIT_CLK, S/PDIF_OUT
SDATA_IN, EAPD

(Note 4)

-
-

mA
mA

CS4297A

AC '97 SERIAL PORT TIMING

Standard test conditions unless otherwise noted: T

ambient

= 25° C,

AVdd = 5.0 V, DVdd = 3.3 V; C

= 55 pF load.

Parameter

Symbol

Min

Typ

Max

Unit

RESET Timing

RESET# active low pulse width

rst_low

1.0

µs

RESET# inactive to BIT_CLK start-up delay

rst2clk

40.0

µs

1st SYNC active to CODEC READY set

sync2crd

62.5

µs

Vdd stable to Reset inactive

vdd2rst#

100

µs

Clocks

BIT_CLK frequency

clk

12.288

MHz

BIT_CLK period

clk_period

81.4

BIT_CLK output jitter (depends on XTAL_IN source)

750

BIT_CLK high pulse width

clk_high

40.7

BIT_CLK low pulse width

clk_low

40.7

SYNC frequency

sync

kHz

SYNC period

sync_period

20.8

µs

SYNC high pulse width

sync_high

1.3

µs

SYNC low pulse width

sync_low

19.5

µs

Data Setup and Hold

Output Propagation delay from rising edge of BIT_CLK

Input setup time from falling edge of BIT_CLK

isetup

Input hold time from falling edge of BIT_CLK

ihold

Input Signal rise time

irise

Input Signal fall time

ifall

Output Signal rise time

(Note 4)

orise

Output Signal fall time

(Note 4)

ofall

Misc. Timing Parameters

End of Slot 2 to BIT_CLK, SDATA_IN low (PR4)

s2_pdown

.28

1.0

µs

SYNC pulse width (PR4) Warm Reset

sync_pr4

1.0

µs

SYNC inactive (PR4) to BIT_CLK start-up delay

sync2clk

162.8

285

Setup to trailing edge of RESET# (ATE test mode) (Note 4)

setup2rst

Rising edge of RESET# to Hi-Z delay

(Note 4)

off

CS4297A

2. GENERAL DESCRIPTION

The CS4297A is a mixed-signal serial audio Codec
compliant to the Intel

Audio Codec `97 Specifica-

tion, revision 2.1 [1]. It is designed to be paired
with a digital controller, typically located on the
PCI bus or integrated within the system core logic
chip set. The controller is responsible for all com-
munications between the CS4297A and the remain-
der of the system. The CS4297A contains two
distinct functional sections: digital and analog. The
digital section includes the AC-link interface,
S/PDIF interface, serial data port, and power man-
agement support. The analog section includes the
analog input multiplexer (mux), stereo output mix-
er, mono output mixer, stereo Analog-to-Digital
Converters (ADCs), stereo Digital-to-Analog Con-
verters (DACs), and their associated volume con-
trols.

2.1

AC-Link

All communication with the CS4297A is estab-
lished with a 5-wire digital interface to the control-
ler, as shown in Figure 7. This interface is called
the AC-link. All clocking for the serial communi-
cation is synchronous to the BIT_CLK signal.
BIT_CLK is generated by the primary audio codec
and is used to clock the controller and any second-

ary audio codecs. Both input and output AC-link
audio frames are organized as a sequence of 256 se-
rial bits forming 13 groups referred to as `slots'.
During each audio frame, data is passed bi-direc-
tionally between the CS4297A and the controller.
The input frame is driven from the CS4297A on the
SDATA_IN line. The output frame is driven from
the controller on the SDATA_OUT line. The con-
troller is also responsible for issuing reset com-
mands via the RESET# signal. Following a Cold
Reset, the CS4297A is responsible for notifying the
controller that it is ready for operation after syn-
chronizing its internal functions. The CS4297A
AC-link signals must use the same digital supply
voltage as the controller chip, either +5 V or
+3.3 V. See Section 3, AC Link Frame Definition,
for detailed AC-link information.

2.2

Control registers

The CS4297A contains a set of AC '97 compliant
control registers and a set of Cirrus Logic defined
control registers. These registers control the basic
functions and features of the CS4297A. Read ac-
cesses of the control registers by the AC '97 con-
troller are accomplished with the requested register
index in Slot 1 of a SDATA_OUT frame. The fol-
lowing SDATA_IN frame will contain the read

CODEC

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

Digital AC'97

Controller

Figure 7. AC-link Connections

CS4297A

data in its Slot 2. Write operations are similar, with
the register index in Slot 1 and the write data in Slot
2 of a SDATA_OUT frame. The function of each
input and output frame is detailed in Section 3,
AC Link Frame Definition. Individual register de-
scriptions are found in Section 4, Register Inter-
face.

2.3

Output Mixer

The CS4297A has two output mixers, illustrated in
Figure 8. The stereo output mixer sums together
the analog inputs to the CS4297A, including the
PC_BEEP and PHONE signals, according to the
settings in the volume control registers. The stereo
output mix is sent to the LINE_OUT and
ALT_LINE_OUT pins on the CS4297A. The
mono output mixer generates a monophonic sum of
the left and right channels from the stereo input
mixer. The mono output mix is sent to the
MONO_OUT output pin on the CS4297A.

2.4

Input Mux

The input multiplexer controls which analog input
is sent to the ADCs. The output of the input mux is
converted to stereo 18-bit digital PCM data and
sent to the controller by means of the AC-link
SDATA_IN signal.

2.5

Volume Control

The CS4297A volume registers control analog in-
put levels to the input mixer and analog output lev-
els, including the master volume level, and the
alternate volume level. The PC_BEEP volume con-
trol uses 3 dB steps with a range of 0 dB to -45 dB
attenuation. All other analog volume controls use
1.5 dB steps. The analog inputs have a mixing
range of +12 dB signal gain to -34.5 dB signal at-
tenuation. The analog output volume controls have
from 0 dB to -94.5 dB attenuation for LINE_OUT
and from 0 dB to -46.5 dB attenuation for
ALT_LINE_OUT and MONO_OUT.

CS4297A

3. AC LINK FRAME DEFINITION

The AC-link is a bidirectional serial port with data
organized into frames consisting of one 16-bit and
twelve 20-bit time-division multiplexed slots. The
first slot, called the tag slot, contains bits indicating
if the CS4297A is ready to receive data (input
frame) and which, if any, other slots contain valid
data. Slots 1 through 12 contain audio or con-
trol/status data. Both the serial data output and in-
put frames are defined from the controller
perspective, not from the CS4297A perspective.

The controller synchronizes the beginning of a
frame with the assertion of the SYNC signal.

Figure 9 shows the position of each bit location
within the frame. The first bit position in a new se-
rial data frame is F0 and the last bit position in the
serial data frame is F255. When SYNC goes active
(high) and is sampled active by the CS4297A (on
the falling edge of BIT_CLK), both devices are
synchronized to a new serial data frame. The data
on the SDATA_OUT pin at this clock edge is the
final bit of the previous frame's serial data. On the
next rising edge of BIT_CLK, the first bit of Slot 0
is driven by the controller on the SDATA_OUT
pin. On the next falling edge of BIT_CLK, the
CS4297A latches this data in, as the first bit of the
frame.

20.8

µs

(48 kHz)

Tag Phase

Data Phase

12.288 MHz

81.4 ns

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

F16

F15

F14

F13

F12

F35

F56

F76

D19

F255

Valid

Frame

Slot 1

Valid

R/W

WD15

F36

F57

D19

D18

D19

D18

D19

RD15

F16

F15

F14

F13

F12

F35

F56

F76

F255

F36

F57

F255

GPIO

INT

F96

D19

Slot 0

Slot 1

Slot 2

Slot 3

Slot 4

Slots 5-12

Slot 2

Valid

Slot 1

Valid

Slot 2

Valid

Codec
Ready

Slot 12

Valid

Codec

ID1

Codec

ID0

Slot 12

Valid

GPIO

INT

Bit Frame Position:

Figure 9. AC-link Input and Output Framing

CS4297A

3.1

AC-Link Serial Data Output Frame

In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4297A from the AC '97
controller. Figure 9 illustrates the serial port timing.

The PCM playback data being passed to the CS4297A is shifted out MSB first in the most significant bits
of each slot. Any PCM data from the AC '97 controller that is not 20 bits wide should be left justified in
its corresponding slot and dithered or zero-padded in the unused bit positions.

Bits that are reserved should always be `cleared' by the AC '97 controller.

3.1.1

Serial Data Output Slot Tags (Slot 0)

Valid Frame

The Valid Frame bit determines if any of the following slots contain either valid playback data

for the CS4297A DACs or data for read/write operations. When `set', at least one of the other
AC-link slots contain valid data. If this bit is `clear', the remainder of the frame is ignored.

Slot [1:2] Valid

The Slot [1:2] Valid bits indicate the validity of data in their corresponding serial data output

slots. If a bit is `set', the corresponding output slot contains valid data. If a bit is `cleared', the
corresponding slot will be ignored.

Slot [3:10] Valid

The Slot [3:10] Valid bits indicate Slot [3:10] contains valid playback data for the CS4297A. If a

Slot Valid bit is `set', the named slot contains valid audio data. If the bit is `clear', the slot will be
ignored. The CS4297A supports alternate slot mapping as defined in the AC '97 2.1 specifica-
tion. For more information, see the AC Mode Control Register (Index 5Eh).

Codec ID[1:0]

The Codec ID[1:0] bits display the Codec ID of the audio codec being accessed during the cur-
rent AC-link frame. Codec ID[1:0] = 00 indicates the primary codec is being accessed. Codec
ID[1:0] = 01, 10, or 11 indicates one of three possible secondary codecs is being accessed. A
non-zero value of one or more of the Codec ID bits indicates a valid Read or Write Address in
Slot 1, and the Slot 1 R/W bit indicates presence or absence of valid Data in Slot 2.

Bit 15

Valid

Frame

Slot 1

Valid

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Slot 5

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

Slot 10

Valid

Reserved

Codec

ID1

Codec

ID0

CS4297A

3.1.2

Command Address Port (Slot 1)

R/W Read/Write. When this bit is `set', a read of the AC '97 register specified by the register index

bits will occur in the AC '97 2.1 audio codec. When the bit is `cleared', a write will occur. For any
read or write access to occur, the Frame Valid bit (F0) must be `set' and the Codec ID[1:0] bits
(F[14:15]) must match the Codec ID of the AC '97 2.1 audio codec being accessed. Additionally,
for a primary codec, the Slot 1 Valid bit (F1) must be `set' for a read access and both the Slot 1
Valid bit (F1) and the Slot 2 Valid bit (F2) must be `set' for a write access. For a secondary co-
dec, both the Slot 1 Valid bit (F1) and the Slot 2 Valid bit (F2) must be `cleared' for read and
write accesses. See Figure 9 for bit frame positions.

RI[6:0]

CS4297A. All registers are defined at word addressable boundaries. The RI0 bit must be `clear'
to access CS4297A registers.

3.1.3

Command Data Port (Slot 2)

WD[15:0]

Write Data. The WD[15:0] bits contain the 16-bit value to be written to the register. If an access
is a read, this slot is ignored.

NOTE:

For any write to an AC '97 register, the write is defined to be an `atomic' access. This means

that when the Slot 1 Valid bit in output Slot 0 is `set', the Slot 2 Valid bit in output slot 0 should
always be `set' during the same audio frame. No write access may be split across 2 frames.

3.1.4

PCM Playback Data (Slots 3-10)

PD[19:0]

Playback Data. The PD[19:0] bits contain the 20-bit PCM playback (2's complement) data for

the left and right DACs and/or the S/PDIF transmitter. Table 7 on page 29 lists a cross reference
for each function and its respective slot. The mapping of a given slot to a DAC is determined by
the state of the ID[1:0] bits in the Extended Audio ID Register (Index 28h) and by the SM[1:0]
and AMAP bits in the AC Mode Control Register (Index 5Eh).

Bit 19

R/W

RI6

RI5

RI4

RI3

RI2

RI1

RI0

Bit 19

WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0

Reserved

Bit 19

PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

CS4297A

3.2

AC-Link Audio Input Frame

In the serial data input frame, data is passed on the SDATA_IN pin from the CS4297A to the AC '97 con-
troller. The data format for the input frame is very similar to the output frame. Figure 9 on page 13 illus-
trates the serial port timing.

The PCM capture data from the CS4297A is shifted out MSB first in the most significant 18 bits of each
slot. The least significant 2 bits in each slot will be `cleared'. If the host requests PCM data from the
AC '97 Controller that is less than 18 bits wide, the controller should dither and round or just round (but
not truncate) to the desired bit depth.

Bits that are reserved or not implemented in the CS4297A will always be returned `cleared'.

3.2.1

Serial Data Input Slot Tag Bits (Slot 0)

Codec Ready

The Codec Ready bit indicates the readiness of the CS4297A AC-link. Immediately after a
Cold Reset this bit will be `clear'. Once the CS4297A clocks and voltages are stable, this bit
will be `set'. Until the Codec Ready bit is `set', no AC-link transactions should be attempted
by the controller. The Codec Ready bit does not indicate readiness of the DACs, ADCs, Vref,
or any other analog function. Those must be checked in the Powerdown Control/Status Reg-
ister (Index 26h) by the controller before any access is made to the mixer registers. Any ac-
cesses to the CS4297A while Codec Ready is `clear' are ignored.

Slot 1 Valid

When `set', the Slot 1 Valid bit indicates Slot 1 contains a valid read back address.

Slot 2 Valid

When `set', the Slot 2 Valid bit indicates Slot 2 contains valid register read data.

Slot [3:10] Valid

When `set', the Slot [3:10] Valid bits indicate Slot [3:10] contains valid capture data from the

CS4297A ADCs. Only if a Slot [3:10] Valid bit is `set' will the corresponding input slot contain
valid data.

3.2.2

Status Address Port (Slot 1)

RI[6:0]

Register Index. The RI[6:0] bits echo the AC '97 register address when a register read has
been requested in the previous frame. The CS4297A will only echo the register index for a
read access. Write accesses will not return valid data in Slot 1.

Bit 15

Codec
Ready

Slot 1

Valid

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Slot 5

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

Slot 10

Valid

Bit 19

RI6

RI5

RI4

RI3

RI2

RI1

RI0

Reserved

CS4297A

4. REGISTER INTERFACE

Reg

Register Name

D15 D14 D13 D12 D11 D10

D0 Default

00h

Reset

SE4 SE3 SE2 SE1 SE0

ID8

ID7

ID4

1990h

02h

Master Volume

Mute

ML5 ML4 ML3 ML2

ML1 ML0

MR5 MR4 MR3 MR2

MR1

MR0

8000h

04h

Alternate Volume

Mute

ML5 ML4 ML3 ML2

ML1 ML0

MR5 MR4 MR3 MR2

MR1

MR0

8000h

06h

Mono Volume

Mute

MM5 MM4 MM3 MM2 MM1 MM0

8000h

0Ah PC_BEEP Volume

Mute

PV3

PV2

PV1

PV0

0000h

0Ch Phone Volume

Mute

GN4 GN3

GN2

GN1

GN0

8008h

0Eh Mic Volume

Mute

20dB

GN4 GN3

GN2

GN1

GN0

8008h

10h

Line In Volume

Mute

GL4 GL3 GL2

GL1

GL0

GR4 GR3

GR2

GR1

GR0

8808h

12h

CD Volume

Mute

GL4 GL3 GL2

GL1

GL0

GR4 GR3

GR2

GR1

GR0

8808h

14h

Video Volume

Mute

GL4 GL3 GL2

GL1

GL0

GR4 GR3

GR2

GR1

GR0

8808h

16h

Aux Volume

Mute

GL4 GL3 GL2

GL1

GL0

GR4 GR3

GR2

GR1

GR0

8808h

18h

PCM Out Volume

Mute

GL4 GL3 GL2

GL1

GL0

GR4 GR3

GR2

GR1

GR0

8808h

1Ah Record Select

SL2

SL1

SL0

SR2

SR1

SR0

0000h

1Ch Record Gain

Mute

GL3 GL2

GL1

GL0

GR3

GR2

GR1

GR0

8000h

20h

General Purpose

MIX

LPBK

0000h

22h

3D Control

0000h

26h

Powerdown Ctrl/Stat

EAPD

PR6 PR5 PR4 PR3 PR2

PR1 PR0

REF

ANL

DAC

ADC

000Fh

28h

Extended Audio ID

ID1

ID0

AMAP

VRA

0201h

2Ch PCM Front DAC Rate

SR15 SR14 SR13 SR12 SR11 SR10

SR9 SR8 SR7 SR6 SR5 SR4 SR3

SR2

SR1

SR0

BB80h

32h

PCM L/R ADC Rate

SR15 SR14 SR13 SR12 SR11 SR10

SR9 SR8 SR7 SR6 SR5 SR4 SR3

SR2

SR1

SR0

BB80h

Cirrus Logic Defined Registers:

AC Mode Control

DDM AMAP

SM1 SM0

0080h

Misc. Crystal Control

Reserved

LOSM

0023h

S/PDIF Control

SPEN

Val

CC6 CC5 CC4 CC3 CC2 CC1 CC0

Emph

Copy

/Audio

Pro

0000h

7Ch Vendor ID1(CR)

4352h

7Eh Vendor ID2(Y-)

DID2 DID1 DID0

REV2

REV1 REV0

5931h

Table 1. Mixer Registers

CS4297A

4.1

Reset Register (Index 00h)

SE[4:0]

Crystal 3D Stereo Enhancement. SE[4:0] = 00110, indicating this feature is present.

ID8

18-bit ADC Resolution. The ID8 bit is `set', indicating this feature is present.

ID7

20-bit DAC resolution. The ID7 bit is `set', indicating this feature is present.

ID4

Headphone Output (Alt Line Out). The ID4 bit is `set', indicating this feature is present.

Default

1990h. The data in this register is read-only data.

Any write to this register causes a Register Reset to the default state of the audio (Index 00h - 38h) and vendor spe-
cific (Index 5Ah - 7Ah) registers. A read from this register returns configuration information about the CS4297A.

4.2

Master Volume Register (Index 02h)

Mute

Master Mute. Setting this bit mutes the LINE_OUT_L/R output signals.

ML[5:0]

Master Volume Left. These bits control the left master output volume. Each step corresponds
to 1.5 dB gain adjustment, with 00000 = 0 dB. The total range is 0 dB to -94.5 dB attenuation.

MR[5:0]

Master Volume Right. These bits control the right master output volume. Each step corresponds
to 1.5 dB gain adjustment, with 00000 = 0 dB. The total range is 0 dB to -94.5 dB attenuation.

Default

8000h. This value corresponds to 0 dB attenuation and Mute `set'.

D15

D14

D13

D12

D11

D10

SE4

SE3

SE2

SE1

SE0

ID8

ID7

ID4

D15

D14

D13

D12

D11

D10

Mute

ML5

ML4

ML3

ML2

ML1

ML0

MR5

MR4

MR3

MR2

MR1

MR0

CS4297A

4.3

Alternate Volume Register (Index 04h)

Mute

Alternate Mute. Setting this bit mutes the ALT_LINE_OUT_L/R output signals.

ML[4:0]

Alternate Volume Left. These bits control the left alternate output volume. Each step corre-

sponds to 1.5 dB gain adjustment, with 00000 = 0 dB. The total range is 0 dB to -46.5 dB atten-
uation. See Table 2 for further attenuation levels.

ML5

Alternate Volume Left Max Attenuation. Setting ML5 sets the left channel attenuation to

-46.5 dB by forcing ML[4:0] to a `1' state. ML[5:0] will read back 011111 when ML5 has been
`set'. Table 2 summarizes this behavior.

MR[4:0]

Alternate Volume Right. These bits control the right alternate output volume. Each step corre-

sponds to 1.5 dB gain adjustment, with 00000 = 0 dB. The total range is 0 dB to -46.5 dB atten-
uation. See Table 2 for further attenuation levels.

MR5

Alternate Volume Right Max Attenuation. Setting MR5 sets the right channel attenuation to

-46.5 dB by forcing MR[4:0] to a `1' state. MR[5:0] will read back 011111 when MR5 has been
`set'. Table 2 summarizes this behavior.

Default

8000h. This value corresponds to 0 dB attenuation and Mute `set'.

4.4

Mono Volume Register (Index 06h)

Mute

Mono Mute. Setting this bit mutes the MONO_OUT signal.

MM[5:0]

Mono Volume. These bits control the mono output volume. Each step corresponds to 1.5 dB
gain adjustment, with a total available range from 0 dB to -46.5 dB attenuation. See Table 2 for
further attenuation levels.

MM5

Mono Volume Max Attenuation. Setting the MM5 bit sets the mono attenuation to -46.5 dB by
forcing MM[4:0] to a `1' state. MM[5:0] will read back 011111 when MM5 has been `set'. Table 2
summarizes this behavior.

Default

8000h. This value corresponds to 0 dB attenuation and Mute `set'.

D15

D14

D13

D12

D11

D10

Mute

ML5

ML4

ML3

ML2

ML1

ML0

MR5

MR4

MR3

MR2

MR1

MR0

Mx[5:0]

Write

Mx[5:0]

Read

Gain

Level

000000

0 dB

000001

-1.5 dB

...

011111

-46.5 dB

100000

011111

-46.5 dB

...

111111

011111

-46.5 dB

Table 2. Analog Mixer Output Attenuation

D15

D14

D13

D12

D11

D10

Mute

MM5

MM4

MM3

MM2

MM1

MM0

CS4297A

4.5

PC_BEEP Volume Register (Index 0Ah)

Mute

PC_BEEP Mute. Setting this bit mutes the PC_BEEP input signal.

PV[3:0]

PC_BEEP Volume Control. The PV[3:0] bits are used to control the gain levels of the PC_BEEP
input source to the Input Mixer. Each step corresponds to 3 dB gain adjustment, with
0000 = 0 dB. The total range is 0 dB to -45 dB attenuation.

Default

0000h. This value corresponds to 0 dB attenuation and Mute `clear'.

This register has no effect on the PC_BEEP volume during RESET#.

4.6

Phone Volume Register (Index 0Ch)

Mute

Phone Mute. Setting this bit mutes the Phone input signal.

GN[4:0]

Phone Volume Control. The GN[4:0] bits are used to control the gain levels of the Phone input
source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with 01000 = 0 dB.
The total range is +12 dB to -34.5 dB gain. See Table 4 on page 24 for further details.

Default

8008h. This value corresponds to 0 dB gain and Mute `set'.

D15

D14

D13

D12

D11

D10

Mute

PV3

PV2

PV1

PV0

D15

D14

D13

D12

D11

D10

Mute

GN4

GN3

GN2

GN1

GN0

CS4297A

4.7

Microphone Volume Register (Index 0Eh)

Mute

Microphone Mute. Setting this bit mutes the MIC1 or MIC2 signal. The selection of the MIC1 or
MIC2 input pin is controlled by the MS bit in the General Purpose Register (Index 20h).

GN[4:0]

Microphone Volume Control. The GN[4:0] bits are used to control the gain level of the Micro-
phone input source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with
01000 = 0 dB. The total range is +12 dB to -34.5 dB gain. See Table 3 for further details.

20dB

Microphone 20 dB Boost. When `set', the 20dB bit enables the +20 dB microphone boost block.
This bit allows for variable boost of 0 dB or +20 dB. Table 3 summarizes this behavior.

Default

8008h. This value corresponds to 0 dB gain and Mute `set'.

D15

D14

D13

D12

D11

D10

Mute

20dB

GN4

GN3

GN2

GN1

GN0

GN[4:0]

Gain Level

20dB = 0

20dB = 1

00000

+12.0 dB

+32.0 dB

00001

+10.5 dB

+30.5 dB

...

00111

+1.5 dB

+21.5 dB

01000

0.0 dB

+20.0 dB

01001

-1.5 dB

+18.5 dB

...

11111

-34.5 dB

-14.5 dB

Table 3. Microphone Input Gain Values

CS4297A

4.8

Stereo Analog Mixer Input Gain Registers (Index 10h - 18h)

Mute

Stereo Input Mute. Setting this bit mutes the respective input signal, both right and left inputs.

GL[4:0]

Left Volume Control. The GL[4:0] bits are used to control the gain level of the left analog input
source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with 01000 = 0 dB.
The total range is +12 dB to -34.5 dB gain. See Table 4 for further details.

GR[4:0]

Right Volume Control. The GR[4:0] bits are used to control the gain level of the right analog in-
put source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with 01000 =
0 dB. The total range is +12 dB to -34.5 dB gain. See Table 4 for further details.

Default

8808h. This value corresponds to 0 dB gain and Mute `set'.

The Stereo Analog Mixer Input Gain Registers are listed in Table 5.

D15

D14

D13

D12

D11

D10

Mute

GL4

GL3

GL2

GL1

GL0

GR4

GR3

GR2

GR1

GR0

Gx[4:0]

Gain Level

00000

+12.0 dB

00001

+10.5 dB

...

00111

+1.5 dB

01000

0.0 dB

01001

-1.5 dB

...

11111

-34.5 dB

Table 4. Analog Mixer Input Gain Values

Register Index

Function

10h

Line In Volume

12h

CD Volume

14h

Video Volume

16h

Aux Volume

18h

PCM Out Volume

Table 5. Stereo Volume Register Index

CS4297A

4.9

Input Mux Select Register (Index 1Ah)

SL[2:0]

Left Channel Source. The SL[2:0] bits select the left channel source to pass to the ADCs for
recording. See Table 6 for possible values.

SR[2:0]

Right Channel Source. The SR[2:0] bits select the right channel source to pass to the ADCs for
recording. See Table 6 for possible values.

Default

0000h. This value selects the Mic input for both channels.

4.10

Record Gain Register (Index 1Ch)

Mute

Record Gain Mute. Setting this bit mutes the input to the L/R ADCs.

GL[3:0]

Left ADC Gain. The GL[3:0] bits control the input gain on the left channel of the analog source,
applied after the input mux and before the ADCs. Each step corresponds to 1.5 dB gain adjust-
ment, with 0000 = 0 dB. The total range is 0 dB to +22.5 dB gain.

GR[3:0]

Right ADC Gain. The GR[3:0] bits control the input gain on the right channel of the analog
source, applied after the input mux and before the ADCs. Each step corresponds to 1.5 dB gain
adjustment, with 0000 = 0 dB. The total range is 0 dB to +22.5 dB gain.

Default

8000h. This value corresponds to 0 dB gain and Mute `set'.

D15

D14

D13

D12

D11

D10

SL2

SL1

SL0

SR2

SR1

SR0

Sx[2:0]

Record Source

000

Mic

001

CD Input

010

Video Input

011

Aux Input

100

Line Input

101

Stereo Mix

110

Mono Mix

111

Phone Input

Table 6. Input Mux Selection

D15

D14

D13

D12

D11

D10

Mute

GL3

GL2

GL1

GL0

GR3

GR2

GR1

GR0

CS4297A

4.11

General Purpose Register (Index 20h)

3D Enable. When `set', the 3D bit enables the CrystalClear

3D stereo enhancement. This

function is not available in DAC Direct Mode (DDM).

MIX

Mono Output Select. The MIX bit selects the source for the Mono Out output. When `set', the
microphone input is selected. When `clear', the stereo-to-mono mixer is selected.

Microphone Select. The MS bit determines which of the two Mic inputs are passed to the mixer.
When `set', the MIC2 input is selected. When `clear', the MIC1 input is selected.

LPBK

Loopback Enable. When `set', the LPBK bit enables the ADC/DAC Loopback Mode. This bit
routes the output of the ADCs to the input of the DACs without involving the AC-link.

Default

0000h

4.12

3D Control Register (Index 22h)

S[3:0]

Spacial Enhancement Depth. These bits control the amount of "space" added to the output ste-

reo signal. When S[3:0] = 0000, the minimum amount of spatial enhancement is added. When
S[3:0] = 1111, the maximum amount of spatial enhancement is added. The 3D function is en-
abled and disabled by the 3D bit in the General Purpose Register (Index 20h).

Default

0000h. This value corresponds to minimum spatial enhancement added to the output signal.

D15

D14

D13

D12

D11

D10

MIX

LPBK

D15

D14

D13

D12

D11

D10

CS4297A

4.13

Powerdown Control/Status Register (Index 26h)

EAPD

External Amplifier Power Down. The EAPD pin follows this bit and is generally used to power

down external amplifiers.

PR6

Alternate Line Out Powerdown. When `set', the alternate line out buffer is powered down.

PR5

Internal Clock Disable. When `set', this bit completely powers down both the analog and digital

sections of the CS4297A. The only way to recover from setting this bit is through a Cold Reset
(driving the RESET# signal active).

PR4

AC-link Powerdown. When `set', the AC link is powered down (BIT_CLK off). The AC-link can

be restarted through a Warm Reset using the SYNC signal, or a Cold Reset using the RESET#
signal (primary audio codec only).

PR3

Analog Mixer Powerdown (Vref off). When `set', the analog mixer and voltage reference are

powered down. When clearing this bit, the ANL, ADC, and DAC bits should be checked before
writing any mixer registers.

PR2

Analog Mixer Powerdown (Vref on). When `set', the analog mixer is powered down (the voltage

reference is still active). When clearing this bit, the ANL bit should be checked before writing
any mixer registers.

PR1

Front DACs Powerdown. When `set', the DACs are powered down. When clearing this bit, the

DAC bit should be checked before sending any data to the DACs.

PR0

L/R ADCs and Input Mux Powerdown. When `set', the ADCs and the ADC input muxes are pow-

ered down. When clearing this bit, no valid data will be sent down the AC link until the ADC bit
goes high.

REF

Voltage Reference Ready Status. When `set', indicates the voltage reference is at a nominal

level.

ANL

Analog Ready Status. When `set', the analog output mixer, input multiplexer, and volume con-

trols are ready. When clear, no volume control registers should be written.

DAC

Front DAC Ready Status. When `set', the DACs are ready to receive data across the AC link.

When clear, the DACs will not accept any valid data.

ADC

L/R ADC Ready Status. When `set', the ADCs are ready to send data across the AC link. When

clear, no data will be sent to the Controller.

Default

0000h. This value indicates all blocks are powered on. The lower four bits will change as the

CS4297A finishes an initialization and calibration sequence.

The PR[6:0] and the EAPD bits are powerdown control for different sections of the CS4297A as well as external
amplifiers. The REF, ANL, DAC, and ADC bits are read-only status bits which, when `set', indicate that a particular
section of the CS4297A is ready. After the controller receives the Codec Ready bit in input Slot 0, these status bits
must be checked before writing to any mixer registers. See Section 5, Power Management, for more information on
the powerdown functions.

D15

D14

D13

D12

D11

D10

EAPD

PR6

PR5

PR4

PR3

PR2

PR1

PR0

REF

ANL

DAC

ADC

CS4297A

4.14

Extended Audio ID Register (Index 28h)

ID[1:0]

Codec Configuration ID. When ID[1:0] = 00, the CS4297A is the primary audio codec. When
ID[1:0] = 01, 10, or 11, the CS4297A is a secondary audio codec. The state of the ID[1:0] bits
is determined at power-up from the ID[1:0]# pins.

AMAP

Audio Slot Mapping. The AMAP bit indicates whether the optional AC '97 2.1 compliant AC-link
slot to audio DAC mapping is supported. This bit is a shadow of the AMAP bit in the AC Mode
Control Register (Index 5Eh). The PCM playback and capture slots are mapped according to
Table 7 on page 29.

VRA

Variable Rate PCM Audio. The VRA bit indicates whether variable rate PCM audio is supported.
This bit always returns `0', indicating that variable rate PCM audio is not available.

Default

x200h. Where x is determined by the state of ID[1:0]# input pins. The Extended Audio ID Reg-
ister (Index 28h) is a read only register.

4.15

PCM Front DAC Rate Register (Index 2Ch)

SR[15:0]

Front DAC Sample Rate. The SR[15:0] bits are read-only bits, and always read BB80h indicat-

ing 48 kHz sample rate.

Default

BB80h. This value corresponds to 48 kHz sample rate.

4.16

PCM L/R ADC Rate Register (Index 32h)

SR[15:0]

Left/Right ADC Sample Rate. The SR[15:0] bits are read-only bits, and always read BB80h in-

dicating 48 kHz sample rate.

Default

BB80h. This value corresponds to 48 kHz sample rate.

D15

D14

D13

D12

D11

D10

ID1

ID0

AMAP

VRA

D15

D14

D13

D12

D11

D10

SR15

SR14

SR13

SR12

SR11

SR10

SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

D15

D14

D13

D12

D11

D10

SR15

SR14

SR13

SR12

SR11

SR10

SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

CS4297A

4.17

AC Mode Control Register (Index 5Eh)

DDM

DAC Direct Mode. This bit controls the source to the line and alternate line output drivers. When

`set', the L/R DACs directly drive the line and alternate line outputs by bypassing the audio mix-
er. When `clear', the audio mixer is the source for the line and alternate line outputs.

AMAP

Audio Slot Mapping. This read/write bit controls whether the CS4297A responds to the Codec

ID based slot mapping as outlined in the AC '97 2.1 specification. The bit is shadowed in the
Extended Audio ID Register (Index 28h). Refer to Table 7 for the slot mapping configurations.

SM[1:0]

Slot Map. The SM[1:0] bits define the Slot Mapping for the CS4297A when the AMAP bit is

`cleared'. Refer to Table 7 for the slot mapping configurations.

Default

0080h

4.18

Misc. Crystal Control Register (Index 60h)

LOSM

Loss of SYNC Mute Enable. The LOSM bit controls the loss of SYNC mute function. If this bit

is `set', the CS4297A will mute all analog outputs for the duration of loss of SYNC. If this bit
is `cleared', the mixer will continue to function normally during loss of SYNC. The CS4297A
expects to sample SYNC `high' for 16 consecutive BIT_CLK periods and then `low' for 240
consecutive BIT_CLK periods, otherwise loss of SYNC becomes true.

Default

0023h

D15

D14

D13

D12

D11

D10

DDM

AMAP

SM1

SM0

Slot

Assignment

Mode

Codec ID

Slot Map

AMAP

Slot Assignments

ID1

ID0 SM1 SM0

DAC,

SPDIF

ADC

AMAP Mode 0

AMAP Mode 1

AMAP Mode 2

AMAP Mode 3

Slot Map Mode 0

Slot Map Mode 1

Slot Map Mode 2

Slot Map Mode 3

Table 7. Slot Mapping

D15

D14

D13

D12

D11

D10

Reserved

LOSM

CS4297A

4.19

S/PDIF Control Register (Index 68h)

SPEN

S/PDIF Enable. The SPEN bit enables S/PDIF data transmission on the S/PDIF_OUT pin.
The SPEN bit routes the left and right channel data from the AC '97 controller, the digital mix-
er, or the digital effects engine to the S/PDIF transmitter block. The actual data routed to the
S/PDIF block is controlled through the AMAP/SM[1:0] configuration in the AC Mode Control
Register (Index 5Eh).

Val

Validity. The V bit is mapped to the V bit (bit 28) of every sub-frame. If this bit is `0', the signal
is suitable for conversion or processing.

Sample Rate. The Fs bit indicates the sampling rate for the S/PDIF data. The inverse of this
bit is mapped to bit 25 of the channel status block. When the Fs bit is `clear', the sampling
frequency is 48 kHz. When `set', the sampling frequency is 44.1 kHz. The actual rate at which
S/PDIF data are being transmitted solely depends on the master clock frequency of the
CS4297A. The Fs bit is merely an indicator to the S/PDIF receiver.

Generation Status. The L bit is mapped to bit 15 of the channel status block. For category
codes 001xxxx, 0111xxx and 100xxxx, a value of `0' indicates original material and a value of
`1' indicates a copy of original material. For all other category codes the definition of the L bit
is reversed.

CC[6:0]

Category Code. The CC[6:0] bits are mapped to bits 8-14 of the channel status block.

Emph

Data Emphasis. The Emph bit is mapped to bit 3 of the channel status block. If the Emph bit
is `1', 50/15us filter pre-emphasis is indicated. If the bit is `0', no pre-emphasis is indicated.

Copy

Copyright. The Copy bit is mapped to bit 3 of the channel status block. If the Copy bit is `1'
copyright is not asserted and copying is permitted.

/Audio

Audio / Non-Audio. The /Audio bit is mapped to bit 1 of the channel status block. If the /Audio
bit is `0', the data transmitted over S/PDIF is assumed to be digital audio. If the /Audio bit is
`1', non-audio data is assumed.

Pro

Professional/Consumer. The Pro bit is mapped to bit 0 of the channel status block. If the Pro

bit is `0', consumer use of the audio control block is indicated. If the bit is `1', professional use
is indicated.

Default

0000h

For a further discussion of the proper use of the channel status bits see application note AN22: Overview of Digital
Audio Interface Data Structures [3].

D15

D14

D13

D12

D11

D10

SPEN

Val

CC6

CC5

CC4

CC3

CC2

CC1

CC0

Emph

Copy /Audio

Pro

CS4297A

4.20

Vendor ID1 Register (Index 7Ch)

F[7:0]

First Character of Vendor ID. With a value of F[7:0] = 43h, these bits define the ASCII `C'

character.

S[7:0]

Second Character of Vendor ID. With a value of S[7:0] = 52h, these bits define the ASCII `R'

character.

Default

4352h. This register contains read-only data.

4.21

Vendor ID2 Register (Index 7Eh)

T[7:0]

Third Character of Vendor ID. With a value of T[7:0] = 59h, these bits define the ASCII `Y'

character.

DID[2:0]

Device ID. With a value of DID[2:0] = 001, these bits specify the audio codec is a CS4297A.

REV[2:0]

Revision. With a value of REV[2:0] = 001, these bits specify the audio codec revision is `A'.

Default

591xh. This register contains read-only data.

The two Vendor ID registers provide a means to determine the manufacturer of the AC '97 audio codec. The first
three bytes of the Vendor ID registers contain the ASCII code for the first three letters of Crystal (CRY). The final
byte of the Vendor ID registers is divided into a Device ID field and a Revision field. Table 8 lists the currently defined
Device ID's. Table 9 lists the current revisions of the CS4297A.

D15

D14

D13

D12

D11

D10

D15

D14

D13

D12

D11

D10

DID2

DID1

DID0

REV2 REV1 REV0

DID[2:0]

Part Name

000

CS4297

001

CS4297A

010

CS4294/CS4298

011

CS4299

100

CS4201

101

CS4205

Table 8. Device ID with Corresponding Part Number

REV[2:0]

Revision

001

010

011

100

D, E, F, G, H

101

110

Table 9. Revision Values

CS4297A

5. POWER MANAGEMENT

5.1

AC '97 Reset Modes

The CS4297A supports three reset methods, as de-
fined in the AC '97 Specification: Cold AC '97 Re-
set, Warm AC '97 Reset, Register AC '97 Reset. A
Cold Reset results in all AC '97 logic (registers in-
cluded) initialized to its default state. A Warm Re-
set leaves the contents of the AC '97 register set
unaltered. A Register Reset initializes only the
AC '97 registers to their default states.

5.1.1

Cold AC `97 Reset

A Cold Reset is achieved by asserting RESET# for
a minimum of 1 µs after the power supply rails
have stabilized. This is done in accordance with the
minimum timing specifications in the AC '97 Seri-
al Port Timing section on page 7. Once deasserted,
all of the CS4297A registers will be reset to their
default power-on states and the BIT_CLK and
SDATA_IN signals will be reactivated.

5.1.2

Warm AC '97 Reset

A Warm Reset allows the AC-link to be reactivated
without losing information in the CS4297A regis-
ters. A Warm Reset is required to resume from a
D3

hot

state, where the AC-link had been halted yet

full power had been maintained. A primary codec
Warm Reset is initiated when the SYNC signal is
driven high for at least 1 µs and then driven low in
the absence of the BIT_CLK clock signal. The
BIT_CLK clock will not restart until at least 2 nor-
mal BIT_CLK clock periods (162.8 ns) after the
SYNC signal is deasserted. A Warm Reset of the
secondary codec is recognized when the primary
codec on the AC-link resumes BIT_CLK genera-
tion. The CS4297A will wait for BIT_CLK to be
stable to restore SDATA_IN activity and/or
S/PDIF transmission on the following frame.

5.1.3

Register AC '97 Reset

The third reset mode provides a Register Reset to
the CS4297A. This is available only when the
CS4297A AC-link is active and the Codec Ready
bit is `set'. The audio (including extended audio)
registers (Index 00h - 38h) and the vendor specific
registers (Index 5Ah - 7Ah) are reset to their default
states by a write of any value to the Reset Register
(Index 00h).

CS4297A

5.2

Powerdown Controls

The

Powerdown Control/Status Register

(Index 26h) controls the power management func-
tions. The PR[6:0] bits in this register control the
internal powerdown states of the CS4297A. Power-
down control is available for individual subsections
of the CS4297A by asserting any PRx bit or any
combination of PRx bits. Most powerdown states
can be resumed by clearing the corresponding PRx
bit. Table 10 shows the mapping of the power con-
trol bits to the functions they manage.

When PR0 is `set', the L/R ADCs and the Input
Mux are shut down and the ADC bit in the Power-
down Control/Status Register (Index 26h) is
`cleared' indicating the ADCs are no longer in a
ready state. The same is true for the DACs, the an-
alog mixers, and the reference voltage (Vrefout).
When the PR2 or PR3 bit of the mixer is `cleared',
the mixer section will begin a power-on process,
and the corresponding powerdown status bit will be
`set' when the hardware is ready.

Shutting down the AC-link by `setting' PR4 causes
the primary Codec to turn off the BIT_CLK and
drive SDATA_IN low. It also ignores SYNC and

SDATA_OUT in their normal capacities. Either a
Cold Reset or a Warm Reset is required to restore
operation to the CS4297A. A Cold Reset will re-
store all mixer registers to their power-on default
values. A Warm Reset will not alter the values of
any mixer register, except clearing the PR4 bit in
Powerdown Control/Status Register (Index 26h).

The PR5 bit powers down all analog and digital
subsections of the device. A Cold Reset is the only
way to restore operation to the CS4297A after a
PR5 global powerdown.

The CS4297A does not automatically mute any in-
put or output when the powerdown bits are `set'.
The software driver controlling the AC '97 device
must manage muting the input and output analog
signals before putting the part into any power man-
agement state. The definition of each PRx bit may
affect a single subsection or a combination of sub-
sections within the CS4297A. Table 11 on page 34
contains the matrix of subsections affected by the
respective PRx function. Table 12 on page 34
shows the different operating power consumptions
levels for different powerdown functions.

PR Bit

Function

PR0

L/R ADCs and Input Mux Powerdown

PR1

Front DACs Powerdown

PR2

Analog Mixer Powerdown (Vref on)

PR3

Analog Mixer Powerdown (Vref off)

PR4

AC-link Powerdown (BIT_CLK off)*

PR5

Internal Clock Disable

PR6

Alternate Line Out Powerdown

* Applies only to primary codec

Table 10. Powerdown PR Bit Functions

CS4297A

6. ANALOG HARDWARE

DESCRIPTION

The analog line-level input hardware consists of
four stereo inputs (LINE_IN_L/R, CD_L/GND/R,
VIDEO_L/R, and AUX_L/R), two selectable
mono microphone inputs (MIC1 and MIC2), and
two mono inputs (PC_BEEP and PHONE). The an-
alog line-level output hardware consists of a mono
output (MONO_OUT), and dual stereo line outputs
(LINE_OUT_L/R and ALT_LINE_OUT_L/R).
This section describes the analog hardware needed
to interface with these pins. The designs presented
in this section comply with specifications detailed
in Chapter 17 of the Microsoft

PC Design Guide-

lines [7] (referred to as PC 99). For EMI reduction
techniques refer to the application note N165:
CS4297A/CS4299 EMI Reduction Techniques [5].

6.1

Analog Inputs

All analog inputs to the CS4297A, including
CD_GND, should be capacitively coupled to the
input pins. Unused analog inputs should be tied to-
gether and connected through a capacitor to analog
ground or tied to the Vrefout pin directly. The max-
imum allowed voltage for analog inputs, except the
microphone input, is 1 V

RMS

. For the microphone

input the maximum allowed voltage depends on the
selected boost setting.

6.1.1

Line-Level Inputs

Figure 10 shows circuitry for a line-level stereo in-
put. Replicate this circuit for the Line, Video and
Aux inputs. This design attenuates the input by
6 dB, bringing the signal from the PC 99 specified
2 V

RMS

, to the CS4297A maximum allowed

1 V

RMS

6.1.2

CD Input

The CD line-level input has an extra pin,
CD_GND, providing a pseudo-differential input
for both CD_L and CD_R. This pin takes the
common-mode noise out of the CD inputs when

connected to the CD analog source ground. Follow-
ing the reference designs in Figure 11 and
Figure 12 provides extra attenuation of common
mode noise coming from the CD-ROM drive,
thereby producing a higher quality signal. One per-
cent resistors are recommended since closely
matched resistor values provide better com-
mon-mode attenuation of unwanted signals. The
circuit shown in Figure 11 can be used to attenuate
a 2 V

RMS

CD input signal by 6 dB. The circuit

shown in Figure 12 can be used for a 1 V

RMS

CD in-

put signal.

6.8 k

1.0

µF

1.0

µF

6.8 k

Figure 10. Line Input (Replicate for Video and Aux)

(All resistors 1%)

6.8 k

CD_L

CD_COM

CD_R

1.0

µF

CD_L

CD_R

CD_GND

6.8 k

1.0

µF

3.4 k

6.8 k

2.2

µF

3.4 k

6.8 k

AGND

Figure 11. Differential 2 V

RMS

CD Input

100

CD_L

CD_COM

CD_R

1.0

µF

CD_L

CD_R

CD_GND

100

1.0

µF

100

47 k

2.2

µF

47 k

AGND

Figure 12. Differential 1 V

RMS

CD Input

CS4297A

6.1.3

Microphone Inputs

Figure 13 illustrates an input circuit suitable for dy-
namic and electret microphones. Electret, or phan-
tom-powered, microphones use the right channel
(ring) of the jack for power. The design also sup-
ports the recommended advanced frequency re-
sponse for voice recognition as specified in PC 99.
Note the microphone input to the CS4297A has an
integrated pre-amplifier. Using the 20dB bit in the
Microphone Volume Register (Index 0Eh) the
pre-amplifier gain can be set to 0 dB or 20 dB.
Figure 14 shows an external pre-amplifier circuit
for an additional 18 dB gain.

6.1.4

PC Beep Input

The PC_BEEP input is useful for mixing the output
of the "beeper" (timer chip), provided in most PCs,
with the other audio signals. When the CS4297A is
held in reset, PC_BEEP is passed directly to the
line output. This allows the system sounds or
"beeps" to be available before the AC '97 interface
has been activated. Figure 15 illustrates a typical
input circuit for the PC_BEEP input. If PC_BEEP
is driven from a CMOS gate, the 4.7 k

resistor

should be tied to analog ground instead of +5VA.
Although this input is described for a low-quality
"beeper", it is of the same high-quality as all other
analog inputs and may be used for other purposes.

0.33

µF

220 pF
NPO

3.3

µF

6.8 K

47 k

MC33078 or
MC33178

Vrefout

MIC1
or
MIC2

µF

0.33

µF

X7R

2 k

47 k

0.1

µF

100 pF
NPO

Figure 13. Microphone Input

AGND

+5 VA

100

2.7

CGND

220 pF

AGND

0.068 µF

X7R

AGND

+5 VA

U1A
MC33078D

10 µF

AGND

+5 VA

6.8

10 µF

AGND

220 pF

47 k

U1B
MC33078D

1 µF

X7R

MIC1/MIC2

47 k

Figure 14. Microphone Pre-amplifier

4.7 k

PC_BEEP

+5VA (Low Noise) or

AGND if CMOS Source

PC-BEEP-BUS

47 k

2.7 nF

X7R

0.1

µF

X7R

AGND

Figure 15. PC_BEEP Input

CS4297A

6.1.5

Phone Input

One application of the PHONE input is to interface
to the output of a modem analog front end (AFE)
device so that modem dialing signals and protocol
negotiations may be monitored through the audio
system. Figure 16 shows a design for a modem
connection where the output is fed from the
CS4297A MONO_OUT pin through a divider. The
divider ratio shown does not attenuate the signal,
providing an output voltage of 1 V

RMS

. If a lower

output voltage is desired, the resistors can be re-
placed with appropriate values, as long as the total
load on the output is kept greater than 10 k

. The

PHONE input is divided by 6 dB to accommodate
a line-level source of 2 V

RMS

6.2

Analog Outputs

The analog line-level output section provides two
stereo outputs and a mono output. The
LINE_OUT_L/R, ALT_LINE_OUT_L/R, and

MONO_OUT pins require 680 pF to 1000 pF NPO
capacitors between the corresponding pin and ana-
log ground. Each analog output is DC-biased up to
the Vrefout signal reference, nominally 2.3 V. This
requires the outputs be AC-coupled to external cir-
cuitry (AC load must be greater than 10 k

) or DC

coupled to a buffer op-amp biased at Vrefout.

6.2.1

Stereo Outputs

See Figure 18 for a line-level stereo output refer-
ence design. See Figure 17 for a recommended
headphone stereo output reference design.

6.2.2

Mono Output

The mono output, MONO_OUT, can be either a
sum of the left and right output channels, attenuat-
ed by 6 dB to prevent clipping at full scale, or the
selected Mic signal. The mono out channel can
drive the PC internal mono speaker using an appro-
priate buffer circuit

PHONE

MONO_OUT

PHONE

MONO_OUT

6.8 k

1.0

µF

6.8 k

1.0

µF

47 k

AGND

1000 pF

Figure 16. Modem Connection

ALT_LINE_OUT_R

ALT_LINE_OUT_L

27 k

1000 pF
NPO

AGND

220

µF

ELEC

220

µF

ELEC

1000 pF
NPO

27 k

47 k

AGND

22 pF
NPO

39 k

22 pF
NPO

39 k

TDA1308

Vrefout

1/4 Watt

47 k

Headphone
Out

Figure 17. Alternate Line Output as Headphone Output

AGND

ALT_LINE_OUT_R

27 k

1000 pF

NPO

1000 pF
NPO

AGND

0.1 µF

Y5V

220 µF

39 k

22 pF
NPO

TDA1308

ALT_LINE_OUT_L

VREFOUT

ELEC

1/4 WATT

HP_OUT_R

220 µF

ELEC

1/4 WATT

HP_OUT_L

47 k

AGND

1 µF

Figure 18. Stereo Output

CS4297A

6.3

Miscellaneous Analog Signals

The AFLT1 and AFLT2 pins must have a 1000 pF
NPO capacitor to analog ground. These capacitors
provide a single-pole low-pass filter at the inputs to
the ADCs. This makes low-pass filters at each ana-
log input pin unnecessary.

The REFFLT pin must have a 1

µF and a 0.1 µF ca-

pacitor connected to analog ground with a short,
wide trace to this pin (see Figure 21 in Section 8,
Grounding and Layout, for an example). The 1

µF

capacitor must not be replaced with any value high-
er than 1

µF. No other connection should be made,

as any coupling onto this pin will degrade the ana-
log performance of the CS4297A. Likewise, digital
signals should be kept away from REFFLT for sim-
ilar reasons.

The Vrefout pin is typically 2.3 V and provides a
common mode signal for single-supply external
circuits. Vrefout only supports light DC loads and
should be buffered if AC loading is needed. For
typical use the Vrefout pin should have a 1

µF and

a 0.1

µF capacitor connected to analog ground.

6.4

Power Supplies

The power supplies providing analog power should
be as clean as possible to minimize coupling into
the analog section which could degrade analog per-
formance. The analog power pins, AVdd1 and
AVdd2, supply power to all the analog circuitry on
the CS4297A. The +5 V analog supply should be
generated from a linear voltage regulator (7805
type) connected to a +12 V supply. This helps iso-
late the analog circuitry from noise typically found
on +5 V digital supplies. A typical voltage regula-
tor circuit for analog power using a
MC78M05CDT +5 V regulator is shown in
Figure 19. The digital power pins, DVdd1 and
DVdd2, should be connected to the same digital
supply as the controller AC-link interface. The dig-
ital interface on the CS4297A may operate at either
+3.3 V or +5 V and proper connection of these pins
will depend on the digital power supply of the con-
troller.

6.5

Reference Design

See Section 11 for a CS4297A reference design.

Figure 19. Voltage Regulator

+12VD

AGND

DGND

+5VA

0.1µF

Y5V

10µF

ELEC

10µF

ELEC

MC78M05CDT

OUT

GND

0.1µF

Y5V

CS4297A

7. SONY/PHILIPS DIGITAL

INTERFACE (S/PDIF)

The S/PDIF digital output is used to interface the
CS4297A to consumer audio equipment external to
the PC. This output provides an interface for stor-
ing digital audio data or playing digital audio data
to digital speakers. Figure 20 illustrates the circuits
necessary for implementing the IEC-958 optical or
consumer interface. For further information on
S/PDIF operation see application note AN22: Over-
view of Digital Audio Interface Data Structures [3].
For further information on S/PDIF recommended
transformers see application note AN134: AES and
S/PDIF Recommended Transformers [4].

8. GROUNDING AND LAYOUT

Figure 21 on page 40 shows the conceptual layout
for the CS4297A. The decoupling capacitors
should be located physically as close to the pins as
possible. Also note the connection of the REFFLT
decoupling capacitors to the ground return trace
connected directly to the ground return pin, AVss1.

It is strongly recommended that separate analog
and digital ground planes be used. Separate ground
planes keep digital noise and return currents from
modulating the CS4297A ground potential and de-
grading performance. The digital ground pins
should be connected to the digital ground plane and
kept separate from the analog ground connections
of the CS4297A and any other external analog cir-

cuitry. All analog components and traces should be
located over the analog ground plane and all digital
components and traces should be located over the
digital ground plane.

The common connection point between the two
ground planes (required to maintain a common
ground voltage potential) should be located under
the CS4297A. The AC-link digital interface con-
nection traces should be routed such that the digital
ground plane lies underneath these signals (on the
internal ground layer). This applies along the entire
length of these traces from the AC '97 controller to
the CS4297A.

Refer to the Application Note AN18: Layout and
Design Rules for Data Converters and Other
Mixed Signal Devices [2] for more information on
layout and design rules.

0.1

µF

DGND

DVdd

SPDO/SDO2

S/PDIF_OUT

TOTX-173

SPDO/SDO2

+5V_PCI

DGND

8.2 k

DGND

3.3V

247.5

107.6

375

93.75

Figure 20. S/PDIF Output

CS4297A

Audio I/O

PC_BEEP - Analog Mono Source, Input, Pin 12

The PC_BEEP input is intended to allow the PC system POST (Power On Self-Test) tones to pass
through to the audio subsystem. The PC_BEEP input has two connections: the first connection is to the
analog output mixer, the second connection is directly to the LINE_OUT stereo outputs. While the
RESET# pin is actively being asserted and the BCFG pin is left floating, the PC_BEEP bypass path to
the LINE_OUT outputs is enabled. While the CS4297A is in normal operation mode, with RESET#
deasserted or BCFG grounded, PC_BEEP is a monophonic source to the analog output mixer. The
maximum allowable input is 1 V

RMS

(sinusoidal). This input is internally biased at the Vrefout voltage

reference and requires AC-coupling to external circuitry. If this input is not used, it should be connected
to the Vrefout pin or AC-coupled to analog ground.

PHONE - Analog Mono Source, Input, Pin 13

This analog input is a monophonic source to the analog output mixer. It is intended to be used as a
modem subsystem input to the audio subsystem. The maximum allowable input is 1 V

RMS

(sinusoidal).

This input is internally biased at the Vrefout voltage reference and requires AC-coupling to external
circuitry. If this input is not used, it should be connected to the Vrefout pin or AC-coupled to analog
ground.

MIC1 - Analog Mono Source, Input, Pin 21

This analog input is a monophonic source to the analog output mixer. It is intended to be used as a
desktop microphone connection to the audio subsystem. The CS4297A internal mixer's microphone
input is MUX selectable with either MIC1 or MIC2 as the input. The maximum allowable input is 1 V

RMS

(sinusoidal). This input is internally biased at the Vrefout voltage reference and requires AC-coupling to
external circuitry. If this input is not used, it should be connected to the Vrefout pin or AC-coupled to
analog ground.

MIC2 - Analog Mono Source, Input, Pin 22

This analog input is a monophonic source to the analog output mixer. It is intended to be used as an
alternate microphone connection to the audio subsystem. The CS4297A internal mixer's microphone
input is MUX selectable with either MIC1 or MIC2 as the input. The maximum allowable input is 1 V

RMS

LINE_IN_L, LINE_IN_R - Analog Line Source, Inputs, Pins 23 and 24

These inputs form a stereo input pair to the CS4297A. The maximum allowable input is 1 V

RMS

(sinusoidal). These inputs are internally biased at the Vrefout voltage reference and require AC-coupling
to external circuitry. If these inputs are not used, they should both be connected to the Vrefout pin or
both AC-coupled, with separate AC-coupling caps, to analog ground.

CD_L, CD_R - Analog CD Source, Inputs, Pins 18 and 20

These inputs form a stereo input pair to the CS4297A. It is intended to be used for the Red Book CD
audio connection to the audio subsystem. The maximum allowable input is 1 V

RMS

(sinusoidal). These

inputs are internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry.
If these inputs are not used, they should both be connected to the Vrefout pin or both AC-coupled, with
separate AC-coupling caps, to analog ground.

CD_GND - Analog CD Common Source, Input, Pin 19

This analog input is used to remove common mode noise from Red Book CD audio signals. The
impedance on the input signal path should be one half the impedance on the CD_L and CD_R input
paths. This pin requires AC-coupling to external circuitry. If this input is not used, it should be connected
to the Vrefout pin or AC-coupled to analog ground.

CS4297A

VIDEO_L, VIDEO_R - Analog Video Audio Source, Inputs, Pins 16 and 17

These inputs form a stereo input pair to the CS4297A. It is intended to be used for the audio signal
output of a video device. The maximum allowable input is 1 V

RMS

(sinusoidal). These inputs are

internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. If these
inputs are not used, they should both be connected to the Vrefout pin or both AC-coupled, with separate
AC-coupling caps, to analog ground.

AUX_L, AUX_R - Analog Auxiliary Source, Inputs, Pins 14 and 15

These inputs form a stereo input pair to the CS4297A. The maximum allowable input is 1 V

RMS

LINE_OUT_L, LINE_OUT_R - Analog Line-Level, Outputs, Pins 35 and 36

These signals are analog outputs from the stereo output mixer. The full-scale output voltage for each
output is nominally 1 V

RMS

(sinusoidal). These outputs are internally biased at the Vrefout voltage

reference and require either AC-coupling to external circuitry or DC-coupling to a buffer op-amp biased
at the Vrefout voltage. These pins need a 680-1000 pF NPO capacitor attached to analog ground.

ALT_LINE_OUT_L, ALT _LINE_OUT_R - Analog Alternate Line-Level, Outputs, Pins 39 and 41

These signals are analog outputs from the stereo output mixer. The full-scale output voltage for each
output is nominally 1 V

RMS

(sinusoidal). These outputs are internally biased at the Vrefout voltage

reference and require either AC-coupling to external circuitry or DC-coupling to a buffer op-amp biased
at the Vrefout voltage. These pins need a 680-1000 pF NPO capacitor attached to analog ground.

MONO_OUT - Analog Mono Line-Level, Output, Pin 37

This signal is an analog output from the stereo-to-mono mixer or MIC1/2. The full-scale output voltage
for this output is nominally 1 V

RMS

(sinusoidal). This output is internally biased at the Vrefout voltage

reference and requires either AC-coupling to external circuitry or DC-coupling to a buffer op-amp biased
at the Vrefout voltage. This pin needs a 680-1000 pF NPO capacitor attached to analog ground.

Clock and Configuration

XTL_IN - Crystal Input/Clock Input, Pin 2

In primary mode this pin requires either a 24.576 MHz crystal, with the other pin attached to XTL_OUT,
or an external CMOS clock. The crystal frequency must be 24.576 MHz and designed for fundamental
mode, parallel resonance operation. If an external CMOS clock is used to drive this pin, it must run at
24.576 MHz. In secondary mode all timing is derived from the BIT_CLK input signal and this pin should
be left floating.

XTL_OUT - Crystal Output, Pin 3

This pin is used when a crystal is placed between XTL_OUT and XLT_IN. If an external 24.576 MHz
clock is used on XTL_IN, this pin must be left floating with no traces or components connected to it. In
secondary mode this pin should be left floating.

ID1#, ID0# - Codec ID, Inputs, Pins 45 and 46

These pins select the Codec ID and mode of operation for the CS4297A. They are only sampled after
the rising edge of RESET#. These pins are internally pulled up to the digital supply voltage and should
be left floating for logic `0' or tied to digital ground for logic `1'. When both pins are left floating the
CS4297A is the primary codec. If either or both pins are tied to ground the CS4297A is a secondary
codec.

CS4297A

Analog Reference, Filters, and Configuration

REFFLT - Internal Reference Voltage, Input, Pin 27

This signal is the voltage reference used internal to the CS4297A. A 0.1

µF and a 1.0 µF (must not be

larger than 1

µF) capacitor with short, wide traces must be connected to this pin. No other connections

should be made to this pin.

Vrefout - Voltage Reference, Output, Pin 28

All analog inputs and outputs are centered around Vrefout, nominally 2.3 Volts. This pin may be used to
level shift external circuitry. This pin cannot drive any DC loads, thus any external loading must be
buffered.

AFLT1 - Left ADC Channel Antialiasing Filter, Input, Pin 29

This pin needs a 1000 pF NPO capacitor connected to analog ground.

AFLT2 - Right ADC Channel Antialiasing Filter, Input, Pin 30

This pin needs a 1000 pF NPO capacitor connected to analog ground.

FLTI, FLTO - 3D Filter, Input, Pin 33 and 34

A 1000 pF capacitor must be connected between FLTI and FLTO if the 3D function is used.

FLT3D - 3D Filter, Input, Pin 32

A 0.01

µF capacitor must be connected from this pin to AGND if the 3D function is used.

BCFG - Beep Configuration, Input, Pin 31

This pin is the configuration control for the PC_BEEP bypass path. If this pin is grounded, the bypass
path is disabled. If this pin is left floating, the PC_BEEP bypass path is enabled.

Misc. Digital Interfaces

S/PDIF_OUT - Sony/Philips Digital Interface, Output, Pin 48

This pin generates the S/PDIF digital output from the CS4297A when the SPEN bit in the S/PDIF
Control Register (Index 68h) is `set'. This output may be used to directly drive a resistive divider and
coupling transformer to an RCA-type connector for use with consumer audio equipment.

EAPD - External Amplifier Powerdown, Output, Pin 47

This pin is used to control the powerdown state of an audio amplifier external to the CS4297A. The
output is controlled by the EAPD bit in the Powerdown Ctrl/Stat Register (Index 26h). It is driven as a
normal CMOS output and defaults low (`0') upon power-up.

CS4297A

AC-Link

RESET# - AC '97 Chip Reset, Input, Pin 11

This active low signal is the asynchronous Cold Reset input to the CS4297A. The CS4297A must be
reset before it can enter normal operating mode.

SYNC - AC-Link Serial Port Sync pulse, Input, Pin 10

This signal is the serial port timing signal for the AC-link. Its period is the reciprocal of the maximum
sample rate, 48 kHz. The signal is generated by the controller, synchronous to BIT_CLK. SYNC is an
asynchronous input when the CS4297A is configured as a primary audio codec and is in a PR4
powerdown state. A series terminating resistor of 47

should be connected on the signal near the

SYNC source.

BIT_CLK - AC-Link Serial Port Master Clock, Input/Output, Pin 6

This input/output signal controls the master clock timing for the AC-link. In primary mode, this signal is a
12.288 MHz output clock derived from a 24.576 MHz crystal on the XTL_IN input clock. When the
CS4297A is in secondary mode, this signal is an input which controls the AC-link serial interface and
generates all internal clocking including the AC-link serial interface timing and the analog sampling
clocks. A series terminating resistor of 47

should be connected on this signal close to the CS4297A in

primary mode or close to the BIT_CLK source in secondary mode.

SDATA_OUT - AC-Link Serial Data Input Stream to AC '97, Input, Pin 5

This input signal receives the control information and digital audio output streams. The data is clocked
into the CS4297A on the falling edge of BIT_CLK. A series terminating resistor of 47

should be

connected on this signal near the controller.

SDATA_IN - AC-Link Serial Data Output Stream from AC '97, Output, Pin 8

This output signal transmits the status information and digital audio input streams from the ADCs. The
data is clocked out of the CS4297A on the rising edge of BIT_CLK. A series terminating resistor of 47

should be connected on this signal as close to the CS4297A as possible.

Power Supplies

DVdd1, DVdd2 - Digital Supply Voltage, Pins 1 and 9

Digital supply voltage for the AC-link section of the CS4297A. These pins can be tied to +5 V digital or
to +3.3 V digital. The CS4297A and controller AC-link should share a common digital supply

DVss1, DVss2 - Digital Ground, Pins 4 and 7

Digital ground connection for the AC-link section of the CS4297A. These pins should be isolated from
analog ground currents.

AVdd1, AVdd2 - Analog Supply Voltage, Pins 25 and 38

Analog supply voltage for the analog and mixed signal sections of the CS4297A. These pins must be
tied to the analog +5 V power supply. It is strongly recommended that +5 V be generated from a voltage
regulator to ensure proper supply currents and noise immunity from the rest of the system.

AVss1, AVss2 - Analog Ground, Pins 26 and 42

Ground connection for the analog, mixed signal, and substrate sections of the CS4297A. These pins
should be isolated from digital ground currents.

CS4297A

10. PARAMETER AND TERM DEFINITIONS

AC '97 Specification

Refers to the Audio Codec '97 Component Specification Ver 2.1 published by the Intel

Corporation [6].

AC '97 Controller or Controller

Refers to the control chip which interfaces to the audio codec AC-link. This has been also called DC '97
for Digital Controller '97 [6].

AC '97 Registers or Codec Registers

Refers to the 64-field register map defined in the AC '97 Specification.

ADC

Refers to a single Analog-to-Digital converter in the CS4297A. "ADCs" refers to the stereo pair of
Analog-to-Digital converters. The CS4297A ADCs have 18-bit resolution.

Codec

Refers to the chip containing the ADCs, DACs, and analog mixer. In this data sheet, the codec is the
CS4297A.

DAC

Refers to a single Digital-to-Analog converter in the CS4297A. "DACs" refers to the stereo pair of
Digital-to-Analog converters. The CS4297A DACs have 20-bit resolution.

dB FS A

dB FS is defined as dB relative to full-scale. The "A" indicates an A weighting filter was used.

Differential Nonlinearity

The worst case deviation from the ideal code width. Units in LSB.

Dynamic Range (DR)

DR is the ratio of the RMS full-scale signal level divided by the RMS sum of the noise floor, in the
presence of a signal, available at any instant in time (no change in gain settings between
measurements). Measured over a 20 Hz to 20 kHz bandwidth with units in dB FS A.

FFT

Fast Fourier Transform.

Frequency Response (FR)

FR is the deviation in signal level verses frequency. The 0 dB reference point is 1 kHz. The amplitude
corner, Ac, lists the maximum deviation in amplitude above and below the 1 kHz reference point. The
listed minimum and maximum frequencies are guaranteed to be within the Ac from minimum frequency
to maximum frequency inclusive.

Sampling Frequency.

Interchannel Gain Mismatch

For the ADCs, the difference in input voltage to get an equal code on both channels. For the DACs, the
difference in output voltages for each channel when both channels are fed the same code. Units are in
dB.

CS4297A

Interchannel Isolation

The amount of 1 kHz signal present on the output of the grounded AC-coupled line input channel with 1
kHz, 0 dB, signal present on the other line input channel. Units are in dB.

Line-level

Refers to a consumer equipment compatible, voltage driven interface. The term implies a low driver
impedance and a minimum 10

load impedance.

Paths

A-D: Analog in, through the ADCs, onto the serial link.

D-A: Serial interface inputs through the DACs to the analog output.

A-A: Analog in to Analog out (analog mixer).

PC 99

Refers to the PC 99 System Design Guide published by the Microsoft

Corporation [7].

PLL

Phase Lock Loop. Circuitry for generating a desired clock from an external clock source.

Resolution

The number of bits in the output words to the DACs, and in the input words to the ADCs.

Signal to Noise Ratio (SNR)

SNR, similar to DR, is the ratio of an arbitrary sinusoidal input signal to the RMS sum of the noise floor,
in the presence of a signal. It is measured over a 20 Hz to 20 kHz bandwidth with units in dB.

S/PDIF

Sony/Phillips Digital Interface. This interface was established as a means of digitally interconnecting
consumer audio equipment. The documentation for S/PDIF has been superseded by the IEC-958
consumer digital interface document.

SRC

Sample Rate Converter. Converts data derived at one sample rate to a differing sample rate. The
CS4297A operates at a fixed sample frequency of 48 kHz. The internal sample rate converters are used
to convert digital audio streams playing back at other frequencies to 48 kHz.

Total Harmonic Distortion plus Noise (THD+N)

THD+N is the ratio of the RMS sum of all non-fundamental frequency components, divided by the RMS
full-scale signal level. It is tested using a -3 dB FS input signal and is measured over a 20 Hz to 20 kHz
bandwidth with units in dB FS.

CS4297A

11. REFERENCE DESIGN

22pF

1uF

Y5V

1uF

X7R

HDR-

1uF

Y5V

1uF

X7R

1uF

X7R

47K

1uF

X7R

O-1/

1uF

X7R

1uF

X7R

1uF

Y5V

O-1/

1uF

X7R

1uF

Y5V

10uF

ELEC

1000pF

24.

576 M

HDR-

100K

1uF

Y5V

10uF

ELEC

1uF

Y5V

HDR-

100K

1uF

X7R

1000pF

4297A

AVdd2

ALT

_LI

ALT

_LI

ss2

FLTO

FLTI

dd1

XTL_I

XTL_O

ss1

A_OU

ss2

A_I

SYN

dd2

ESET

_BEEP

X_L

X_R

O_L

O_R

CD_

AVdd1

ss1

FFL

Vref

out

I
F

_OU

EAPD

-
1

1uF

Y5V

1uF

Y5V

2700pF

X7R

60 m

il t

r
ac

ND_

TIE

1000pF

100K

1uF

X7R

01uF

X7R

78M

05AC

GND

O-1/

1000pF

1uF

Y5V

1000pF

100

1uF

X7R

10uF

ELEC

10uF

ELEC

10uF

ELEC

220K

1uF

Y5V

220K

AGN

12V

AGN

.
3

AGN

ABI

ASD

I
N

ASYN

ASD

PC SPEAKER

CD IN

MIC IN

AUX IN

LINE IN

LINE OUT

i
e at

one point

only

under t

he c

odec

I
N

I
A

udio C

ont

r
o

ller

ont

r
o

ller

(50 PPM

)

S/PDIF OUT

re 23.

CS429

7A Reference Des

i
g

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CS4297A-JQ