Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 1999
(All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CS4334/5/6/7/8/9
8-Pin, 24-Bit, 96 kHz Stereo D/A Converter
Features
l
Complete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
l
24-Bit Conversion
l
96 dB Dynamic Range
l
-88 dB THD+N
l
Low Clock Jitter Sensitivity
l
Single +5 V Power Supply
l
Filtered Line Level Outputs
l
On-Chip Digital De-emphasis
l
Popgaurd
Technology
l
Functionally Compatible with CS4330/31/33
Description
The CS4334 family members are complete, stereo digi-
tal-to-analog output systems including interpolation, 1-bit
D/A conversion and output analog filtering in an 8-pin
package. The CS4334/5/6/7/8/9 support all major audio
data interface formats, and the individual devices differ
only in the supported interface format.
The CS4334 family is based on delta-sigma modulation,
where the modulator output controls the reference volt-
age input to an ultra-linear analog low-pass filter. This
architecture allows for infinite adjustment of sample rate
between 2 kHz and 100 kHz simply by changing the
master clock frequency.
The CS4334 family contains on-chip digital de-empha-
sis, operates from a single +5V power supply, and
requires minimal support circuitry. These features are
ideal for set-top boxes, DVD players, SVCD players, and
A/V receivers.
ORDERING INFORMATION
See page 23
I
LRCK
3
SDATA
1
DEM/SCLK
2
MCLK
4
VA
AOUTL
8
AOUTR
5
Serial Input
Interface
Interpolator
Interpolator
De-emphasis
Modulator
Modulator
DAC
DAC
Voltage Reference
Analog
Low-Pass
Filter
Analog
Low-Pass
Filter
7
AGND
6
SEP `99
DS248PP3
CS4334/5/6/7/8/9
2
DS248PP3
TABLE OF CONTENTS
1. CHARACTERISTICS/SPECIFICATIONS ...................................................... 4
ANALOG CHARACTERISTICS................................................................... 4
POWER AND THERMAL CHARACTERISTICS ......................................... 6
DIGITAL CHARACTERISTICS.................................................................... 7
ABSOLUTE MAXIMUM RATINGS .............................................................. 7
RECOMMENDED OPERATING CONDITIONS .......................................... 7
SWITCHING CHARACTERISTICS ............................................................. 8
2. TYPICAL CONNECTION DIAGRAM ........................................................... 10
3. GENERAL DESCRIPTION .......................................................................... 11
3.1 Digital Interpolation Filter ................................................................... 11
3.2 Delta-Sigma Modulator ...................................................................... 11
3.3 Switched-Capacitor DAC ................................................................... 11
3.4 Analog Low-Pass Filter ...................................................................... 11
4. SYSTEM DESIGN ........................................................................................ 12
4.1 Master Clock ...................................................................................... 12
4.2 Serial Clock ........................................................................................ 12
4.2.1 External Serial Clock Mode ...................................................... 12
4.2.2 Internal Serial Clock Mode ....................................................... 12
4.3 De-Emphasis ..................................................................................... 12
4.4 Initialization and Power-Down ........................................................... 12
4.5 Output Transient Control ................................................................... 13
4.6 Grounding and Power Supply Decoupling ......................................... 13
4.7 Analog Output and Filtering ............................................................... 13
4.8 Overall Base-Rate Frequency Response .......................................... 17
4.9 Overall High-Rate Frequency Response ........................................... 18
4.10 Base Rate Mode Performance Plots ............................................... 19
4.11 High Rate Mode Performance Plots ................................................ 20
5. PIN DESCRIPTIONS ................................................................................... 21
6. PARAMETER DEFINITIONS ....................................................................... 22
7. REFERENCES ............................................................................................. 22
8. ORDERING INFORMATION: ...................................................................... 23
9. FUNCTIONAL COMPATIBILITY ................................................................. 23
10. PACKAGE DIMENSIONS .......................................................................... 24
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.
CS4334/5/6/7/8/9
DS248PP3 3
LIST OF FIGURES
Figure 1.Output Test Load .................................................................................... 6
Figure 2.Maximum Loading................................................................................... 6
Figure 3.Power vs. Sample Rate .......................................................................... 6
Figure 4.External Serial Mode Input Timing.......................................................... 9
Figure 5.Internal Serial Mode Input Timing ........................................................... 9
Figure 6. Internal Serial Clock Generation ............................................................ 9
Figure 7.Recommended Connection Diagram.................................................... 10
Figure 8.System Block Diagram.......................................................................... 11
Figure 9.De-Emphasis Curve (Fs = 44.1kHz) ..................................................... 13
Figure 10.CS4334 Data Format (I
2
S).................................................................. 14
Figure 11.CS4335 Data Format .......................................................................... 14
Figure 12.CS4336 Data Format .......................................................................... 14
Figure 13.CS4337 Data Format .......................................................................... 15
Figure 14.CS4338 Data Format .......................................................................... 15
Figure 15.CS4339 Data Format .......................................................................... 15
Figure 16.CS4334/5/6/7/8/9 Initialization and Power-Down Sequence .............. 16
Figure 17.Stopband Rejection............................................................................. 17
Figure 18.Transition Band................................................................................... 17
Figure 19.Transition Band................................................................................... 17
Figure 20.Passband Ripple................................................................................. 17
Figure 21.Stopband Rejection............................................................................. 18
Figure 22.Transition Band................................................................................... 18
Figure 23.Transition Band................................................................................... 18
Figure 24.Passband Ripple................................................................................. 18
Figure 25.0 dBFS FFT (BRM) ............................................................................. 19
Figure 26. -60 dBFS FFT (BRM)......................................................................... 19
Figure 27.Idle Channel Noise FFT (BRM)........................................................... 19
Figure 28.Twin Tone IMD FFT (BRM)................................................................. 19
Figure 29.THD+N vs. Amplitude (BRM) .............................................................. 19
Figure 30.THD+N vs. Frequency (BRM) ............................................................. 19
Figure 31.0 dBFS FFT (HRM)............................................................................. 20
Figure 32. -60 dBFS FFT (HRM)......................................................................... 20
Figure 33.Idle Channel Noise FFT (HRM) .......................................................... 20
Figure 34.Twin Tone IMD FFT (HRM) ................................................................ 20
Figure 35.THD+N vs. Amplitude (HRM).............................................................. 20
Figure 36. THD+N vs. Frequency (HRM)............................................................ 20
CS4334/5/6/7/8/9
4
DS248PP3
1. CHARACTERISTICS/SPECIFICATIONS
ANALOG CHARACTERISTICS
(T
A
= 25 C; Logic "1" = VA = 5 V; Logic "0" = AGND;
Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz,
Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for High-Rate Mode = 96 kHz,
SCLK = 6.144 MHz, Measurement Bandwidth 10 Hz to 40 kHz, unless otherwise specified. Test load R
L
= 10 k
,
C
L
= 10 pF (see Figure 1))
Notes: 1. One-half LSB of triangular PDF dither added to data.
Parameter
Base-rate Mode
High-Rate Mode
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Dynamic Performance for CS4334/5/6/7/8/9-KS
Specified Temperature Range
T
A
-10
-
70
-10
-
70
C
Dynamic Range
(Note 1)
18 to 24-Bit
unweighted
A-Weighted
16-Bit
unweighted
A-Weighted
88
91
86
89
93
96
91
94
-
-
-
-
-
91
-
89
90
96
88
94
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 1)
18 to 24-Bit
0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
THD+N
-
-
-
-
-
-
-88
-73
-33
-86
-71
-31
-83
-68
-28
-81
-66
-26
-
-
-
-
-
-
-88
-70
-30
-86
-68
-28
-83
-65
-25
-81
-63
-23
dB
dB
dB
dB
dB
dB
Interchannel Isolation
(1 kHz)
-
94
-
-
95
-
dB
Dynamic Performance for CS4334/5/6/7/8/9-BS
Specified Temperature Range
T
A
-40
-
85
-40
-
85
C
Dynamic Range
(Note 1)
18 to 24-Bit
unweighted
A-Weighted
16-Bit
unweighted
A-Weighted
85
88
83
86
93
96
91
94
-
-
-
-
-
88
-
86
90
96
88
94
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 1)
18 to 24-Bit
0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
THD+N
-
-
-
-
-
-
-88
-73
-33
-86
-71
-31
-82
-65
-25
-70
-63
-23
-
-
-
-
-
-
-88
-70
-30
-86
-68
-28
-82
-62
-22
-80
-60
-20
dB
dB
dB
dB
dB
dB
Interchannel Isolation
(1 kHz)
-
94
-
-
95
-
dB
CS4334/5/6/7/8/9
DS248PP3
5
ANALOG CHARACTERISTICS
(Continued)
Notes: 2. Filter response is not tested but is guaranteed by design.
3. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 17-24) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
4. For Base-Rate Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For High-Rate Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
5. De-emphasis is not available in High-Rate Mode.
6. Refer to Figure 2.
Parameter
Base-rate Mode
High-Rate Mode
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Combined Digital and On-chip Analog Filter Response
(Note 2)
Passband
(Note 3)
to -0.05 dB corner
to -0.1 dB corner
to -3 dB corner
0
-
0
-
-
-
.4780
-
.4996
-
0
0
-
-
-
-
.4650
.4982
Fs
Fs
Fs
Frequency Response 10 Hz to 20 kHz
-.01
-
+.08
-.05
-
+.2
dB
Passband Ripple
-
-
.08
-
-
.2
dB
StopBand
.5465
-
-
.5770
-
-
Fs
StopBand Attenuation
(Note 4)
50
-
-
55
-
-
dB
Group Delay
tgd
-
9/Fs
-
-
4/Fs
-
s
Passband Group Delay Deviation 0 - 40 kHz
0 - 20 kHz
-
0.36/Fs
-
-
-
1.39/Fs
0.23/Fs
-
-
s
s
De-emphasis Error
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
+1.5/+0
+.05/-.25
-.2/-.4
(Note 5)
dB
dB
dB
Parameters
Symbol
Min
Typ
Max
Units
dc Accuracy
Interchannel Gain Mismatch
-
0.1
0.4
dB
Gain Error
-
5
-
%
Gain Drift
-
100
-
ppm/C
Analog Output
Full Scale Output Voltage
3.25
3.5
3.75
Vpp
Quiescent Voltage
V
Q
-
2.2
-
VDC
Max AC-Load Resistance
(Note 6)
R
L
-
3
-
k
Max Load Capacitance
(Note 6)
C
L
-
100
-
pF
CS4334/5/6/7/8/9
6
DS248PP3
POWER AND THERMAL CHARACTERISTICS
Notes: 7. Refer to Figure 3. Max Power Dissipation is measured at VA=5.5V.
Parameters
Symbol
Min
Typ
Max
Units
Power Supplies
Power Supply Current
normal operation
power-down state
I
A
I
A
-
-
15
40
19
-
mA
A
Power Dissipation
(Note 7)
normal operation
power-down
-
-
75
0.2
104
-
mW
mW
Package Thermal Resistance
JA
-
110
-
C/Watt
Power Supply Rejection Ratio
(1 kHz)
PSRR
-
79
-
dB
AOUTx
AGND
10 F
V
out
R
L
C
L
Figure 1. Output Test Load
100
50
75
25
2.5
5
10
15
Safe Operating
Region
C
a
p
a
c
i
t
i
ve
Lo
ad
--
C
(
p
F
)
L
Resistive Load -- R (k
)
L
125
3
20
Figure 2. Maximum Loading
75
50
30
Po
w
e
r
(
m
W
)
Sample Rate (kHz)
B
R
M
HR
M
70
65
60
55
40
50
60
70
80
90
100
Figure 3. Power vs. Sample Rate
CS4334/5/6/7/8/9
DS248PP3
7
DIGITAL CHARACTERISTICS
(T
A
= 25C; VA = 4.75V - 5.5V)
Notes: 8. I
in
for CS433X LRCK is 20
A max.
ABSOLUTE MAXIMUM RATINGS
(AGND = 0V; all voltages with respect to ground.)
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND = 0V; all voltages with respect to ground.)
Parameters
Symbol Min Typ
Max
Units
High-Level Input Voltage
V
IH
2.0
-
-
V
Low-Level Input Voltage
V
IL
-
-
0.8
V
Input Leakage Current
(Note 8)
I
in
-
-
10
A
Input Capacitance
-
8
-
pF
Parameters
Symbol
Min
Max
Units
DC Power Supply
VA
-0.3
6.0
V
Input Current, Any Pin Except Supplies
I
in
-
10
mA
Digital Input Voltage
V
IND
-0.3
VA+0.4
V
Ambient Operating Temperature (power applied)
T
A
-55
125
C
Storage Temperature
T
stg
-65
150
C
Parameters
Symbol Min Typ
Max
Units
DC Power Supply
VA
4.75
5.0
5.5
V
CS4334/5/6/7/8/9
8
DS248PP3
SWITCHING CHARACTERISTICS
(T
A
= -40 to 85C; VA = 4.75V - 5.5V; Inputs: Logic 0 = 0V,
Logic 1 = VA, CL = 20pF)
Notes: 9. In Internal SCLK Mode, the Duty Cycle must be 50%
+/-
1/2 MCLK Period.
10. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK
ratio. (See figures 10-15)
Parameters
Symbol Min Typ
Max
Units
Input Sample Rate
Fs
2
-
100
kHz
MCLK Pulse Width High
MCLK/LRCK = 512
10
-
1000
ns
MCLK Pulse Width Low
MCLK/LRCK = 512
10
-
1000
ns
MCLK Pulse Width High MCLK / LRCK = 384 or 192
21
-
1000
ns
MCLK Pulse Width Low
MCLK / LRCK = 384 or 192
21
-
1000
ns
MCLK Pulse Width High MCLK / LRCK = 256 or 128
31
-
1000
ns
MCLK Pulse Width Low
MCLK / LRCK = 256 or 128
31
-
1000
ns
External SCLK Mode
LRCK Duty Cycle (External SCLK only)
40
50
60
%
SCLK Pulse Width Low
t
sclkl
20
-
-
ns
SCLK Pulse Width High
t
sclkh
20
-
-
ns
SCLK Period
MCLK / LRCK = 512, 256 or 384
t
sclkw
-
-
ns
SCLK Period
MCLK / LRCK = 128 or 192
t
sclkw
-
-
ns
SCLK rising to LRCK edge delay
t
slrd
20
-
-
ns
SCLK rising to LRCK edge setup time
t
slrs
20
-
-
ns
SDATA valid to SCLK rising setup time
t
sdlrs
20
-
-
ns
SCLK rising to SDATA hold time
t
sdh
20
-
-
ns
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only)
(Note 9)
-
50
-
%
SCLK Period
(Note 10)
t
sclkw
-
-
ns
SCLK rising to LRCK edge
t
sclkr
-
-
s
SDATA valid to SCLK rising setup time
t
sdlrs
-
-
ns
SCLK rising to SDATA hold time
MCLK / LRCK = 512, 256 or 128
t
sdh
-
-
ns
SCLK rising to SDATA hold time
MCLK / LRCK = 384 or 192
t
sdh
-
-
ns
1
128
(
)
Fs
----------------------
1
64
( )
Fs
-------------------
1
SCLK
-----------------
tsclkw
2
------------------
1
512
(
)
Fs
----------------------
10
+
1
512
(
)
Fs
----------------------
15
+
1
384
(
)
Fs
----------------------
15
+
CS4334/5/6/7/8/9
DS248PP3
9
sclkh
t
slrs
t
slrd
t
sdlrs
t
sdh
t
sclkl
t
SDATA
SCLK
LRCK
Figure 4. External Serial Mode Input Timing
SDATA
*INTERNAL SCLK
LRCK
sclkw
t
sdlrs
t
sdh
t
sclkr
t
Figure 5. Internal Serial Mode Input Timing
* The SCLK pulses shown are internal to the CS4334/5/6/7/8/9.
SDATA
LRCK
MCLK
*INTERNAL SCLK
1
N
2
N
Figure 6. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4334/5/6/7/8/9.
N equals MCLK divided by SCLK
CS4334/5/6/7/8/9
10
DS248PP3
2. TYPICAL CONNECTION DIAGRAM
DEM/SCLK
6
Audio
Data
Processor
External Clock
MCLK
AGND
AOUTR
CS4334
CS4335
CS4336
CS4337
CS4338
CS4339
SDATA
LRCK
VA
AOUTL
3
1
2
4
7
0.1 F
+
1 F
8
Left Audio
Output
5
Right Audio
Output
+5V
3.3 F
10 k
C
560
+
R + 560
C =
4
Fs(R 560)
267 k
R L
3.3 F
10 k
C
560
+
267 k
R L
L
L
Figure 7. Recommended Connection Diagram
CS4334/5/6/7/8/9
DS248PP3
11
3. GENERAL DESCRIPTION
The CS4334 family of devices offers a complete
stereo digital-to-analog system including digital in-
terpolation, fourth-order delta-sigma digital-to-an-
alog conversion, digital de-emphasis and analog
filtering, as shown in Figure 8. This architecture
provides a high tolerance to clock jitter.
The primary purpose of using delta-sigma modula-
tion techniques is to avoid the limitations of resis-
tive laser trimmed digital-to-analog converter
architectures by using an inherently linear 1-bit
digital-to-analog converter. The advantages of a 1-
bit digital-to-analog converter include: ideal differ-
ential linearity, no distortion mechanisms due to re-
sistor matching errors and no linearity drift over
time and temperature due to variations in resistor
values.
The CS4334 family of devices supports two modes
of operation. The devices operate in Base Rate
Mode (BRM) when MCLK/LRCK is 256, 384 or
512 and in High Rate Mode (HRM) when
MCLK/LRCK is 128 or 192. High Rate Mode al-
lows input sample rates up to 100 kHz.
3.1 Digital Interpolation Filter
The digital interpolation filter increases the sample
rate, Fs, by a factor of 4 and is followed by a
32 digital sample-and-hold (16 in HRM). This
filter eliminates images of the baseband audio sig-
nal which exist at multiples of the input sample
rate. The resulting frequency spectrum has images
of the input signal at multiples of 4 Fs. These imag-
es are easily removed by the on-chip analog low-
pass filter and a simple external analog filter (see
Figure 7).
3.2 Delta-Sigma Modulator
The interpolation filter is followed by a fourth or-
der delta-sigma modulator which converts the in-
terpolation filter output into 1-bit data at a rate of
128 Fs in BRM (or 64 Fs in HRM)
.
3.3 Switched-Capacitor DAC
The delta-sigma modulator is followed by a digital-
to-analog converter which translates the 1-bit data
into a series of charge packets. The magnitude of
the charge in each packet is determined by sam-
pling of a voltage reference onto a switched capac-
itor, where the polarity of each packet is controlled
by the 1-bit data. This technique greatly reduces the
sensitivity to clock jitter and provides low-pass fil-
tering of the output.
3.4 Analog Low-Pass Filter
The final signal stage consists of a continuous-time
low-pass filter which serves to smooth the output
and attenuate out-of-band noise.
Interpolator
Delta-Sigma
Modulator
DAC
Analog
Low-Pass
Filter
Analog
Output
Digital
Input
Figure 8. System Block Diagram
CS4334/5/6/7/8/9
12
DS248PP3
4. SYSTEM DESIGN
The CS4334 family accepts data at standard audio
sample rates including 48, 44.1 and 32 kHz in
BRM and 96, 88.2 and 64 kHz in HRM. Audio data
is input via the serial data input pin (SDATA). The
Left/Right Clock (LRCK) defines the channel and
delineation of data, and the Serial Clock (SCLK)
clocks audio data into the input data buffer. The
CS4334/5/6/7/8/9 differ in serial data formats as
shown in Figures 10-15.
4.1 Master Clock
MCLK must be either 256
x
, 384
x
or 512
x
the de-
sired input sample rate in BRM and either 128
x
or
192
x
the desired input sample rate in HRM. The
LRCK frequency is equal to Fs, the frequency at
which words for each channel are input to the de-
vice. The MCLK-to-LRCK frequency ratio is de-
tected automatically during the initialization
sequence by counting the number of MCLK transi-
tions during a single LRCK period. Internal divid-
ers are set to generate the proper clocks. Table 1
illustrates several standard audio sample rates and
the required MCLK and LRCK frequencies. Please
note there is no required phase relationship, but
MCLK, LRCK and SCLK must be synchronous.
Table 1. Common Clock Frequencies
4.2 Serial Clock
The serial clock controls the shifting of data into
the input data buffers. The CS4334 family supports
both external and internal serial clock generation
modes. Refer to Figures 10-15 for data formats.
4.2.1 External Serial Clock Mode
The CS4334 family will enter the External Serial
Clock Mode when 16 low to high transitions are
detected on the DEM/SCLK pin during any phase
of the LRCK period. When this mode is enabled,
the Internal Serial Clock Mode and de-emphasis
filter cannot be accessed. The CS4334 family will
switch to Internal Serial Clock Mode if no low to
high transitions are detected on the DEM/SCLK
pin for 2 consecutive frames of LRCK. Refer to
Figure 16.
4.2.2 Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock
is internally derived and synchronous with MCLK
and LRCK. The SCLK/LRCK frequency ratio is ei-
ther 32, 48, or 64 depending upon data format. Op-
eration in this mode is identical to operation with
an external serial clock synchronized with LRCK.
This mode allows access to the digital de-emphasis
function. Refer to Figures 10 - 16 for details.
While the Internal Serial Clock Mode is provided
to allow access to the de-emphasis filter, the Inter-
nal Serial Clock Mode also eliminates possible
clock interference from an external SCLK.
4.3 De-Emphasis
The CS4334 family includes on-chip digital de-em-
phasis. Figure 9 shows the de-emphasis curve for
Fs equal to 44.1 kHz. The frequency response of
the de-emphasis curve will scale proportionally
with changes in sample rate, Fs.
The de-emphasis filter is active (inactive) if the
DEM/SCLK pin is low (high) for 5 consecutive
falling edges of LRCK. This function is available
only in the internal serial clock mode.
4.4 Initialization and Power-Down
The Initialization and Power-Down sequence flow
chart is shown in Figure 16. The CS4334 family en-
ters the Power-Down State upon initial power-up.
LRCK
(kHz)
MCLK (MHz)
HRM
BRM
128x
192x
256x
384x
512x
32
4.0960
6.1440
8.1920 12.2880 16.3840
44.1
5.6448
8.4672 11.2896 16.9344 22.5792
48
6.1440
9.2160 12.2880 18.4320 24.5760
64
8.1920 12.2880
-
-
-
88.2
11.2896 16.9344
-
-
-
96
12.2880 18.4320
-
-
-
CS4334/5/6/7/8/9
DS248PP3
13
The interpolation filters and delta-sigma modula-
tors are reset, and the internal voltage reference,
one-bit digital-to-analog converters and switched-
capacitor low-pass filters are powered down. The
device will remain in the Power-Down mode until
MCLK and LRCK are present. Once MCLK and
LRCK are detected, MCLK occurrences are count-
ed over one LRCK period to determine the
MCLK/LRCK frequency ratio. Power is then ap-
plied to the internal voltage reference. Finally, pow-
er is applied to the D/A converters and switched-
capacitor filters, and the analog outputs will ramp to
the quiescent voltage, V
Q
.
4.5 Output Transient Control
The CS4334 family uses Popgaurd
technology to
minimize the effects of output transients during
power-up and power-down. This technique elimi-
nates the audio transients commonly produced by
single-ended single-supply converters when it is
implemented with external DC-blocking capacitors
connected in series with the audio outputs. To
make best use of this feature, it is necessary to un-
derstand its operation.
When the device is initially powered-up, the audio
outputs, AOUTL and AOUTR, are clamped to
AGND. After a short delay of approximately 1000
sample periods, each output begins to ramp to-
wards its quiescent voltage, V
Q
. Approximately
10,000 sample cycles later, the outputs reach V
Q
and audio output begins. This gradual voltage
ramping allows time for the external DC-blocking
capacitor to charge to V
Q
, effectively blocking the
quiescent DC voltage.
To prevent transients at power-down, the device
must first enter its power-down state. This is ac-
complished by removing MCLK or LRCK. When
this occurs, audio output ceases and the internal
output buffers are disconnected from AOUTL and
AOUTR. A soft-start current sink is substituted in
place of AOUTL and AOUTR which allows the
DC-blocking capacitors to slowly discharge. Once
this charge is dissipated, the power to the device
may be turned off, and the system is ready for the
next power-on.
To prevent an audio transient at the next power-on,
the DC-blocking capacitors must fully discharge
before turning off the power or exiting the power-
down state. If full discharge does not occur, a tran-
sient will occur when the audio outputs are initially
clamped to AGND. The time that the device must
remain in the power-down state is related to the
value of the DC-blocking capacitance. For exam-
ple, with a 3.3
F capacitor, the time that the device
must remain in the power-down state will be ap-
proximately 0.4 seconds.
4.6 Grounding and Power Supply
Decoupling
As with any high resolution converter, the CS4334
family requires careful attention to power supply
and grounding arrangements to optimize perfor-
mance. Figure 7 shows the recommended power ar-
rangement with VA connected to a clean +5V
supply. For best performance, decoupling capaci-
tors should be located as close to the device pack-
age as possible with the smallest capacitor closest.
4.7 Analog Output and Filtering
The analog filter present in the CS4334 family is a
switched-capacitor filter followed by a continuous
time low pass filter. Its response, combined with
that of the digital interpolator, is given in Figures
17 - 24.
Gain
dB
-10dB
0dB
Frequency
T2 = 15 s
T1=50 s
F1
F2
3.183 kHz
10.61 kHz
Figure 9. De-Emphasis Curve (Fs = 44.1kHz)
CS4334/5/6/7/8/9
14
DS248PP3
LRCK
SCLK
Left Channel
Right Channel
SDATA
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4
Internal SCLK Mode
External SCLK Mode
I
2
S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128
I
2
S, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
I
2
S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 10. CS4334 Data Format (I
2
S)
LRCK
SCLK
Left Channel
Right Channel
SDATA
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4
Internal SCLK Mode
External SCLK Mode
Left Justified, up to 24-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Left Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 11. CS4335 Data Format
LRCK
SCLK
Left Channel
SDATA
6
5
4
3
2
1
0
7
23 22 21 20 19 18
6
5
4
3
2
1
0
7
23 22 21 20 19 18
32 clocks
0
Right Channel
Internal SCLK Mode
External SCLK Mode
Right Justified, 24-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 24-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 48 Cycles per LRCK Period
Figure 12. CS4336 Data Format
CS4334/5/6/7/8/9
DS248PP3
15
LRCK
SCLK
Left Channel
Right Channel
SDATA
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
1
0
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
17 16
17 16
32 clocks
19 18
19 18
Internal SCLK Mode
External SCLK Mode
Right Justified, 20-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 20-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 40 Cycles per LRCK Period
Figure 13. CS4337 Data Format
LRCK
SCLK
Left Channel
Right Channel
SDATA
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
32 clocks
Internal SCLK Mode
External SCLK Mode
Right Justified, 16-Bit Data
INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
Figure 14. CS4338 Data Format
LRCK
SCLK
Left Channel
Right Channel
SDATA
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
1
0
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
17 16
17 16
32 clocks
Internal SCLK Mode
External SCLK Mode
Right Justified, 18-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 18-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 36 Cycles per LRCK Period
Figure 15. CS4339 Data Format
CS4334/5/6/7/8/9
16
DS248PP3
Figure 16. CS4334/5/6/7/8/9 Initialization and Power-Down Sequence
CS4334/5/6/7/8/9
DS248PP3
17
4.8 Overall Base-Rate Frequency Response
Figure 17. Stopband Rejection
Figure 18. Transition Band
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.02
0
0.02
0.04
0.06
0.08
0.1
Amplitude dB
Frequency (normalized to Fs)
Figure 19. Transition Band
Figure 20. Passband Ripple
CS4334/5/6/7/8/9
18
DS248PP3
4.9 Overall High-Rate Frequency Response
Figure 21. Stopband Rejection
Figure 22. Transition Band
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.15
0.1
0.05
0
0.05
0.1
0.15
0.2
0.25
Amplitude dB
Frequency (normalized to Fs)
Figure 23. Transition Band
Figure 24. Passband Ripple
CS4334/5/6/7/8/9
DS248PP3
19
4.10 Base Rate Mode Performance Plots
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k
20k
4k
6k
8k
10k
12k
14k
16k
18k
Hz
2k
4k
6k
8k
10k
12k
14k
16k
18k
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dB
r
A
Hz
20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
d
Br A
2k
6k
4k
8k
10k
12k
14k
16k
18k
20k
Hz
-140
+ 0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k
20k
4k
6k
8k
10k
12k
14k
16k
18k
Hz
20k
2k
4k
6k
8k
10k
12k
14k
16k
18k
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dB
r
A
Hz
20k
2k
6k
4k
8k
10k
12k
14k
16k
18k
20k
Hz
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
dBr
A
(16k FFT of a 1 kHz input signal)
Figure 25. 0 dBFS FFT (BRM)
(16k FFT of a 1 kHz input signal)
Figure 26. -60 dBFS FFT (BRM)
-140
+ 0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k
20k
4k
6k
8k
10k
12k
14k
16k
18k
Hz
2k
4k
6k
8k
10k
12k
14k
16k
18k
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dB
r
A
Hz
20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
dBr
A
2k
6k
4k
8k
10k
12k
14k
16k
18k
20k
Hz
-140
+ 0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k
20k
4k
6k
8 k
10k
12k
14k
1 6k
18k
H z
2k
4k
6k
8k
10k
12k
14k
16k
18k
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dB
r
A
Hz
20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
dBr
A
2k
6k
4k
8k
10k
12k
14k
16k
18k
20k
Hz
(16k FFT with no input signal)
Figure 27. Idle Channel Noise FFT (BRM)
(16k FFT of intermodulation distortion using 13 kHz and 14 kHz input signals)
Figure 28. Twin Tone IMD FFT (BRM)
-110
-60
-100
-90
-80
-70
d
B
r
A
-60
+0
-50
-40
-30
-20
-10
dBFS
-50
-40
-30
-20
-10
dBFS
-60
+0
-110
-100
-90
-80
-70
-60
dB
r
A
-110
+0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
d
B
r
A
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
dB
r A
100
50
200
500
1k
2k
5k
10k
Hz
20
20k
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
Figure 29. THD+N vs. Amplitude (BRM)
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
Figure 30. THD+N vs. Frequency (BRM)
All measurements were taken from the CDB4334 evaluation board using the Audio Precision Dual Domain
System Two Cascade.
CS4334/5/6/7/8/9
20
DS248PP3
4.11 High Rate Mode Performance Plots
-140
+ 0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k
20k
4k
6k
8k
10k
12k
14k
16k
18k
Hz
2k
4k
6k
8k
10k
12k
14k
16k
18k
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dB
r
A
Hz
20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
dB
r
A
2k
6k
4k
8k
10k
12k
14k
16k
18k
20k
Hz
-140
+ 0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k
20k
4k
6k
8k
10k
12k
14k
16k
18k
Hz
2k
4k
6k
8k
10k
12k
14k
16k
18k
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dB
r
A
Hz
20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
dBr
A
2k
6k
4k
8k
10k
12k
14k
16k
18k
20k
Hz
(16k FFT of a 1 kHz input signal)
Figure 31. 0 dBFS FFT (HRM)
(16k FFT of a 1 kHz input signal)
Figure 32. -60 dBFS FFT (HRM)
-140
+ 0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k
20k
4k
6k
8k
10k
12k
14k
16k
18k
Hz
2k
4k
6k
8k
10k
12k
14k
16k
18k
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dB
r
A
Hz
20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
dB
r
A
2k
6k
4k
8k
10k
12k
14k
16k
18k
20k
Hz
A ud io P re c is io n
0 8 /0 5 /9 9 1 1 :1 1 :3 6
D -A C C IF IMD vs A MP L IT UD E
-140
+ 0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
2k
20k
4k
6k
8k
10k
12k
14k
16k
18k
Hz
2k
4k
6k
8k
10k
12k
14k
16k
18k
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dB
r
A
Hz
20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
dB
r
A
2k
6k
4k
8k
10k
12k
14k
16k
18k
20k
Hz
(16k FFT with no input signal)
Figure 33. Idle Channel Noise FFT (HRM)
(16k FFT of intermodulation distortion using 13 kHz and 14 kHz input signals)
Figure 34. Twin Tone IMD FFT (HRM)
-110
-60
-100
-90
-80
-70
d
B
r
A
-60
+0
-50
-40
-30
-20
-10
dBFS
-50
-40
-30
-20
-10
dBFS
-60
+0
-110
-100
-90
-80
-70
-60
dB
r A
-110
+0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
d
B
r
A
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
100
50
200
500
1k
2k
5k
10k
Hz
20
20k
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
dB
r
A
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
Figure 35. THD+N vs. Amplitude (HRM)
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
Figure 36. THD+N vs. Frequency (HRM)
All measurements were taken from the CDB4334 evaluation board using the Audio Precision Dual Domain
System Two Cascade.
CS4334/5/6/7/8/9
DS248PP3
21
5. PIN DESCRIPTIONS
No.
Pin Name
I/O
Pin Function and Description
1
SDATA
I
Serial Audio Data Input
- two's complement MSB-first serial data is input on this pin.
The data is clocked into the CS4334/5/6/7/8/9 via internal or external SCLK, and the
channel is determined by LRCK.
2
DEM/SCLK
I
De-Emphasis/External Serial Clock Input
- used for de-emphasis filter control or exter-
nal serial clock input.
3
LRCK
I
Left/Right Clock
- determines which channel is currently being input on the Audio Serial
Data Input pin, SDATA.
4
MCLK
I
Master Clock
- frequency must be 256x, 384x, or 512x the input sample rate in BRM and
either 128x or 192x the input sample rate in HRM.
5
AOUTR
O
Analog Right Channel Output
- typically 3.5 Vp-p for a full-scale input signal.
6
AGND
I
Analog Ground
- analog ground reference is 0V.
7
VA
I
Analog Power
- analog power supply is nominally +5V.
8
AOUTL
O
Analog Left Channel Output
- typically 3.5 Vp-p for a full-scale input signal.
SERIAL DATA INPUT
SDATA
AOUTL
ANALOG LEFT CHANNEL OUTPUT
DE-EMPHASIS / SCLK
DEM/SCLK
VA
ANALOG POWER
LEFT / RIGHT CLOCK
LRCK
AGND
ANALOG GROUND
MASTER CLOCK
MCLK
AOUTR
ANALOG RIGHT CHANNEL OUTPUT
7
2
6
3
5
4
8
1
CS4334/5/6/7/8/9
22
DS248PP3
6. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)- The ratio of the rms value of the signal to the
rms sum of all other spectral components over the specified bandwidth (typically 10Hz to
20kHz), including distortion components. Expressed in decibels.
Dynamic Range - The ratio of the full scale rms value of the signal to the rms sum of all other
spectral components over the specified bandwidth. Dynamic range is a signal-to-noise
measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added
to the resulting measurement to refer the measurement to full scale. This technique ensures that
the distortion components are below the noise level and do not effect the measurement. This
measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and
the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured
for each channel at the converter's output with all zeros to the input under test and a full-scale
signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch - The gain difference between left and right channels. Units in
decibels.
Gain Error - The deviation from the nominal full scale analog output for a full scale digital
input.
Gain Drift - The change in gain value with temperature. Units in ppm/
C.
7. REFERENCES
1) "How to Achieve Optimum Performance from
Delta-Sigma A/D & D/A Converters" by
Steven Harris. Paper presented at the 93rd Con-
vention of the Audio Engineering Society, Oc-
tober 1992.
2) CDB4334/5/6/7/8/9 Evaluation Board Datasheet
CS4334/5/6/7/8/9
DS248PP3
23
8. ORDERING INFORMATION:
9. FUNCTIONAL COMPATIBILITY
CS4330-KS
CS4339-KS
CS4331-KS
CS4334-KS
CS4333-KS
CS4338-KS
CS4330-BS
CS4339-BS
CS4331-BS
CS4334-BS
CS4333-BS
CS4338-BS
Model
Temperature
Package
Serial Interface
CS4334-KS
-10 to +70 C
8-pin Plastic SOIC
16 to 24-bit, I2S
CS4335-KS
-10 to +70 C
8-pin Plastic SOIC
16 to 24-bit, left justified
CS4336-KS
-10 to +70 C
8-pin Plastic SOIC
24-bit, right justified
CS4337-KS
-10 to +70 C
8-pin Plastic SOIC
20-bit, right justified
CS4338-KS
-10 to +70 C
8-pin Plastic SOIC
16-bit, right justified
CS4339-KS
-10 to +70 C
8-pin Plastic SOIC
18-bit, right justified, 32 F
s
Internal SCLK mode
CS4334-BS
-40 to +85 C
8-pin Plastic SOIC
16 to 24-bit, I2S
CS4335-BS
-40 to +85 C
8-pin Plastic SOIC
16 to 24-bit, left justified
CS4336-BS
-40 to +85 C
8-pin Plastic SOIC
24-bit, right justified
CS4337-BS
-40 to +85 C
8-pin Plastic SOIC
20-bit, right justified
CS4338-BS
-40 to +85 C
8-pin Plastic SOIC
16-bit, right justified
CS4339-BS
-40 to +85 C
8-pin Plastic SOIC
18-bit, right justified, 32 F
s
Internal SCLK mode
CS4334/5/6/7/8/9
24
DS248PP3
10. PACKAGE DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
A 0.053
0.069
1.35
1.75
A1
0.004
0.010
0.10
0.25
B
0.013
0.020
0.33
0.51
C
0.007
0.010
0.19
0.25
D
0.189
0.197
4.80
5.00
E
0.150
0.157
3.80
4.00
e
0.040
0.060
1.02
1.52
H
0.228
0.244
5.80
6.20
L
0.016
0.050
0.40
1.27
0
8
0
8
JEDEC # : MS-012
8L SOIC (150 MIL BODY) PACKAGE DRAWING
D
H
E
e
b
A1
A
c
L
SEATING
PLANE
1
Notes
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