Preliminary Product Information

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Cirrus Logic, Inc. 2001

P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com

CS4360

24-Bit, 192 kHz 6 Channel D/A Converter

Features

24-Bit Conversion

102 dB Dynamic Range

-90 dB THD+N

+3 V to +5 V Power Supply

Digital Volume Control with Soft Ramp

119 dB Attenuation
1 dB Step Size
Zero Crossing Click-Free Transitions

Low Power Consumption

105 mW with 3 V supply

ATAPI Mixing

Low Clock Jitter Sensitivity

Popguard Technology

for Control of Clicks

and Pops

Description

The CS4360 is a complete 6-channel digital-to-analog
system including digital interpolation, fourth-order delta-
sigma digital-to-analog conversion, digital de-emphasis,
volume control, channel mixing and analog filtering. The
advantages of this architecture include: ideal differential
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and tempera-
ture and a high tolerance to clock jitter.

The CS4360 accepts data at audio sample rates from
4 kHz to 200 kHz, consumes very little power and oper-
ates over a wide power supply range. These features are
ideal for cost-sensitive, multi-channel audio systems in-
cluding DVD players, A/V receivers, set-top boxes,
digital TVs and VCRs, mini-component systems, and
mixing consoles.

ORDERING INFORMATION

CS4360-KS

-10 to 70 °C

28-pin SOIC

CS4360-BS

-40 to 85 °C

28-pin SOIC

CS4360-KZ

-10 to 70 °C

28-pin TSSOP

CS4360-BZ

-40 to 85 °C

28-pin TSSOP

CDB4360

Evaluation Board

C o nt r o l P o rt

E xt e rn a l

M ut e C o nt r ol

R S T

V ol u m e C o nt r o l

I nt e r p o lat i o n F i lt e r

A n alo g F i lt e r

A O U T A1

D A C

Mi x e r

V ol u m e C o nt r o l

D A C

A n alo g F i lt e r

A O UT B1

I nt er p o lat i o n F i lt e r

V ol u m e C o nt r o l

I nt e r p o la ti o n F i lt e r

A n alo g Fi lt e r

A O U T A2

D A C

Mi x e r

V ol u m e C o nt r o l

D A C

A n alo g F i lt e r

A O UT B2

I nt er p o lat i o n F i lt e r

V ol u m e C o nt r o l

I nt e r p o la ti o n F i lt e r

A n alo g Fi lt e r

A O U T A3

D A C

Mi x e r

V ol u m e C o nt r o l

D A C

A n alo g F i lt e r

A O UT B3

I nt er p o lat i o n F i lt e r

M C L K

r
i
a

r
t

L R C K

S C L K

S D I N 1

S D I N 2

S D I N 3

DIF1/SCL/CCLK DIF0/SDA/CDIN M1/AD0/CS

VLC

FILT+

GND

VLS

MUTEC1

MUTEC2

MUTEC3

GND

FEB `01

DS517PP1

CS4360

DS517PP1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ......................................................................... 5

ANALOG CHARACTERISTICS ................................................................................................ 5
POWER AND THERMAL CHARACTERISTICS....................................................................... 7
DIGITAL CHARACTERISTICS ................................................................................................. 7
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 7
RECOMMENDED OPERATING CONDITIONS ....................................................................... 8
SWITCHING CHARACTERISTICS .......................................................................................... 9
SWITCHING CHARACTERISTICS- CONTROL PORT- TWO-WIRE FORMAT .................... 10
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................... 11

2. TYPICAL CONNECTION DIAGRAM....................................................................................... 12

3. REGISTER QUICK REFERENCE ........................................................................................... 13

4. REGISTER DESCRIPTIONS ................................................................................................... 14

4.1 Mode Control 1 (address 01h) ......................................................................................... 14
4.1.1 Auto-mute (AMUTE) ...................................................................................................... 14
4.1.2 Digital Interface Format (DIF) ........................................................................................ 14
4.1.3 De-Emphasis Control (DEM) ......................................................................................... 15
4.1.4 Functional Mode (FM).................................................................................................... 15
4.2 Invert Signal (address 02h)............................................................................................. 15
4.2.1 Invert Signal Polarity (INV_xx) ....................................................................................... 15
4.3 Mixing Control Pair 1 (Channels A1 & B1) (address 03h)

Mixing Control Pair 2 (Channels A2 & B2) (address 04h)
Mixing Control Pair 3 (Channels A3 & B3) (address 05h)............................................. 15

4.3.1 ATAPI Channel Mixing and Muting (ATAPI) .................................................................. 16
4.4 Volume Control (addresses 06h - 0Bh)............................................................................ 16
4.4.1 Mute (MUTE) ................................................................................................................ 16
4.4.2 Volume Control (xx_VOL) ............................................................................................. 17
4.5 Mode Control 2 (address 0Dh)........................................................................................ 17
4.5.1 Soft Ramp and Zero Cross Control (SZC) ..................................................................... 17
4.5.2 Control Port Enable (CPEN) .......................................................................................... 18
4.5.3 Power Down (PDN)........................................................................................................ 18
4.5.4 Popguard® Transient Control (POPG) ......................................................................... 18
4.5.5 Freeze Controls (FREEZE)............................................................................................ 18
4.5.6 Master Clock Divide Enable (MCLKDIV) ....................................................................... 18
4.5.7 Single Volume Control (SNGLVOL)............................................................................... 19
4.6 Revision Register (Read Only) (address 0Dh)............................................................... 19

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of
any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including
use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the
property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained
herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts
of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other
copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic,
Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some
jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at

http://www.cirrus.com

CS4360

DS517PP1

4.6.1 Revision Indicator (REV) [Read Only] ........................................................................... 19

5. PIN DESCRIPTION.................................................................................................................. 20

6. APPLICATIONS ...................................................................................................................... 23

6.1 Grounding and Power Supply Decoupling........................................................................ 23
6.2 Oversampling Modes........................................................................................................ 23
6.3 Recommended Power-up Sequence................................................................................ 23
6.4 Popguard® Transient Control........................................................................................... 23

7. CONTROL PORT INTERFACE............................................................................................... 24

7.1 Enabling the Control Port ................................................................................................. 24
7.2 Format Selection .............................................................................................................. 24
7.3 Two-Wire Format .............................................................................................................. 24

7.3.1 Writing in Two-Wire Format ................................................................................. 24
7.3.2 Reading in Two-Wire Format ............................................................................... 25

7.4 SPI Format ....................................................................................................................... 25

7.4.1 Writing in SPI ....................................................................................................... 25

7.5 Memory Address Pointer (MAP) ...................................................................................... 26
7.5.1 INCR (Auto Map Increment Enable) .............................................................................. 26
7.5.2 MAP (Memory Address Pointer) .................................................................................... 26

8. PARAMETER DEFINITIONS................................................................................................... 32

Total Harmonic Distortion + Noise (THD+N) .......................................................................... 32
Dynamic Range ...................................................................................................................... 32
Interchannel Isolation ............................................................................................................. 32
Interchannel Gain Mismatch ................................................................................................... 32
Gain Error ............................................................................................................................... 32
Gain Drift ................................................................................................................................ 32

9. REFERENCES......................................................................................................................... 32

10. PACKAGE DIMENSIONS ..................................................................................................... 33

LIST OF FIGURES

Figure 1.

Serial Mode Input Timing ............................................................................................... 9

Figure 2.

Control Port Timing - Two-Wire Format ....................................................................... 10

Figure 3.

Control Port Timing - SPI Format ................................................................................. 11

Figure 4.

Typical Connection Diagram ........................................................................................ 12

Figure 5.

Control Port Timing, Two-Wire Format ........................................................................ 25

Figure 6.

Control Port Timing, SPI Format .................................................................................. 25

Figure 7.

Base-Rate Stopband Rejection .................................................................................... 27

Figure 8.

Base-Rate Transition Band .......................................................................................... 27

Figure 9.

Base-Rate Transition Band (Detail) ............................................................................. 27

Figure 10. Base-Rate Passband Ripple ........................................................................................ 27
Figure 11. High-Rate Stopband Rejection .................................................................................... 27
Figure 12. High-Rate Transition Band ........................................................................................... 27
Figure 13. High-Rate Transition Band (Detail) .............................................................................. 28
Figure 14. High-Rate Passband Ripple ......................................................................................... 28
Figure 15. Output Test Load ......................................................................................................... 28
Figure 16. Maximum Loading ........................................................................................................ 28
Figure 17. CS4360 Format 0 - Left Justified upto 24-bit Data ....................................................... 29
Figure 18. CS4360 Format 1 - I

S upto 24-bit Data ...................................................................... 29

Figure 19. CS4360 Format 2 - Right Justified 16-bit Data ............................................................ 29
Figure 20. CS4360 Format 3 - Right Justified 24-bit Data ............................................................ 29
Figure 21. CS4360 Format 4 - Right Justified 20-bit Data ............................................................ 30

CS4360

DS517PP1

Figure 22. CS4360 Format 5 - Right Justified 18-bit Data ............................................................ 30
Figure 23. De-Emphasis Curve ..................................................................................................... 30
Figure 24. ATAPI Block Diagram .................................................................................................. 31

LIST OF TABLES

Table 1. Digital Interface Formats - Control Port Mode .................................................................... 14
Table 2. ATAPI Decode .................................................................................................................... 16
Table 3. Example Digital Volume Settings ....................................................................................... 17
Table 4. Digital Interface Formats - Stand Alone Mode.................................................................... 21
Table 5. Mode Selection................................................................................................................... 21
Table 6. Single-Speed Mode Common Clock Frequencies.............................................................. 22
Table 7. Double-Speed Mode Common Clock Frequencies ............................................................ 22
Table 8. Quad-Speed Mode Common Clock Frequencies............................................................... 22

CS4360

DS517PP1

CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS

(Full-Scale Output Sine Wave, 997 Hz; for Single-Speed Mode,

Fs = 48 kHz, SCLK = 3.072 MHz, MCLK = 12.288 MHz; for Double-Speed Mode Fs = 96 kHz, SCLK = 6.144 MHz,
MCLK = 12.288 MHz; for Quad-Speed Mode Fs = 192 kHz, SCLK = 12.288 MHz, MCLK = 24.576 MHz; Measure-
ment Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Test load R

= 10 k

= 10 pF (see Figure 15).

VA = VD = VLS = VLC),

Notes: 1. CS4360-KS/-KZ parts are tested at 25 °C.

2. One-half LSB of triangular PDF dither is added to data.

3. CS4360-BS/-BZ parts are tested at the extremes of the specified temperature range and Min/Max

performance numbers are guaranteed across the specified temperature range, T

. Typical numbers are

taken at 25 °C.

ANALOG CHARACTERISTICS

(Continued)

Parameter

VA = 5 V

VA = 3 V

Symbol

Min

Typ

Max

Min

Typ

Max

Unit

CS4360-KS/-KZ Dynamic Performance (Note 1)

Specified Temperature Range

-10

°C

Dynamic Range

(Note 2)

unweighted

A-Weighted

40 kHz Bandwidth

A-Weighted

TBD
TBD

102
100

-
-
-

TBD
TBD

94
97
97

-
-
-

dB
dB
dB

Total Harmonic Distortion + Noise

(Note 2)

0 dB

-20 dB
-60 dB

THD+N

-
-
-
-

-91
-79
-39

TBD

-
-

-
-
-

-91
-74
-34

TBD

-
-

dB
dB
dB

Interchannel Isolation

(1 kHz)

102

CS4360-BS/-BZ Dynamic Performance (Note 3)

Specified Temperature Range

-40

°C

Dynamic Range

(Note 2)

unweighted

A-Weighted

40 kHz Bandwidth

A-Weighted

TBD
TBD

102
100

-
-
-

TBD
TBD

94
97
97

-
-
-

dB
dB
dB

Total Harmonic Distortion + Noise

(Note 2)

0 dB

-20 dB
-60 dB

THD+N

-
-
-
-

-91
-79
-39

TBD

-
-

-
-
-

-91
-74
-34

TBD

-
-

dB
dB
dB

Interchannel Isolation

(1 kHz)

102

Parameter

Symbol

Min

Typ

Max

Unit

Combined Digital and On-chip Analog Filter Response - Single-Speed Mode (Note 4)

Passband

(Note 5)

to -0.05 dB corner

to -3 dB corner

0
0

-
-

.4535
.4998

Fs
Fs

Frequency Response 10 Hz to 20 kHz

-.02

+.035

StopBand

.5465

CS4360

DS517PP1

Notes: 4. Filter response is guaranteed by design.

5. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9 - 12) have

been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

6. For Single-Speed Mode, the Measurement Bandwidth is .5465 Fs to 3 Fs.

For Double-Speed Mode, the Measurement Bandwidth is .577 Fs to 1.4 Fs.

7. De-emphasis is available only in Single-Speed Mode.

8. Refer to Figure 16.

StopBand Attenuation

(Note 6)

Group Delay

tgd

9/Fs

Passband Group Delay Deviation

0 - 20 kHz

±0.36/Fs

De-emphasis Error (Relative to 1 kHz)

Fs = 32 kHz

Control Port Mode

Fs = 44.1 kHz

(Note 7)

Fs = 48 kHz
Fs = 32 kHz

Stand-Alone Mode

Fs = 44.1 kHz

Fs = 48 kHz

-
-
-
-
-
-

+.2/-.1

+.05/-.14

+0/-.22
+1.5/-0

+.05/-.14

+.2/-.4

dB
dB
dB
dB
dB
dB

Combined Digital and On-chip Analog Filter Response - Double-Speed Mode (Note 4)

Passband

(Note 5)

to -0.1 dB corner

to -3 dB corner

0
0

-
-

.4621
.4982

Fs
Fs

Frequency Response 10 Hz to 20 kHz

-0.1

StopBand

.577

StopBand Attenuation

(Note 6)

Group Delay

tgd

4/Fs

Passband Group Delay Deviation

0 - 20 kHz

±0.23/Fs

Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode (Note 4)

Passband

(Note 5)

to -3 dB corner

.25

Frequency Response 10 Hz to 20 kHz

-0.7

Group Delay

tgd

1.5/Fs

Parameters

Symbol

Min

Typ

Max

Units

Analog Output

Full Scale Output Voltage

0.60·V

0.66·V

0.72·V

Vpp

Quiescent Voltage

0.5·V

VDC

Quiescent Pin External Load

TBD

VDC

Interchannel Gain Mismatch

0.1

Gain Drift

100

ppm/°C

AC-Load Resistance

(Note 8)

Load Capacitance

100

Output Impedance

OUT

100

Parameter

Symbol

Min

Typ

Max

Unit

CS4360

DS517PP1

POWER AND THERMAL CHARACTERISTICS

Notes: 9. Current consumption is directly proportional to Fs. Typ and Max values are based on highest FS

10. I

measured with no external loading on pin 12 (SDA).

11. Power down mode is defined as RST = Low with all clock and data lines held static.

12. Valid with the recommended capacitor values on FILT+ and V

as shown in Figure 4.

DIGITAL CHARACTERISTICS

(For -KS & -KZ parts T

= -10 to +70°C; for -BS & -BZ parts T

= -40

to +85°C; VD = 2.0 V - 5.5 V, VLC = VLS = 1.8 V - 5.5 V)

Parameters

Symbol

Min

Typ

Max

Units

Power Supplies

Power Supply Current

normal operation, All Supplies = 5 V

(Note 9)

All Supplies = 3 V

Interface current (Note 10)

power-down state (all supplies) (Note 11)

-
-
-
-
-
-
-

22
25
21
14

0.002
0.002
0.016

-
-
-
-
-
-
-

mA
mA
mA
mA
mA
mA
mA

Power Dissipation

(Note 9)

All Supplies = 5 V

normal operation

power-down (Note 11)

All Supplies = 3 V

normal operation

power-down (Note 11)

-
-
-
-

235

0.080

105

0.048

TBD

mW
mW
mW
mW

Package Thermal Resistance

SOIC (-KS & -BS)

TSSOP (-KZ & -BZ)

-
-
-
-

TBD
TBD
TBD
TBD

-
-
-
-

°C/Watt
°C/Watt
°C/Watt
°C/Watt

Power Supply Rejection Ratio (1 kHz)

(Note 12)

(60 Hz)

PSRR
PSRR

-
-

60
40

-
-

dB
dB

Parameters

Symbol Min Typ

Max

Units

High-Level Input Voltage

Serial Audio Data Port

Control Port

70%
70%

-
-

VLS

VLC

Low-Level Input Voltage

Serial Audio Data Port

Control Port

-
-

20%
20%

VLS

VLC

Input Leakage Current

±10

Input Capacitance

Maximum MUTEC Drive Current

MUTEC High-Level Output Voltage

MUTEC Low-Level Output Voltage

CS4360

DS517PP1

SWITCHING CHARACTERISTICS- CONTROL PORT- TWO-WIRE FORMAT

(Note 16) (For -KS & -KZ parts T

= -10 to +70°C; for -BS & -BZ parts T

= -40 to +85°C; VLC = 1.7 V - 5.5 V;

Inputs: Logic 0 = GND, Logic 1 = VLC, C

= 30 pF)

Notes: 16. The Two-Wire Format is compatible with the I

C protocol.

17. Data must be held for sufficient time to bridge the transition time, t

, of SCL.

18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

19.

for Single-Speed Mode,

for Double-Speed Mode,

for Quad-Speed Mode.

Parameter

Symbol

Min

Max

Unit

SCL Clock Frequency

scl

100

kHz

RST Rising Edge to Start

irs

500

Bus Free Time Between Transmissions

buf

4.7

µs

Start Condition Hold Time (prior to first clock pulse)

hdst

4.0

µs

Clock Low time

low

4.7

µs

Clock High Time

high

4.0

µs

Setup Time for Repeated Start Condition

sust

4.7

µs

SDA Hold Time from SCL Falling

(Note 17)

hdd

µs

SDA Setup time to SCL Rising

sud

250

Rise Time of SCL and SDA

, t

µs

Fall Time SCL and SDA

, t

300

Setup Time for Stop Condition

susp

4.7

µs

Acknowledge Delay from SCL Falling

(Note 18)

ack

(Note 19)

256

---------------------

128

---------------------

------------------

buf

hdst

lo w

hdd

high

sud

Stop

Sta rt

S D A

S C L

irs

R S T

hdst

t sust

t susp

Sta rt

Stop

R e p e ate d

ack

Figure 2. Control Port Timing - Two-Wire Format

CS4360

DS517PP1

REGISTER QUICK REFERENCE

Addr

Function

Mode Control 1

AMUTE

DIF2

DIF1

DIF0

DEM1

DEM0

FM1

FM0

default

Invert Signal

Reserved

INV_B3

INV_A3

INV_B2

INV_A2

INV_B1

INV_A1

default

Mixing Control P1

Reserved

Reserved P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0

default

Mixing Control P2

Reserved

Reserved P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0

default

Mixing Control P3

Reserved

Reserved P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0

default

Volume Control A1

A1_MUTE A1_VOL6

A1_VOL5

A1_VOL4

A1_VOL3

A1_VOL2

A1_VOL1

A1_VOL0

default

Volume Control B1

B1_MUTE B1_VOL6

B1_VOL5

B1_VOL4

B1_VOL3

B1_VOL2

B1_VOL1

B1_VOL0

default

Volume Control A2

A2_MUTE A2_VOL6

A2_VOL5

A2_VOL4

A2_VOL3

A2_VOL2

A2_VOL1

A2_VOL0

default

Volume Control B2

B2_MUTE B2_VOL6

B2_VOL5

B2_VOL4

B2_VOL3

B2_VOL2

B2_VOL1

B2_VOL0

default

0Ah

Volume Control A3

A3_MUTE A3_VOL6

A3_VOL5

A3_VOL4

A3_VOL3

A3_VOL2

A3_VOL1

A3_VOL0

default

0Bh

Volume Control B3

B3_MUTE B3_VOL6

B3_VOL5

B3_VOL4

B3_VOL3

B3_VOL2

B3_VOL1

B3_VOL0

default

0Ch

Mode Control 2

SZC1

SZC0

CPEN

PDN

POPG

FREEZE

MCLKDIV SNGLVOL

default

0Dh

Revision Indicator

Reserved

REV3

REV2

REV1

REV0

default

CS4360

DS517PP1

REGISTER DESCRIPTIONS

Note: All registers are read/write in Two-Wire mode and write only in SPI, unless otherwise noted.

4.1

Mode Control 1 (address 01h)

4.1.1

AUTO-MUTE (AMUTE)

Default = 1

0 - Disabled
1 - Enabled

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio
samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and
muting is done independently for each channel. The quiescent voltage on the output will be retained
and the Mute Control pin will go active during the mute period. The muting function is affected, similar
to volume control changes, by the Soft and Zero Cross bits in the Power and Muting Control register.

4.1.2

DIGITAL INTERFACE FORMAT (DIF)

Default

= 000

- Format 0 (Left Justified, up to 24-bit data)

Function:

The required relationship between the Left/Right clock, serial clock and serial data is defined by the
Digital Interface Format and the options are detailed in Figures 17-22.

AMUTE

DIF2

DIF1

DIF0

DEM1

DEM0

FM1

FM0

DIF2

DIF1

DIF0

DESCRIPTION

Format

FIGURE

Left Justified, up to 24-bit data,

S, up to 24-bit data

Right Justified, 16-bit data

Right Justified, 24-bit data

Right Justified, 20-bit data

Right Justified, 18-bit data

Reserved

Table 1. Digital Interface Formats - Control Port Mode

CS4360

DS517PP1

4.3.1

ATAPI CHANNEL MIXING AND MUTING (ATAPI)

Default = 1001 - AOUTAx = L, AOUTBx = R (Stereo)

Function:

The CS4360 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to
Table 2 and Figure 24 for additional information.

Note:

All mixing functions occur prior to the digital volume control. Mixing only occurs in channel pairs.

4.4

Volume Control (addresses 06h - 0Bh)

4.4.1

MUTE (MUTE)

Default = 0

0 - Disabled
1 - Enabled

Function:

The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output
will be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero
Cross bits. The MUTEC pin will go active during the mute period if the Mute function is enabled for
both channels in the pair.

ATAPI3

ATAPI2

ATAPI1

ATAPI0

AOUTAx

AOUTBx

MUTE

[(L+R)/2]

MUTE

[(L+R)/2]

MUTE

[(L+R)/2]

MUTE

[(L+R)/2]

Table 2. ATAPI Decode

xx_MUTE

xx_VOL6

xx_VOL5

xx_VOL4

xx_VOL3

xx_VOL2

xx_VOL1

xx_VOL0

CS4360

DS517PP1

4.4.2

VOLUME CONTROL

(XX_VOL)

Default = 0

Function:

The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments
from 0 to -119 dB. Volume settings are decoded as shown in Table 3. The volume changes are im-
plemented as dictated by the Soft Ramp and Zero Cross bits. All volume settings less than -119 dB
are equivalent to enabling the MUTE bit.

4.5

Mode Control 2 (address 0Dh)

4.5.1

SOFT RAMP AND ZERO CROSS CONTROL (SZC)

Default = 10

00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp and Zero Cross

Function:

Immediate Change

When Immediate Change is selected all level changes will be implemented immediately in one step.

Zero Cross

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel.

Soft Ramp

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock
periods.

Soft Ramp and Zero Cross

Soft Ramp and Zero Cross dictates that signal level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and will be implemented on successive signal zero crossings. The 1/8
dB level changes will occur after timeout periods between 512 and 1024 sample periods (10.7 ms to
21.3 ms at 48 kHz sample rate) if the signal does not encounter zero crossings. The zero cross func-
tion is independently monitored and implemented for each channel.

Binary Code

Decimal Value

Volume Setting

0001010

0010100

-20

-20 dB

0101000

-40

-40 dB

0111100

-60

-60 dB

1011010

-90

-90 dB

Table 3. Example Digital Volume Settings

SZC1

SZC0

CPEN

PDN

POPG

FREEZE

MCLKDIV

SNGLVOL

CS4360

DS517PP1

4.5.2

CONTROL PORT ENABLE (CPEN)

Default = 0

0 - Disabled
1 - Enabled

Function:

The Control Port will become active and reset to the default settings when this function is enabled.

4.5.3

POWER DOWN (PDN)

Default = 1

0 - Disabled
1 - Enabled

Function:

The entire device will enter a low-power state when this function is enabled, and the contents of the
control registers are retained in this mode. The power-down bit defaults to `enabled' on power-up and
must be disabled before normal operation in Control Port mode can occur.

4.5.4

POPGUARD® TRANSIENT CONTROL (POPG)

Default = 1

0 - Disabled
1 - Enabled

Function:

The PopGuard

Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to

the quiescent voltage during power-on or power-off when this function is enabled. Please see section
6.4 for implementation details.

4.5.5

FREEZE CONTROLS (FREEZE)

Default = 0

0 - Disabled
1 - Enabled

Function:

This function allows modifications to be made to the registers without the changes taking effect until
the FREEZE is disabled. To make multiple changes in the control port registers take effect simulta-
neously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.

4.5.6

MASTER CLOCK DIVIDE ENABLE (MCLKDIV)

Default = 0

0 - Disabled
1 - Enabled

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all
other internal circuitry.

CS4360

DS517PP1

PIN DESCRIPTION

Pin Name

Pin Description

VLS

Serial Audio Interface Power (

Input) - Determines the required signal level for the serial audio inter-

face. Refer to the Recommended Operating Conditions for appropriate voltages. Applies to pins 2-7.

SDIN1
SDIN2
SDIN3

2
3
4

Serial Audio Data Input (

Input) - Input for two's complement serial audio data. SDIN1 corresponds to

AOUT1x, SDIN2 corresponds to AOUT2x and SDIN3 corresponds to AOUT3x.

SCLK

Serial Clock (

Input) - Serial clock for the serial audio interface.

LRCK

Left / Right Clock (

Input) - Determines which channel, Left or Right, is currently active on the serial

audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.

MCLK

Master Clock (

Input) - Clock source for the delta-sigma modulator and digital filters. Table 6 illustrates

several standard audio sample rates and the required master clock frequency.

Digital Power (

Input) - Positive power supply for the digital section. Refer to the Recommended Operat-

ing Conditions for appropriate voltages.

GND

Ground (

Input) - Ground reference. Should be connected to analog ground.

RST

Reset (

Input) - The device enters a low power mode and all internal registers are reset to their default

settings when low. The control port cannot be accessed when Reset is low.

VLC

Control Port Interface Power (

Input) - Determines the required signal level for the control port and pro-

vides power for bidirectional control port pins. Refer to the Recommended Operating Conditions for
appropriate voltages. Applies to pins 10-13 and 15.

FILT+

Positive Voltage Reference (

Output) - Positive reference voltage for the internal sampling circuits.

Requires the capacitive decoupling to GND as shown in the Typical Connection Diagram.

Serial Audio Power

VLS

MUTEC1 Mute Control 1

Serial Data Input 1

SDIN1

AOUTA1 Analog Output A1

Serial Data Input 2

SDIN2

AOUTB1 Analog Output B1

Serial Data Input 3

SDIN3

MUTEC2 Mute Control 2

Serial Clock

SCLK

AOUTA2 Analog Output A2

Left/Right Clock

LRCK

AOUTB2 Analog Output B2

Master Clock

MCLK

Analog Power

Digital Power

GND

Ground

GND

AOUTA3 Analog Output A3

Reset

RST

AOUTB3 Analog Output B3

DIF1 / SCL/ CCLK DIF1/SCL/CCLK

MUTEC3 Mute Control 3

DIF0 / SDA / CDIN

DIF0/SDA/CDIN

Quiescent Voltage

Mode1 / AD0 / CS

M1/AD0/CS

FILT+

Positive Voltage Reference

Control Port Power

VLC

Mode 2

1
2
3
4
5
6
7
8
9
10
11
12

1
2

24
23
22
21
20
19
18
17
16
15

CS4360

DS517PP1

Quiescent Voltage (

Output) - Filter connection for internal quiescent voltage. VQ must be capacitively

coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is
specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source
impedance and any current drawn from this pin will alter device performance. However, VQ can be used
to bias the analog circuitry assuming there is no AC signal component and the DC current is less than
the maximum specified in the Analog Characteristics and Specifications section.

Analog Power (

Input) - Positive power supply for the analog section. Refer to the Recommended Oper-

ating Conditions for appropriate voltages.

AOUTA1
AOUTB1
AOUTA2
AOUTB2
AOUTA3
AOUTB3

19
20
23
24
26
27

Analog Outputs (

Output) - The full scale analog line output level is specified in the Analog Characteris-

tics specifications table.

MUTEC1
MUTEC2
MUTEC3

18
25
28

Mute Control (

Output) - The Mute Control pin goes high during power-up initialization, reset, muting,

power-down or if the master clock to left/right clock frequency ratio is incorrect. This pin is intended to be
used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single
supply system. The use of an external mute circuit is not mandatory but may be desired for designs
requiring the absolute minimum in extraneous clicks and pops.

Control Port
Definitions

SCL/CCLK

Serial Control Port Clock (

Input) - Serial clock for the serial control port. Requires an external pull-up

resistor to the logic interface voltage in Two-Wire mode as shown in the Typical Connection Diagram.

SDA/CDIN

Serial Control Data (

Input/Output) - SDA is a data I/O line in Two-Wire format and requires an external

pull-up resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDIN is the
input data line for the control port interface in SPI format.

AD0/CS

Address Bit 0 (Two-Wire) / Control Port Chip Select (SPI) (

Input/Output) - AD0 is a chip address pin

Two-Wire format; CS is the chip select signal for SPI format.

Stand-Alone
Definitions

DIF1
DIF0

Digital Interface Format (

Input) - The required relationship between the Left/Right clock, serial clock

and serial data is defined by the Digital Interface Format selection. Refer to Table 4.

M1
M2

13
15

Mode Selection (

Input) - Determines the operational mode of the device as detailed in Table 5.

DIF1

DIF0

DESCRIPTION

Left Justified, up to 24-bit data

S, up to 24-bit data

Right Justified, 16-bit data

Right Justified, 24-bit data

Table 4. Digital Interface Formats - Stand Alone Mode

MODE

Single-Speed without de-emphasis (4 to 50 kHz sample rates)

Single-Speed with de-emphasis (32 to 48 kHz sample rates)

Double-Speed (50 to 100 kHz sample rates)

Quad-Speed (100 to 200 kHz sample rates)

Table 5. Mode Selection

CS4360

DS517PP1

6. APPLICATIONS

6.1

Grounding and Power Supply
Decoupling

As with any high resolution converter, the CS4360
requires careful attention to power supply and
grounding arrangements to optimize performance.
Figure 4 shows the recommended power arrange-
ment with VA, VD, VLS and VLC connected to
clean supplies. Decoupling capacitors should be lo-
cated as close to the device package as possible. If
desired, all supply pins may be connected to the
same supply, but a decoupling capacitor should still
be placed on each supply pin.

6.2

Oversampling Modes

The CS4360 operates in one of three oversampling
modes based on the input sample rate. Mode selec-
tion is determined by the FM pins in Stand-Alone
mode or the FM bits in Control Port mode. Single-
Speed mode supports input sample rates up to 50
kHz and uses a 128x oversampling ratio. Double-
Speed mode supports input sample rates up to 100
kHz and uses an oversampling ratio of 64x. Quad-
Speed mode supports input sample rates up to 200
kHz and uses an oversampling ratio of 32x.

6.3

Recommended Power-up Sequence

1. Hold RST low until the power supply, master,
and left/right clocks are stable. In this state, the
control port is reset to its default settings and VQ
will remain low.

2. Bring RST high. The device will remain in a low
power state with VQ low and will initiate the
Stand-Alone power-up sequence. The control port
will be accessible at this time. If Control Port oper-
ation is desired, write the CPEN bit prior to the
completion of the Stand-Alone power-up se-
quence, approximately 512 LRCK cycles in Sin-
gle-Speed Mode (1024 LRCK cycles in Double-
Speed Mode, and 2048 LRCK cycles in Quad-
Speed Mode). Writing this bit will halt the Stand-

Alone power-up sequence and initialize the control
port to its default settings. The desired register set-
tings can be loaded while keeping the PDN bit set
to 1.

3. If Control Port Mode is selected via the CPEN
bit, set the PDN bit to 0 which will initiate the pow-
er-up sequence, which requires approximately
50 µS when the POPG bit is set to 0. If the POPG
bit is set to 1, see Section 6.4 for total power-up
timing.

6.4

Popguard

Transient Control

The CS4360 uses a novel technique to minimize
the effects of output transients during power-up
and power-down. This technique, when used with
external DC-blocking capacitors in series with the
audio outputs, minimizes the audio transients com-
monly produced by single-ended single-supply
converters.

When the device is initially powered-up, the audio
outputs, AOUTAx and AOUTBx, are clamped to
GND. Following a delay of approximately 1000
sample periods, each output begins to ramp toward
the quiescent voltage. Approximately 10,000
left/right clock cycles later, the outputs reach VQ
and audio output begins. This gradual voltage
ramping allows time for the external DC-blocking
capacitor to charge to the quiescent voltage, mini-
mizing the power-up transient.

To prevent transients at power-down, the device
must first enter its power-down state. When this oc-
curs, audio output ceases and the internal output
buffers are disconnected from AOUTAx and
AOUTBx. In their place, a soft-start current sink is
substituted which allows the DC-blocking capaci-
tors to slowly discharge. Once this charge is dissi-
pated, the power to the device may be turned off
and the system is ready for the next power-on.

To prevent an audio transient at the next power-on,
it is necessary to ensure that the DC-blocking ca-
pacitors have fully discharged before turning off

CS4360

DS517PP1

the power or exiting the power-down state. If not, a
transient will occur when the audio outputs are ini-
tially clamped to GND. The time that the device
must remain in the power-down state is related to
the value of the DC-blocking capacitance. For ex-
ample, with a 3.3 µF capacitor, the minimum pow-
er-down time will be approximately 0.4 seconds.

Use of the Mute Control function is recommended
for designs requiring the absolute minimum in ex-
traneous clicks and pops. Also, use of the Mute
Control function can enable the system designer to
achieve idle channel noise/signal-to-noise ratios
which are only limited by the external mute circuit.
See the CDB4360 data sheet for a suggested mute
circuit.

7. CONTROL PORT INTERFACE

The control port is used to load all the internal set-
tings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference prob-
lems, the control port pins should remain static if
no operation is required.

The CS4360 has MAP auto increment capability,
enabled by the INCR bit in the MAP register,
which is the MSB. If INCR is 0, then the MAP will
stay constant for successive writes. If INCR is set
to 1, then MAP will auto increment after each byte
is written, allowing block reads or writes of succes-
sive registers.

7.1

Enabling the Control Port

On the CS4360 the control port pins are shared
with stand-alone configuration pins. To enable the
control port, the user must set the CPEN bit. This
is done by performing a Two-Wire or SPI write.
Once the control port is enabled, these pins are ded-
icated to control port functionality.

To prevent audible artifacts the CPEN bit (see Sec-
tion 4.5.2) should be set prior to the completion of
the Stand-Alone power-up sequence, approximate-
ly 512 LRCK cycles in Single-Speed Mode (1024

LRCK cycles in Double-Speed Mode, and 2048
LRCK cycles in Quad-Speed Mode). Writing this
bit will halt the Stand-Alone power-up sequence
and initialize the control port to its default settings.
Note, the CPEN bit can be set any time after RST
goes high; however, setting this bit after the Stand-
Alone power-up sequence has completed can cause
audible artifacts.

7.2

Format Selection

The control port has 2 formats: SPI and Two-Wire,
with the CS4360 operating as a slave device.

If Two-Wire operation is desired, AD0/CS should
be tied to VLS or GND. If the CS4360 ever detects
a high to low transition on AD0/CS after power-up
and after the control port is activated, SPI format
will be selected.

7.3

Two-Wire Format

In Two-Wire Format, SDA is a bidirectional data
line. Data is clocked into and out of the part by the
clock, SCL, with a clock to data relationship as
shown in Figure 5. The receiving device should
send an acknowledge (ACK) after each byte re-
ceived. There is no CS pin. Pin AD0 form the par-
tial chip address and should be tied to VLS or GND
as required. The upper 6 bits of the 7 bit address
field must be 001000.

Note, MCLK is required during all two-wire trans-
actions. The Two-Wire format is compatible with
the I

C protocol. Please see reference 2 for further

details.

7.3.1

Writing in Two-Wire Format

To communicate with the CS4360, initiate a
START condition of the bus. Next, send the chip
address. The eighth bit of the address byte is the
R/W bit (low for a write). The next byte is the
Memory Address Pointer, MAP, which selects the
register to be read or written. The MAP is then fol-
lowed by the data to be written. To write multiple
registers, continue providing a clock and data,

CS4360

DS517PP1

waiting for the CS4360 to acknowledge between
each byte. To end the transaction, send a STOP
condition.

7.3.2

Reading in Two-Wire Format

To communicate with the CS4360, initiate a
START condition of the bus. Next, send the chip
address. The eighth bit of the address byte is the
R/W bit (high for a read). The contents of the reg-
ister pointed to by the MAP will be output after the
chip address. To read multiple registers, continue
providing a clock and issue an ACK after each
byte. To end the transaction, send a STOP condi-
tion.

7.4

SPI Format

In SPI format, CS is the CS4360 chip select signal,
CCLK is the control port bit clock, CDIN is the in-
put data line from the microcontroller and the chip
address is 0010000. CS, CCLK and CDIN are all

inputs and data is clocked in on the rising edge of
CCLK.

Note that the CS4360 is write-only when in SPI
format.

7.4.1

Writing in SPI

Figure 6 shows the operation of the control port in
SPI format. To write to a register, bring CS low.
The first 7 bits on CDIN form the chip address and
must be 0010000. The eighth bit is a read/write in-
dicator (R/W), which must be low to write. The
next 8 bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next 8 bits are the data
which will be placed into register designated by the
MAP. To write multiple registers, keep CS low and
continue providing clocks on CCLK. End the read
transaction by setting CS high.

SDA

SCL

001000

ADDR
AD0

R/W

Start

ACK

DATA
1-8

ACK

DATA
1-8

ACK

Stop

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.

Note 1

Figure 5. Control Port Timing, Two-Wire Format

MAP

MSB

LSB

DATA

byte 1

byte n

R/W

MAP = Memory Address Pointer

ADDRESS

CHIP

CDIN

CCLK

0010000

Figure 6. Control Port Timing, SPI Format

CS4360

DS517PP1

PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
affect the measurement. This measurement technique has been accepted by the Audio Engineering So-
ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full scale analog output for a full scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

REFERENCES

1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris.
Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.

2) CDB4360 Evaluation Board Datasheet

3) "The I

C Bus Specification: Version 2.0" Philips Semiconductors, December 1998.

http://www.semiconductors.philips.com

CS4360

DS517PP1

Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.

2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not
reduce dimension "b" by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

INCHES

MILLIMETERS

NOTE

DIM

MIN

NOM

MAX

MIN

NOM

MAX

0.47

1.20

0.002

0.004

0.006

0.05

0.10

0.15

0.03150

0.035

0.04

0.80

0.90

1.00

0.00748

0.0096

0.012

0.19

0.245

0.30

2,3

0.378 BSC

0.382 BSC

0.386 BSC

9.60 BSC

9.70 BSC

9.80 BSC

0.248

0.2519

0.256

6.30

6.40

6.50

0.169

0.1732

0.177

4.30

4.40

4.50

0.026 BSC

0.65 BSC

0.020

0.024

0.029

0.50

0.60

0.75

0°

4°

8°

0°

4°

8°

JEDEC #: MO-153

Controlling Dimension is Millimeters.

28L TSSOP (4.4 mm BODY) PACKAGE DRAWING

1 2 3

SEATING

PLANE

SIDE VIEW

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