Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 2002
(All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CS4362
114 dB, 192 kHz 6-Channel D/A Converter
Features
24-Bit Conversion
Up to 192 kHz Sample Rates
114 dB Dynamic Range
-100 dB THD+N
Supports PCM or DSD Data Formats
Selectable Digital Filters
Volume Control with Soft Ramp
1 dB Step Size
Zero Crossing Click-Free Transitions
Dedicated DSD inputs
Low Clock Jitter Sensitivity
Simultaneous Support for Two Synchronous
Sample Rates for DVD Audio
C or Stand-Alone Operation
Description
The CS4362 is a complete 6-channel digital-to-analog
system including digital interpolation, fifth-order delta-
sigma digital-to-analog conversion, digital de-emphasis,
volume control and analog filtering. The advantages of
this architecture include: ideal differential linearity, no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and temperature and a high
tolerance to clock jitter.
The CS4362 accepts PCM data at sample rates from
4 kHz to 192 kHz, DSD audio data, and operates over a
wide power supply range. These features are ideal for
multi-channel audio systems including DVD players.
SACD players, A/V receivers, digital TV's and VCR's,
mixing consoles, effects processors and set-top box
systems.
ORDERING INFORMATION
CS4362-KQ
-10 to 70
48-pin LQFP
CS4362-BQ
-40 to 85
48-pin LQFP
CDB4362
Evaluation Board
I
E x t e r n a l
M u t e C o n t r o l
R S T
V o l u m e C o n t r o l
I n t e r p o la t i o n F i lt e r
A n a lo g F i lt e r
D A C
M i x e r
V o l u m e C o n t r o l
D A C
A n a lo g F i lt e r
I n t e r p o l a t i o n F i lt e r
V o l u m e C o n t r o l
I n t e r p o la t i o n F i lt e r
A n a lo g F i lt e r
D A C
M i x e r
V o l u m e C o n t r o l
D A C
A n a lo g F i lt e r
I n t e r p o l a t i o n F i lt e r
V o l u m e C o n t r o l
I n t e r p o la t i o n F i lt e r
A n a lo g F i lt e r
D A C
M i x e r
V o l u m e C o n t r o l
D A C
A n a lo g F i lt e r
A O U T B 3-
I n t e r p o l a t i o n F i lt e r
M C L K
S
e
ri
a
l
P
o
rt
M 1/S CL/CCLK
M 2/SDA/CDIN
M 0/A D0/CS
V LC
2
VQ
FILT+
VA
G ND
V D
M UTEC[1:6]
M 3/DS D_S CLK
G ND
Control Port/M ode S elect
6
VLS
L R C K
S D I N 1
S D I N 2
S D I N 3
2
S C L K
L R C K 2
S C L K
DS Dxx
6
A O U T B3+
A O U T A 3-
A O U T A3+
A O U T B 2-
A O U T B2+
A O U T A 2-
A O U T A2+
A O U T B 1-
A O U T B1+
A O U T A 1-
A O U T A1+
1
1
MAR `02
DS257PP2
CS4362
2
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
2. REGISTER QUICK REFERENCE .......................................................................................... 14
3. REGISTER DESCRIPTION .................................................................................................... 15
4. PIN DESCRIPTION ................................................................................................................. 24
5. APPLICATIONS ...................................................................................................................... 27
5.1 Grounding and Power Supply Decoupling ....................................................................... 27
5.2 Oversampling Modes ....................................................................................................... 27
5.3 Recommended Power-up Sequence ............................................................................... 27
5.4 Analog Output and Filtering ............................................................................................. 27
5.5 Interpolation Filter ............................................................................................................ 27
5.6 Clock Source Selection .................................................................................................... 28
5.7 Using DSD mode ............................................................................................................. 28
6. CONTROL PORT INTERFACE .............................................................................................. 28
6.1 Enabling the Control Port ................................................................................................. 28
6.2 Format Selection .............................................................................................................. 28
6.3 I
2
C Format ....................................................................................................................... 29
6.3.1 Writing in I
2
C Format ........................................................................................... 29
6.3.2 Reading in I
2
C Format ........................................................................................ 29
6.4 SPI Format ....................................................................................................................... 29
6.4.1 Writing in SPI ...................................................................................................... 29
6.5 Memory Address Pointer (MAP) ...................................................................................... 30
7. PARAMETER DEFINITIONS.................................................................................................. 38
8. REFERENCES ........................................................................................................................ 38
9. PACKAGE DIMENSIONS ....................................................................................................... 39
LIST OF FIGURES
Figure 1. Serial Mode Input Timing ................................................................................................. 8
Figure 2. Direct Stream Digital - Serial Audio Input Timing ............................................................. 9
Figure 3. Control Port Timing - I
2
C Format ................................................................................... 10
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product informa-
tion describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any
kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied
on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining
to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as
the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing
this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property
rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization
with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising
or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material
and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained
from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law
and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE
SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH
APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Purchase of I
2
C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I
2
C Patent Rights to use
those components in a standard I
2
C system.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
CS4362
3
Figure 4. Control Port Timing - SPI Format................................................................................... 11
Figure 5. Typical Connection Diagram Control Port...................................................................... 12
Figure 6. Typical Connection Diagram Stand-Alone ..................................................................... 13
Figure 7. Control Port Timing, I
2
C Format .................................................................................... 30
Figure 8. Control Port Timing, SPI Format.................................................................................... 30
Figure 9. Single Speed (fast) Stopband Rejection ........................................................................ 31
Figure 10. Single Speed (fast) Transition Band ............................................................................ 31
Figure 11. Single Speed (fast) Transition Band (detail) ................................................................ 31
Figure 12. Single Speed (fast) Passband Ripple .......................................................................... 31
Figure 13. Single Speed (slow) Stopband Rejection..................................................................... 31
Figure 14. Single Speed (slow) Transition Band........................................................................... 31
Figure 15. Single Speed (slow) Transition Band (detail)............................................................... 32
Figure 16. Single Speed (slow) Passband Ripple......................................................................... 32
Figure 17. Double Speed (fast) Stopband Rejection..................................................................... 32
Figure 18. Double Speed (fast) Transition Band........................................................................... 32
Figure 19. Double Speed (fast) Transition Band (detail)............................................................... 32
Figure 20. Double Speed (fast) Passband Ripple......................................................................... 32
Figure 21. Double Speed (slow) Stopband Rejection ................................................................... 33
Figure 22. Double Speed (slow) Transition Band ......................................................................... 33
Figure 23. Double Speed (slow) Transition Band (detail) ............................................................. 33
Figure 24. Double Speed (slow) Passband Ripple ....................................................................... 33
Figure 25. Quad Speed (fast) Stopband Rejection ....................................................................... 33
Figure 26. Quad Speed (fast) Transition Band ............................................................................. 33
Figure 27. Quad Speed (fast) Transition Band (detail) ................................................................. 34
Figure 28. Quad Speed (fast) Passband Ripple ........................................................................... 34
Figure 29. Quad Speed (slow) Stopband Rejection...................................................................... 34
Figure 30. Quad Speed (slow) Transition Band ............................................................................ 34
Figure 31. Quad Speed (slow) Transition Band (detail) ................................................................ 34
Figure 32. Quad Speed (slow) Passband Ripple .......................................................................... 34
Figure 33. Format 0 - Left Justified up to 24-bit Data.................................................................... 35
Figure 34. Format 1 - I
2
S up to 24-bit Data................................................................................... 35
Figure 35. Format 2 - Right Justified 16-bit Data .......................................................................... 35
Figure 36. Format 3 - Right Justified 24-bit Data .......................................................................... 35
Figure 37. Format 4 - Right Justified 20-bit Data .......................................................................... 36
Figure 38. Format 5 - Right Justified 18-bit Data .......................................................................... 36
Figure 39. De-Emphasis Curve..................................................................................................... 36
Figure 40. Channel Pair Routing Diagram (x = Channel Pair 1, 2, or 3) ....................................... 36
Figure 41. ATAPI Block Diagram (x = channel pair 1, 2, or 3) ...................................................... 37
Figure 42. Recommended Output Filter........................................................................................ 37
LIST OF TABLES
Table 1. Digital Interface Formats - PCM Mode............................................................................ 16
Table 2. Digital Interface Formats - DSD Mode ............................................................................ 16
Table 3. ATAPI Decode ................................................................................................................ 21
Table 4. Example Digital Volume Settings .................................................................................... 22
Table 5. Common Clock Frequencies........................................................................................... 26
Table 6. Digital Interface Format, Stand-Alone Mode Options...................................................... 26
Table 7. Mode Selection, Stand-Alone Mode Options .................................................................. 26
Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options ............................................... 26
CS4362
4
1.
CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS
(Full-Scale Output Sine Wave, 997 Hz; Measurement Bandwidth
10 Hz to 20 kHz, unless otherwise specified; Test load R
L
= 3 k
, C
L
= 100 pF
,
VA = 5 V, VD = 3.3V (see Figure 5)
For Single speed Mode Fs = 48 kHz, SCLK = 3.072 MHz, MCLK = 12.288 MHz;
For Double Speed Mode Fs = 96 kHz, SCLK = 6.144 MHz, MCLK = 12.288 MHz;
For Quad Speed Mode Fs = 192 kHz, SCLK = 12.288 MHz, MCLK = 24.576 MHz;
For Direct Stream Digital Mode Fs = 128 x 48 kHz, DSD_SCLK = 6.144 MHz, MCLK = 12.288 MHz).
Notes: 1. CS4362-KQ parts are tested at 25 C.
2. One-half LSB of triangular PDF dither is added to data.
3. Performance limited by 16-bit quantization noise.
4. CS4362-BQ parts are tested at the extremes of the specified temperature range and Min/Max
performance numbers are guaranteed across the specified temperature range, T
A
. Typical numbers are
taken at 25 C.
Parameters
Symbol
Min
Typ
Max
Unit
CS4362-KQ Dynamic Performance - All PCM modes and DSD (Note 1)
Specified Temperature Range
T
A
-10
-
70
C
Dynamic Range (Note 2)
24-bit
unweighted
A-Weighted
16-bit
unweighted
(Note 3) A-Weighted
105
108
-
-
111
114
94
97
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 2)
24-bit
0 dB
-20 dB
-60 dB
16-bit
0 dB
(Note 3)
-20 dB
-60 dB
THD+N
-
-
-
-
-
-
-100
-91
-51
-94
-74
-34
-94
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Idle Channel Noise / Signal-to-noise ratio
-
114
-
dB
Interchannel Isolation
(1 kHz)
-
90
-
dB
CS4362-BQ Dynamic Performance - All PCM modes and DSD (Note 4)
Specified Temperature Range
T
A
-40
-
85
C
Dynamic Range (Note 2)
24-bit
unweighted
A-Weighted
16-bit
unweighted
(Note 3) A-Weighted
102
105
-
-
111
114
94
97
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 2)
24-bit
0 dB
-20 dB
-60 dB
16-bit
0 dB
(Note 3)
-20 dB
-60 dB
THD+N
-
-
-
-
-
-
-100
-91
-51
-94
-74
-34
-91
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Idle Channel Noise / Signal-to-noise ratio
-
114
-
dB
Interchannel Isolation
(1 kHz)
-
90
-
dB
CS4362
5
ANALOG CHARACTERISTICS
(Continued)
POWER AND THERMAL CHARACTERISTICS
Notes: 5. V
FS
is tested under load R
L
and includes attenuation due to Z
OUT
6. Current consumption increases with increasing FS within a given speed mode and is signal dependant.
Max values are based on highest FS and highest MCLK.
7. I
LC
measured with no external loading on the SDA pin.
8. This specification is violated when the VLC supply is greater than VD and when pin 16 (M1/SDA) is tied
or pulled low. Logic tied to pin 16 needs to be able to sink this current.
9. Power down mode is defined as RST pin = Low with all clock and data lines held static.
10. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6.
Parameters
Symbol
Min
Typ
Max
Units
Analog Output - All PCM modes and DSD
Full Scale Differential Output Voltage (Note 5)
V
FS
88% V
A
92% V
A
94% V
A
Vpp
Quiescent Voltage
V
Q
-
50% V
A
-
VDC
Max Current from V
Q
I
QMAX
-
1
-
A
Interchannel Gain Mismatch
-
0.1
-
dB
Gain Drift
-
100
-
ppm/C
Output Impedance
(Note 5)
Z
OUT
-
100
-
AC-Load Resistance
R
L
3
-
-
k
Load Capacitance
C
L
-
-
100
pF
Parameters
Symbol
Min
Typ
Max
Units
Power Supplies
Power Supply Current
normal operation, V
A
= 5V
(Note 6)
V
D
= 5V
V
D
= 3.3V
Interface current, VLC=5V (Note 7, 8)
VLS=5V
power-down state (all supplies) (Note 9)
I
A
I
D
I
D
I
LC
I
LS
I
pd
-
-
-
-
-
-
50
38
25
2
84
200
55
60
40
-
-
-
mA
mA
mA
A
A
A
Power Dissipation
(Note 6)
VA = 5 V, VD = 3.3 V
normal operation
power-down (Note 9)
VA = 5 V, VD = 5 V
normal operation
power-down (Note 9)
-
-
-
-
335
1
440
1
410
-
575
-
mW
mW
mW
mW
Package Thermal Resistance
JA
JC
-
-
48
15
-
-
C/Watt
C/Watt
Power Supply Rejection Ratio (Note 10)
(1 kHz)
(60 Hz)
PSRR
-
-
60
40
-
-
dB
dB
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