Document Outline
- CS4391A
- Features
- Description
- 1. Characteristics/Specifications
- 2. Typical Connection Diagrams
- 3. Register Quick Reference
- 4. Register Description
- 5. Pin Description - PCM Data mode
- 6. Pin Description - DSD mode
- Table 1. Digital Interface Formats - PCM Modes
- Table 2. Digital Interface Formats - DSD Mode
- Table 3. De-Emphasis Mode Selection
- Table 4. Functional Mode Selection
- Table 5. Soft Cross or Zero Cross Mode Selection
- Table 6. ATAPI Decode
- Table 7. Digital Volume Control
- Table 8. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies
- Table 9. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies
- Table 10. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies
- Table 11. Single Speed (4 to 50 kHz) Digital Interface Format, Stand-Alone Mode Options
- Table 12. Single Speed Only (4 to 50 kHz) De-Emphasis, Stand-Alone Mode Options
- Table 13. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options
- Table 14. Quad Speed (100 to 200 kHz) Digital Interface Format, Stand-Alone Mode Options
- Table 15. Direct Stream Digital (DSD), Stand-Alone Mode Options
- Figure 7. Format 0, Left Justified up to 24-Bit Data
- Figure 8. Format 1, I2S up to 24-Bit Data
- Figure 9. Format 2, Right Justified 16-Bit Data
- Figure 10. Format 3, Right Justified 24-Bit Data
- Figure 11. Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only)
- Figure 12. Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)
- Figure 13. De-Emphasis Curve
- Figure 14. ATAPI Block Diagram
- 7. Applications
- 8. Control Port Interface
- 9. Parameter Definitions
- 10. References
- 11. Package Dimensions
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 2004
(All Rights Reserved)
www.cirrus.com
CS4391A
24-Bit, 192 kHz Stereo DAC with Volume Control
Features
Complete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
108 dB Dynamic Range
94 dB THD+N
Direct Stream Digital Mode
Low Clock Jitter Sensitivity
+5 V Power Supply
ATAPI Mixing
On-Chip Digital De-emphasis for 32, 44.1,
and 48 kHz
Volume Control with Soft Ramp
119 dB Attenuation
1 dB Step Size
Zero Crossing Click-Free Transitions
Direct Interface with 5 V to 1.8 V Logic
Description
The CS4391A is a complete stereo digital-to-analog sys-
tem including digital interpolation, fourth-order delta-
sigma digital-to-analog conversion, digital de-emphasis,
volume control, channel mixing and analog filtering. The
advantages of this architecture include: ideal differential
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and tempera-
ture and a high tolerance to clock jitter.
The CS4391A accepts PCM data at sample rates from
4 kHz to 192 kHz, DSD audio data, consumes very little
power and operates over a wide power supply range.
These features are ideal for DVD, A/V receivers, CD and
set-top box systems.
ORDERING INFORMATION
CS4391A-KS 20-pin SOIC
-10 to 70 C
CS4391A-KZ 20-pin TSSOP
-10 to 70 C
CS4391A-KZZ 20-pin TSSOP, Lead Free -10 to 70 C
CDB4391A
Evaluation Board
I
LRCK
SDATA
(SDA/CDIN)
MCLK
AMUTEC
AOUTA-
AOUTB-
SERIAL
PORT
INTERPOLATION
INTERPOLATOR
(CONTROL PORT)
DAC
DAC
EXTERNAL
ANALOG
FILTER
ANALOG
FILTER
MUTE CONTROL
FILTER
FILTER
RST
SCLK
VOLUME
CONTROL
VOLUME
CONTROL
MIXER
(SCL/CCLK)
(AD0/CS)
AOUTA+
AOUTB+
CMOUT
REFERENCE
FILT+
BMUTEC
M1
M3
M2
MODE SELECT
M0
JUL `04
DS600PP3
CS4391A
2
DS600PP3
TABLE OF CONTENTS
1. CHARACTERISTICS/SPECIFICATIONS ................................................................................. 5
2. TYPICAL CONNECTION DIAGRAMS ................................................................................... 13
3. REGISTER QUICK REFERENCE .......................................................................................... 15
3.1 Mode Control 1 (address 01h) .......................................................................................... 15
3.2 Volume and Mixing Control (address 02h)........................................................................ 16
3.3 Channel A Volume Control (address 03h) ........................................................................ 16
3.4 Channel B Volume Control (address 04h) ........................................................................ 16
3.5 Mode Control 2 (address 05h) .......................................................................................... 17
4. REGISTER DESCRIPTION .................................................................................................... 18
4.1 Mode Control 1 - Address 01h .......................................................................................... 18
4.1.1 Auto-Mute (Bit 7) ................................................................................................. 18
4.1.2 Digital Interface Formats (Bits 6:4) ...................................................................... 18
4.1.3 De-Emphasis Control (Bits 3:2) ........................................................................... 18
4.1.4 Functional Mode (Bits 1:0) .................................................................................. 18
4.2 Volume and Mixing Control (Address 02h) ....................................................................... 19
4.2.1 Channel A Volume = Channel B Volume (Bit 7) ................................................. 19
4.2.2 Soft Ramp or Zero Cross Enable (Bits 6:5) ......................................................... 19
4.2.3 ATAPI Channel Mixing and Muting (Bits 4:0) ...................................................... 19
4.3 Channel A Volume Control - Address 03h ........................................................................ 19
4.4 Channel B Volume Control - Address 04h ....................................................................... 20
4.4.1 Mute (Bit 7) .......................................................................................................... 20
4.4.2 Volume Control (Bits 6:0) .................................................................................... 20
4.5 Mode Control 2 - Address 05h .......................................................................................... 20
4.5.1 Invert Signal Polarity (Bits 7:6) ............................................................................ 20
4.5.2 Control Port Enable (Bit 5) .................................................................................. 20
4.5.3 Power Down (Bit 4) ............................................................................................. 20
4.5.4 AMUTEC = BMUTEC (Bit 3) ............................................................................... 20
4.5.5 Freeze (Bit 2) ...................................................................................................... 21
4.5.6 Master Clock Divide (Bit 1) .................................................................................. 21
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to
http://www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product infor-
mation describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the infor-
mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this
information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus
and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the
information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying
such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this ma-
terial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANT-
ED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Purchase of I
2
C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I
2
C Patent Rights to use
those components in a standard I
2
C system.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-
marks or service marks of their respective owners.
CS4391A
DS600PP3
3
5. PIN DESCRIPTION - PCM DATA MODE ............................................................................... 22
6. PIN DESCRIPTION - DSD MODE .......................................................................................... 26
7. APPLICATIONS ..................................................................................................................... 33
7.1 Recommended Power-up Sequence for Hardware Mode ............................................... 33
7.2 Recommended Power-up Sequence and Access to Control Port Mode ......................... 33
7.3 Analog Output and Filtering ............................................................................................. 33
8. CONTROL PORT INTERFACE .............................................................................................. 34
8.1 SPI Mode ......................................................................................................................... 34
8.2 I2C Mode ......................................................................................................................... 34
9. PARAMETER DEFINITIONS .................................................................................................. 38
10. REFERENCES ...................................................................................................................... 38
11. PACKAGE DIMENSIONS ................................................................................................. 39
LIST OF TABLES
Table 1. Digital Interface Formats - PCM Modes ................................................................................ 27
Table 2. Digital Interface Formats - DSD Mode................................................................................... 27
Table 3. De-Emphasis Mode Selection .............................................................................................. 27
Table 4. Functional Mode Selection .................................................................................................... 27
Table 5. Soft Cross or Zero Cross Mode Selection ............................................................................ 27
Table 6. ATAPI Decode ....................................................................................................................... 28
Table 7. Digital Volume Control ........................................................................................................... 28
Table 8. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies................................ 29
Table 9. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies ......................... 29
Table 10. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies ........................ 29
Table 11. Single Speed (4 to 50 kHz) Digital Interface Format, Stand-Alone Mode Options .............. 29
Table 12. Single Speed Only (4 to 50 kHz) De-Emphasis, Stand-Alone Mode Options ..................... 29
Table 13. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options......... 29
Table 14. Quad Speed (100 to 200 kHz) Digital Interface Format, Stand-Alone Mode Options ......... 30
Table 15. Direct Stream Digital (DSD), Stand-Alone Mode Options ................................................... 30
Table 16. Memory Address Pointer (MAP) .......................................................................................... 35
CS4391A
4
DS600PP3
LIST OF FIGURES
Figure 1. Serial Mode Input Timing ................................................................................................. 9
Figure 2. Direct Stream Digital - Serial Audio Input Timing ........................................................... 10
Figure 3. I
2
C Control Port Timing .................................................................................................. 11
Figure 4. SPI Control Port Timing ................................................................................................. 12
Figure 5. Typical Connection Diagram - PCM Mode ..................................................................... 13
Figure 6. Typical Connection Diagram - DSD Mode ..................................................................... 14
Figure 7. Format 0, Left Justified up to 24-Bit Data....................................................................... 31
Figure 8. Format 1, I2S up to 24-Bit Data ..................................................................................... 31
Figure 9. Format 2, Right Justified 16-Bit Data ............................................................................. 31
Figure 10. Format 3, Right Justified 24-Bit Data ........................................................................... 31
Figure 11. Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only).............. 32
Figure 12. Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)............... 32
Figure 13. De-Emphasis Curve ..................................................................................................... 32
Figure 14. ATAPI Block Diagram .................................................................................................. 32
Figure 15. CS4391A Output Filter ................................................................................................. 33
Figure 16. Control Port Timing, SPI mode .................................................................................... 35
Figure 17. Control Port Timing, I
2
C Mode ..................................................................................... 35
Figure 18. Single-Speed Frequency Response ............................................................................ 36
Figure 19. Single-Speed Transition Band ..................................................................................... 36
Figure 20. Single-Speed Transition Band ..................................................................................... 36
Figure 21. Single-Speed Stopband Rejection ............................................................................... 36
Figure 22. Double-Speed Frequency Response ........................................................................... 36
Figure 23. Double-Speed Transition Band .................................................................................... 36
Figure 24. Double-Speed Transition Band .................................................................................... 37
Figure 25. Double-Speed Stopband Rejection .............................................................................. 37
CS4391A
DS600PP3
5
1.
CHARACTERISTICS/SPECIFICATIONS
(Min/Max performance characteristics and specifications are guaranteed over the
Specified Operating Conditions
.
Typical performance characteristics are derived from measurements taken at T
A
= 25
C, VA = 5.0 V)
SPECIFIED OPERATING CONDITIONS
(AGND = 0V; all voltages with respect to ground.)
ABSOLUTE MAXIMUM RATINGS
(AGND = 0 V; all voltages with respect to ground.)
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
Parameters
Symbol Min
Typ
Max
Units
DC Power Supply
VA
VL
4.75
1.8
5.0
-
5.25
VA
V
V
Specified Temperature Range
-KS & -KZ
T
A
-10
-
70
C
Parameters
Symbol
Min
Max
Units
DC Power Supply
VA
VL
-0.3
-0.3
6.0
VA
V
V
Input Current, Any Pin Except Supplies
I
in
-
10
mA
Digital Input Voltage
V
IND
-0.3
VL+0.4
V
Ambient Operating Temperature (power applied)
T
A
-55
125
C
Storage Temperature
T
stg
-65
150
C
CS4391A
6
DS600PP3
ANALOG CHARACTERISTICS
(Test conditions (unless otherwise specified): Input test signal is a
997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; Test load R
L
= 5 k
, C
L
= 10 pF)
Parameter
VA = 5 V
Symbol
Min
Typ
Max
Unit
Dynamic Performance
Dynamic Range
(Note 1)
unweighted
A-Weighted
40 kHz Bandwidth
A-Weighted
100
103
-
105
108
102
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 1,2)
0 dB
-20 dB
-60 dB
THD+N
-
-
-
-94
-85
-45
-89
-
-40
dB
dB
dB
Idle Channel Noise / Signal-to-Noise Ratio
-
108
-
dB
Interchannel Isolation
(1 kHz)
-
100
-
dB
Power Supplies
Power Supply Current
normal operation
power-down state
I
A
+ I
L
I
A
+ I
L
-
-
17
60
35
-
mA
A
Power Dissipation
normal operation
power-down
-
-
85
0.3
175
-
mW
mW
Power Supply Rejection Ratio (1 kHz)
(Note 3)
(60 Hz)
PSRR
-
-
60
40
-
-
dB
dB
Parameter
Symbol
Min
Typ
Max
Units
Analog Output
Full Scale Differential Output Voltage
1.05VA
1.1VA
1.15VA
Vpp
Common Mode Voltage
CMOUT
-
0.43VA
-
VDC
Interchannel Gain Mismatch
-
0.1
-
dB
Gain Drift
-
100
-
ppm/C
AC-Load Resistance
R
L
5
-
-
k
Load Capacitance
C
L
-
-
100
pF
CS4391A
DS600PP3
7
ANALOG CHARACTERISTICS
(continued)
Notes: 1. Triangular PDF dithered data.
2. THD+N specifications for 48 kHz sample rates are made over a 20 kHz Bandwidth.
3. Valid with the recommended capacitor values on FILT+ and CMOUT as shown in Figure 1. Increasing
the capacitance will also increase the PSRR.
4. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 18-25) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
5. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
Parameter
Symbol
Min Typ
Max
Unit
Combined Digital and On-chip Analog Filter Response - Single Speed Mode
Passband
(Note 3)
to -0.05 dB corner
to -3 dB corner
0
0
-
-
.4535
.4998
Fs
Fs
Frequency Response 10 Hz to 20 kHz
-.02
-
+.035
dB
StopBand
.5465
-
-
Fs
StopBand Attenuation
(Note 5)
50
-
-
dB
Group Delay
tgd
-
9/Fs
-
s
Passband Group Delay Deviation
0 - 20 kHz
-
0.36/Fs
-
s
De-emphasis Error
(Relative to 1 kHz)
Control Port Mode
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
Stand-Alone Mode
Fs = 44.1 kHz
-
-
-
-
-
-
-
-
+.2/-.1
+.05/-.14
+0/.22
+.05/-.14
dB
dB
dB
dB
Combined Digital and On-chip Analog Filter Response - Double Speed Mode
Passband
(Note 4)
to -0.1 dB corner
to -3 dB corner
0
0
-
-
.4621
.4982
Fs
Fs
Frequency Response 10 Hz to 20 kHz
-0.1
-
0
dB
StopBand
.577
-
-
Fs
StopBand Attenuation
(Note 5)
55
-
-
dB
Group Delay
tgd
-
9/Fs
-
s
Passband Group Delay Deviation
0 - 20 kHz
-
0.23/Fs
-
s
On-chip Analog Filter Response - Quad Speed Mode
Passband
(Note 4)
to -3 dB corner
0
-
0.25
Fs
Frequency Response 10 Hz to 20 kHz
-0.7
-
0
dB
On-chip Analog Filter Response - DSD Mode
Passband
(Note 4)
to -3 dB corner
0
-
1.0
Fs
Frequency Response 10 Hz to 20 kHz
-0.7
-
0
dB
CS4391A
8
DS600PP3
DIGITAL CHARACTERISTICS
(AGND = 0 V; all voltages with respect to ground.)
Parameters
Symbol Min
Typ
Max
Units
High-Level Input Voltage
V
IH
70%
-
-
VL
Low-Level Input Voltage
V
IL
-
20%
VL
Input Leakage Current
I
in
-
-
10
A
Input Capacitance
-
8
-
pF
Maximum MUTEC Drive Current
-
3
-
mA
CS4391A
DS600PP3
9
SWITCHING CHARACTERISTICS - PCM MODES
(Inputs: Logic 0 = 0 V, Logic 1 = VL)
Notes: 6. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.
Parameters
Symbol Min
Typ
Max
Units
Input Sample Rate
Fs
4
-
200
kHz
LRCK Duty Cycle
45
50
55
%
MCLK Duty Cycle
40
50
60
%
SCLK Frequency
-
-
MCLK/2
Hz
SCLK Frequency
(Note 6)
-
-
MCLK/4
Hz
SCLK rising to LRCK edge delay
t
slrd
20
-
-
ns
SCLK rising to LRCK edge setup time
t
slrs
20
-
-
ns
SDATA valid to SCLK rising setup time
t
sdlrs
20
-
-
ns
SCLK rising to SDATA hold time
t
sdh
20
-
-
ns
slrs
t
s lrd
t
s d lrs
t
s d h
t
S D AT A
S C LK
L R C K
Figure 1. Serial Mode Input Timing
CS4391A
10
DS600PP3
SWITCHING CHARACTERISTICS - DSD
(Logic 0 = AGND = DGND; Logic 1 = VL)
Parameter
Symbol Min
Typ
Max
Unit
MCLK Duty Cycle
40
50
60
%
SCLK Pulse Width Low
t
sclkl
20
-
-
ns
SCLK Pulse Width High
t
sclkh
20
-
-
ns
SCLK Period
t
sclkw
20
-
-
ns
SDIN valid to SCLK rising setup time
t
sdlrs
20
-
-
ns
SCLK rising to SDIN hold time
t
sdh
20
-
-
ns
s c lk h
t
sclkl
t
S D A TA
S C LK
s dlrs
t
sd h
t
Figure 2. Direct Stream Digital - Serial Audio Input Timing
CS4391A
DS600PP3
11
SWITCHING CHARACTERISTICS - I
2
C CONTROL PORT
(Inputs: logic 0 = AGND,
logic 1 = VL)
Notes: 7. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Parameter
Symbol
Min
Max
Unit
I
2
C
Mode
SCL Clock Frequency
f
scl
-
100
KHz
RST Rising Edge to Start
t
irs
500
-
ns
Bus Free Time Between Transmissions
t
buf
4.7
-
s
Start Condition Hold Time (prior to first clock pulse)
t
hdst
4.0
-
s
Clock Low time
t
low
4.7
-
s
Clock High Time
t
high
4.0
-
s
Setup Time for Repeated Start Condition
t
sust
4.7
-
s
SDA Hold Time from SCL Falling
(Note 7)
t
hdd
0
-
s
SDA Setup time to SCL Rising
t
sud
250
-
ns
Rise Time of Both SDA and SCL Lines
t
r
-
1
s
Fall Time of Both SDA and SCL Lines
t
f
-
300
ns
Setup Time for Stop Condition
t
susp
4.7
-
s
t
buf
t
hdst
t
hdst
t
lo w
t r
t f
t
hdd
t high
t sud
t sust
t susp
Stop
S tart
S ta rt
Stop
R e p e a te d
S D A
S C L
t
irs
R S T
Figure 3. I
2
C Control Port Timing
CS4391A
12
DS600PP3
SWITCHING CHARACTERISTICS - SPI CONTROL PORT
(Inputs: logic 0 = AGND,
logic 1 = VL)
Notes: 8. t
spi
only needed before first falling edge of CS after RST rising edge. t
spi
= 0 at all other times.
9. Data must be held for sufficient time to bridge the transition time of CCLK.
10. For F
SCK
< 1 MHz
Parameter
Symbol
Min
Max
Unit
SPI Mode
CCLK Clock Frequency
f
sclk
-
6
MHz
RST Rising Edge to CS Falling
t
srs
500
-
ns
CCLK Edge to CS Falling
(Note 8)
t
spi
500
-
ns
CS High Time Between Transmissions
t
csh
1.0
-
s
CS Falling to CCLK Edge
t
css
20
-
ns
CCLK Low Time
t
scl
66
-
ns
CCLK High Time
t
sch
66
-
ns
CDIN to CCLK Rising Setup Time
t
dsu
40
-
ns
CCLK Rising to DATA Hold Time
(Note 9)
t
dh
15
-
ns
Rise Time of CCLK and CDIN
(Note 10)
t
r2
-
100
ns
Fall Time of CCLK and CDIN
(Note 10)
t
f2
-
100
ns
t r2
t f2
t dsu t dh
t sch
t scl
C S
C C L K
C D IN
t css
t csh
t spi
t srs
R S T
Figure 4. SPI Control Port Timing
CS4391A
DS600PP3
13
2.
TYPICAL CONNECTION DIAGRAMS
S C LK
Au dio
D a ta
P ro cessor
*
E xterna l C lo ck
M C L K
AG N D
AO U TB +
C S4 391A
S D AT A
V A
A OU T B-
+5V Analog
M o de
S e lect
M 1 (S DA /
C D IN
)
M 0 (A D 0/C S )
A OU T A-
A O UT A +
A na lo g
C on dition in g
&
M ute
A na lo g
C on dition in g
&
M ute
17
1 9
1 8
1 4
1 5
16
1
3
4
5
8
9
1 0
M2 (SCL/CCLK)
L R CK
1.0
f
+
RST
6
M3
7
12
1.0 f
0.1 f
1.0 f
11
FILT +
0.1 f
+
+
CMOUT
BM U T EC 1 3
AMUT EC 2 0
(Control Port)
*
2
V L
Logic Power
+5V to 1.8V
0 .1 f
Figure 5. Typical Connection Diagram - PCM Mode
* A high logic level for all digital inputs should not exceed VL.
CS4391A
14
DS600PP3
D SD _ B
A u dio
D ata
P ro ce ssor
*
E xtern al C lo ck
M CL K
A G N D
A O U T B +
CS4391A
D S D _A
V A
A OU T B -
+5V Analog
M o de
S e le ct
M 1 (S D A /
C DIN
)
M 0 (A D0 /C S )
A OU T A -
A O UT A +
V L
A na lo g
C on d itionin g
&
M ute
A na log
C on d ition in g
&
M u te
17
1 9
1 8
1 4
1 5
1 6
1
2
3
4
7
8
9
1 0
M 2 (S C L /C C LK )
D S D _ C LK
1.0
f
+
R S T
6
1 2
1.0 f
0.1 f
1.0 f
1 1
F ILT +
0.1 f
+
+
CMOUT
B M U T E C 1 3
A M U T E C 2 0
(Control Port)
5
DSD_MODE
Lo gic P ow e r
+5V to 1.8V
0.1 f
Figure 6. Typical Connection Diagram - DSD Mode
* A high logic level for all digital inputs should not exceed VL.
CS4391A
DS600PP3
15
3.
REGISTER QUICK REFERENCE
** "default" ==> bit status after power-up-sequence or reset**
3.1
MODE CONTROL 1 (ADDRESS 01H)
AMUTE (Auto-mute)
Default = `1'.
0 - Disabled
1 - Enabled
DIF2, DIF1 and DIF0 (Digital Interface Format - PCM Modes). See Table 1
Default = `0'.
000 - Format 0, Left Justified, up to 24-bit data
001 - Format 1, I
2
S, up to 24-bit data
010 - Format 2, Right Justified, 16-bit Data
011 - Format 3, Right Justified, 24-bit Data
100 - Format 4, Right Justified, 20-bit Data
101 - Format 5, Right Justified, 18-bit Data
110 - Reserved
111 - Reserved
DIF2, DIF1 and DIF0 (Digital Interface Format - DSD Mode Only). SeeTable 2
Default = `0'.
000 - Format 0, 64x oversampled DSD data with a 4x MCLK to DSD data rate
001 - Format 1, 64x oversampled DSD data with a 6x MCLK to DSD data rate
010 - Format 2, 64x oversampled DSD data with a 8x MCLK to DSD data rate
011 - Format 3, 64x oversampled DSD data with a 12x MCLK to DSD data rate
100 - Format 4, 128x oversampled DSD data with a 2x MCLK to DSD data rate
101 - Format 5, 128x oversampled DSD data with a 3x MCLK to DSD data rate
110 - Format 6, 128x oversampled DSD data with a 4x MCLK to DSD data rate
111 - Format 7, 128x oversampled DSD data with a 6x MCLK to DSD data rate
DEM1, DEM0 (De-Emphasis Mode). See Table 3
Default = `00'.
00 - No De-emphasis
01 - 44.1 kHz De-Emphasis
10 - 48 kHz De-Emphasis
11 - 32 kHz De-Emphasis
FM1, FM0 (Functional Mode). See Table 4
Default = `00'.
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
11 - Direct Stream Digital Mode
7
6
5
4
3
2
1
0
AMUTE
DIF2
DIF1
DIF0
DEM1
DEM0
FM1
FM0
1
0
0
0
0
0
0
0
CS4391A
16
DS600PP3
3.2
VOLUME AND MIXING CONTROL (ADDRESS 02H)
A = B (Channel A Volume = Channel B Volume)
Default = `0'.
0 - AOUTA volume is determined by register 03h and AOUTB volume is determined by reg-
ister 04h.
1 - AOUTA and AOUTB volumes are determined by register 03h and register 04h is ig-
nored.
Soft & Zero Cross (Soft control and zero cross detection control)
Default = `10'.
SoftZero CrossMode
00
Changes take effect immediately
01
Changes take effect on zero crossings
10
Changes take effect with a soft ramp (default)
11
Changes take effect in 1/8 dB steps on each zero crossing
ATAPI 0-4 (Channel mixing and muting). SeeTable 6
Default = `01001', (Stereo)
AOUTA = Left Channel
AOUTB = Right Channel
3.3
CHANNEL A VOLUME CONTROL (ADDRESS 03H)
See
Channel B Volume Control (address 04h)
3.4
CHANNEL B VOLUME CONTROL (ADDRESS 04H)
MUTE
Default = `0'
0 - Disabled
1 - Enabled
Volume
Default = `0'
(Refer to Table 7)
7
6
5
4
3
2
1
0
A = B
Soft
Zero Cross
ATAPI4
ATAPI3
ATAPI2
ATAPI1
ATAPI0
0
1
0
0
1
0
0
1
7
6
5
4
3
2
1
0
MUTE
VOL6
VOL5
VOL4
VOL3
VOL2
VOL1
VOL0
0
0
0
0
0
0
0
0
CS4391A
DS600PP3
17
3.5
MODE CONTROL 2 (ADDRESS 05H)
INVERT_A (Invert Channel A)
Default = `0'.
0 - Disabled
1 - Enabled
INVERT_B (Invert Channel B)
Default = `0'.
0 - Disabled
1 - Enabled
CPEN (Control Port Enable)
Default = `0'
0 - Disabled (Stand-Alone Mode)
1 - Enabled (Control Port Mode)
PDN (Power-Down)
Default ='1'.
0 - Disabled
1 - Enabled
MUTEC A=B
Default = `0'.
0 - Disabled
1 - Enabled
FREEZE
Default = 0.
0 - Disabled
1 - Enabled
MCLK Divide
Default = 0.
0 - Disabled
1 - Enabled
7
6
5
4
3
2
1
0
INVERT_A
INVERT_B
CPEN
PDN
MUTEC A = B
FREEZE
MCLK Divide
Reserved
0
0
1
1
0
0
0
0
CS4391A
18
DS600PP3
4.
REGISTER DESCRIPTION
** All register access is R/W in I
2
C mode and write only in SPI mode **
4.1
MODE CONTROL 1 - ADDRESS 01H
4.1.1
Auto-Mute (Bit 7)
Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio
samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and
muting is done independently for each channel. (However, Auto-Mute detection and muting can be-
come dependent on either channel if the Mute A = B function is enabled.) The common mode on the
output will be retained and the Mute Control pin for that channel will go active during the mute period.
The muting function is effected, similar to volume control changes, by the Soft and Zero Cross bits in
the Volume and Mixing Control register.
4.1.2
Digital Interface Formats (Bits 6:4)
Function:
PCM Mode - The required relationship between the Left/Right clock, serial clock and serial data is
defined by the Digital Interface Format and the options are detailed in Table 2 and Figures 7-24.
DSD Mode - The relationship between the oversampling ratio of the DSD audio data and the required
Master clock to DSD data rate is defined by the Digital interface Format pins. Note that the Functional
Mode registers must be set to DSD Mode.
See Table 1 (PCM Modes)
See Table 2 (DSD Mode)
4.1.3
De-Emphasis Control (Bits 3:2)
Function:
Implementation of the standard 15
s/50 s digital de-emphasis filter response, Figure 13, requires
reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample
rates. NOTE: De-emphasis is available only in Single-Speed Mode.
See Table 3
4.1.4
Functional Mode (Bits 1:0)
Function:
Selects the required range of input sample rates or DSD Mode.
See Table 4
7
6
5
4
3
2
1
0
AMUTE
DIF2
DIF1
DIF0
DEM1
DEM0
FM1
FM0
CS4391A
DS600PP3
19
4.2
VOLUME AND MIXING CONTROL (ADDRESS 02H)
4.2.1
Channel A Volume = Channel B Volume (Bit 7)
Function:
The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Vol-
ume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are de-
termined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function
is enabled.
4.2.2
Soft Ramp or Zero Cross Enable (Bits 6:5)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8 left/right clock
periods.
Zero Cross Enable
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes
or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level
change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel.
See Table 5
4.2.3
ATAPI Channel Mixing and Muting (Bits 4:0)
Function:
The CS4391A implements the channel mixing functions of the ATAPI CD-ROM specification.
See Table 6
4.3
CHANNEL A VOLUME CONTROL - ADDRESS 03H
See Section 4.4
Channel B Volume Control - Address 04h
7
6
5
4
3
2
1
0
A = B
Soft
Zero Cross
ATAPI4
ATAPI3
ATAPI2
ATAPI1
ATAPI0
CS4391A
20
DS600PP3
4.4
CHANNEL B VOLUME CONTROL - ADDRESS 04H
4.4.1
Mute (Bit 7)
Function:
The Digital-to-Analog converter output will mute when enabled. The common mode voltage on the
output will be retained. The muting function is effected, similiar to attenuation changes, by the Soft
and Zero Cross bits in the Volume and Mixing Control register. The MUTEC pin for that channel will
go active during the mute period if the Mute function is enabled. Both the AMUTEC and BMUTEC
will go active if either MUTE register is enabled and the MUTEC A = B bit (register 5) is enabled.
4.4.2
Volume Control (Bits 6:0)
Function:
The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -119 dB.
Volume settings are decoded as shown in Table 7. The volume changes are implemented as dictated
by the Soft and Zero Cross bits in the Volume and Mixing Control register. All volume settings less
than -119 dB are equivalent to enabling the Mute bit.
4.5
MODE CONTROL 2 - ADDRESS 05H
4.5.1
Invert Signal Polarity (Bits 7:6)
Function:
When set, this bit inverts the signal polarity.
4.5.2
Control Port Enable (Bit 5)
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode
can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by
the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean and
click free power-up, the user should write 30h to register 5 within 10 ms following the release of Reset.
4.5.3
Power Down (Bit 4)
Function:
The device will enter a low-power state whenever this function is activated. The power-down bit de-
faults to `enabled' on power-up and must be disabled before normal operation will begin. The contents
of the control registers are retained when the device is in power-down.
4.5.4
AMUTEC = BMUTEC (Bit 3)
Function:
When this function is enabled, the individual controls for AMUTEC and BMUTEC are internally con-
nected through a AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC
pins will go active only when the requirements for both AMUTEC and BMUTEC are valid.
7
6
5
4
3
2
1
0
MUTE
VOL6
VOL5
VOL4
VOL3
VOL2
VOL1
VOL0
7
6
5
4
3
2
1
0
INVERT_A
INVERT_B
CPEN
PDN
MUTEC A = B
FREEZE
MCLK Divide
Reserved
CS4391A
DS600PP3
21
4.5.5
Freeze (Bit 2)
Function:
This function allows modifications to the registers without the changes being taking effect until Freeze
is disabled. To make multiple changes in the Control port registers take effect simultaneously, set the
Freeze Bit, make all register changes, then Disable the Freeze bit.
4.5.6
Master Clock Divide (Bit 1)
Function:
This function allows the user to select an internal divide by 2 of the Master Clock. This selection is
required to access the higher Master Clock rates as shown in Table 9.
CS4391A
22
DS600PP3
5.
PIN DESCRIPTION - PCM DATA MODE
Reset - RST
Pin 1, Input
Function:
Hardware Mode: The device enters a low power mode and the internal state machine is reset to the de-
fault setting when low. When high, the device becomes operational.
Control Port Mode: The device enters a low power mode and all internal registers are reset to the default
settings, including the control port, when low. When high, the control port becomes operational and the
PDN bit must be cleared before normal operation will occur. The control port can not be accessed when
reset is low. The Control Port Enable Bit must also be enabled after a device reset.
RST is required to remain low until the power supplies and clocks are applied and stable.
Interface Power - VL
Pin 2, Input
Function:
Digital interface power supply. The voltage on this pin determines the logic level high threshold for the
digital inputs.
Serial Audio Data - SDATA
Pin 3, Input
Function:
Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial
clock and the channel is determined by the Left/Right clock. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte in Control Port Mode or
the Mode Pins in Hardware Mode. The options are detailed in Figures 7-24.
Reset
RST
AMUTEC
Channel A Mute Control
Logic Voltage
VL
AOUTA-
Differential Output
Serial Data
SDATA
AOUTA+
Differential Output
Serial Clock
SCLK
VA
Analog Power
Left/Right Clock
LRCK
AGND
Analog Ground
Master Clock
MCLK
AOUTB+
Differential Output
See Description
M3
AOUTB-
Differential Output
See Description (SCL/CCLK) M2
BMUTEC
Channel B Mute Control
See Description (SDA/CDIN) M1
CMOUT
Common Mode Voltage
See Description
(AD0/CS) M0
FILT+
Positive Voltage Reference
1
2
3
4
20
19
18
17
5
6
7
8
16
15
14
13
9
10
12
11
CS4391A
DS600PP3
23
Serial Clock - SCLK
Pin 4, Input
Function:
Clocks the individual bits of the serial data into the SDATA pin. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte in Control Port Mode or
the Mode pins in Hardware Mode. The options are detailed in Figures 7-24.
Left / Right Clock - LRCK
Pin 5, Input
Function:
The Left / Right clock determines which channel is currently being input on the serial audio data input,
SDATA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in
Left/Right sample pairs will be simultaneously output from the digital-to-analog converter whereas
Right/Left pairs will exhibit a one sample period difference. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte in Control Port Mode or
the Mode pins in Stand-alone Mode. The options are detailed in Figures 7-24.
Master Clock - MCLK
Pin 6, Input
Function:
The master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in Sin-
gle Speed Mode; either 128x, 192x 256x, 384x or 512x the input sample rate in Double Speed Mode; or
64x, 96x 128x, 192x or 256 x the input sample rate in Quad Speed Mode. Tables 8-10 illustrate the stan-
dard audio sample rates and the required master clock frequencies.
Note: These clocking ratios are only available in Control Port Mode when the MCLK Divide bit is enabled.
Mode Select - M3, M2, M1 and M0 (Stand-alone Mode)
Pins 7, 8, 9 and 10 Inputs
Function:
The Mode Select Pins, M0-M3, select the operational mode of the device as detailed in Tables 11-15.
Mode Select - M3 (Control Port Mode)
Pin 7, Input
Function:
The Mode Select Pin, M3, is not used in PCM Control Port mode and should be terminated to ground.
CS4391A
24
DS600PP3
Serial Control Interface Clock - SCL/CCLK (Control Port Mode)
Pin 8, Input
Function:
Clocks the serial control data into or from SDA/CDIN.
Serial Control Data I/O - SDA/CDIN (Control Port Mode)
Pin 9, Input/Output
Function:
In I
2
C mode, SDA is a data I/O line. CDIN is the input data line for the control port interface in SPI mode.
Address Bit / Chip Select - AD0 / CS (Control Port Mode)
Pin 10, Input
Function:
In I
2
C mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The
device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device
has entered the SPI mode, it will remain until either the part is reset or undergoes a power-down cycle.
Positive Voltage Reference - FILT+
Pin 11, Output
Function:
Positive reference for internal sampling circuits. External capacitors are required from FILT+ to analog
ground, as shown in Figures 5 and 6. The recommended values will typically provide 60 dB of PSRR at
1 kHz and 40 dB of PSRR at 60 Hz. FILT+ is not intended to supply external current. FILT+ has a typical
source impedance of 250 k
and any current drawn from this pin will alter device performance.
Common Mode Voltage - CMOUT
Pin 12, Output
Function:
Filter connection for internal common mode reference voltage, typically 50% of VA. Capacitors must be
connected from CMOUT to analog ground, as shown in Figures 5 and 6. CMOUT is not intended to supply
external current. CMOUT has a typical source impedance of 250 k
and any current drawn from this pin
will alter device performance.
Channel A and Channel B Mute Control - AMUTEC and BMUTEC
Pins 13 and 20, Outputs
Function:
The Mute Control pins go high during power-up initialization, reset, muting, master clock to left/right clock
frequency ratio is incorrect or power-down. These pins are intended to be used as a control for an external
mute circuit to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control
is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and
pops.
CS4391A
DS600PP3
25
Differential Analog Output - AOUTB+, AOUTB- and AOUTA+, AOUTA-
Pins 14, 15 and 18, 19, Outputs
Function:
The full scale differential analog output level is specified in the Analog Characteristics specifications table.
Analog Ground - AGND
Pin 16, Input
Function:
Analog ground reference.
Analog Power - VA
Pin 17, Input
Function:
Analog power supply.
CS4391A
26
DS600PP3
6.
PIN DESCRIPTION - DSD MODE
DSD Audio Data - DSD_A and DSD_B
Pins 3 and 4, Inputs
Function:
Direct Stream Digital audio data is clocked into DSD_A and DSD_B via the DSD serial clock.
DSD Mode - DSD_Mode
Pin 5, Input
Function:
This pin must be set to a logic `1' and M0-M2 must be properly set to access the DSD Mode in Hardware
Mode. Refer to Table 2.
In Control Port Mode, this pin must be set to a logic `1' and the Control Registers must be properly set to
access the DSD Mode. Refer to register descriptions.
Master Clock - MCLK
Pin 6, Input
Function:
The master clock frequency must be either 4x, 6x, 8x or 12x the DSD data rate for 64x oversampled DSD
data or 2x, 3x, 4x or 6x the DSD data rate for 128x oversampled DSD data.
DSD Serial Clock - DSD_SCLK
Pin 7, Input
Function:
Clocks the individual bits of the DSD audio data into the DSD_A and DSD_B pins.
Reset
RST
AMUTEC
Refer to PCM Mode
Logic Voltage
VL
AOUTA-
Refer to PCM Mode
Channel A Data
DSD_A
AOUTA+
Refer to PCM Mode
Channel B Data
DSD_B
VA
Refer to PCM Mode
DSD Mode Select
DSD_MODE
AGND
Refer to PCM Mode
Master Clock
MCLK
AOUTB+
Refer to PCM Mode
DSD Serial Clock
DSD_SCLK
AOUTB-
Refer to PCM Mode
Refer to PCM Mode (SCL/CCLK) M2
BMUTEC
Refer to PCM Mode
Refer to PCM Mode (SDA/CDIN) M1
CMOUT
Refer to PCM Mode
Refer to PCM Mode
(AD0/CS) M0
FILT+
Refer to PCM Mode
1
2
3
4
20
19
18
17
5
6
7
8
16
15
14
13
9
10
12
11
CS4391A
DS600PP3
27
DIF2
DIF1
DIFO
DESCRIPTION
0
0
0
Left Justified, up to 24-bit data
0
0
1
I
2
S, up to 24-bit data
0
1
0
Right Justified, 16-bit Data
0
1
1
Right Justified, 24-bit Data
1
0
0
Right Justified, 20-bit Data
1
0
1
Right Justified, 18-bit Data
1
1
0
Reserved
1
1
1
Reserved
Table 1. Digital Interface Formats - PCM Modes
DIF2
DIF1
DIFO
DESCRIPTION
0
0
0
64x oversampled DSD data with a 4x MCLK to DSD data rate
0
0
1
64x oversampled DSD data with a 6x MCLK to DSD data rate
0
1
0
64x oversampled DSD data with a 8x MCLK to DSD data rate
0
1
1
64x oversampled DSD data with a 12x MCLK to DSD data rate
1
0
0
128x oversampled DSD data with a 2x MCLK to DSD data rate
1
0
1
128x oversampled DSD data with a 3x MCLK to DSD data rate
1
1
0
128x oversampled DSD data with a 4x MCLK to DSD data rate
1
1
1
128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 2. Digital Interface Formats - DSD Mode
DEM1
DEMO
DESCRIPTION
0
0
Disabled
0
1
44.1 kHz de-emphasis
1
0
48 kHz de-emphasis
1
1
32 kHz de-emphasis
Table 3. De-Emphasis Mode Selection
FM1
FM0
MODE
0
0
Single-Speed Mode (4 to 50 kHz sample rates)
0
1
Double-Speed Mode (50 to 100 kHz sample rates)
1
0
Quad-Speed Mode (100 to 200 kHz sample rates)
1
1
Direct Stream Digital Mode
Table 4. Functional Mode Selection
SOFT
ZERO
Mode
0
0
Changes to affect immediately
0
1
Zero Cross enabled
1
0
Soft Ramp enabled
1
1
Soft Ramp and Zero Cross enabled
Table 5. Soft Cross or Zero Cross Mode Selection
CS4391A
28
DS600PP3
ATAPI4
ATAPI3
ATAPI2
ATAPI1
ATAPI0
AOUTA
AOUTB
0
0
0
0
0
MUTE
MUTE
0
0
0
0
1
MUTE
bR
0
0
0
1
0
MUTE
bL
0
0
0
1
1
MUTE
b[(L+R)/2]
0
0
1
0
0
aR
MUTE
0
0
1
0
1
aR
bR
0
0
1
1
0
aR
bL
0
0
1
1
1
aR
b[(L+R)/2]
0
1
0
0
0
aL
MUTE
0
1
0
0
1
aL
bR
0
1
0
1
0
aL
bL
0
1
0
1
1
aL
b[(L+R)/2]
0
1
1
0
0
a[(L+R)/2]
MUTE
0
1
1
0
1
a[(L+R)/2]
bR
0
1
1
1
0
a[(L+R)/2]
bL
0
1
1
1
1
a[(L+R)/2]
b[(L+R)/2]
1
0
0
0
0
MUTE
MUTE
1
0
0
0
1
MUTE
bR
1
0
0
1
0
MUTE
bL
1
0
0
1
1
MUTE
[(bL+aR)/2]
1
0
1
0
0
aR
MUTE
1
0
1
0
1
aR
bR
1
0
1
1
0
aR
bL
1
0
1
1
1
aR
[(aL+bR)/2]
1
1
0
0
0
aL
MUTE
1
1
0
0
1
aL
bR
1
1
0
1
0
aL
bL
1
1
0
1
1
aL
[(aL+bR)/2]
1
1
1
0
0
[(aL+bR)/2]
MUTE
1
1
1
0
1
[(aL+bR)/2]
bR
1
1
1
1
0
[(bL+aR)/2]
bL
1
1
1
1
1
[(aL+bR)/2]
[(aL+bR)/2]
Table 6. ATAPI Decode
Binary Code
Decimal Value
Volume Setting
0000000
0
0 dB
0010100
20
-20 dB
0101000
40
-40 dB
0111100
60
-60 dB
1011010
90
-90 dB
Table 7. Digital Volume Control
CS4391A
DS600PP3
29
Note:These clocking ratios are only available inControl Port Mode when the MCLK Divide bit is enabled.
Sample Rate
(kHz)
MCLK (MHz)
See Note
256x
384x
512x
768x
1024x
32
8.1920
12.2880
16.3840
24.5760
32.7680
44.1
11.2896
16.9344
22.5792
33.8688
45.1584
48
12.2880
18.4320
24.5760
36.8640
49.1520
Table 8. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies
Sample Rate
(kHz)
MCLK (MHz)
See Note
128x
192x
256x
384x
512x
64
8.1920
12.2880
16.3840
24.5760
32.7680
88.2
11.2896
16.9344
22.5792
33.8688
45.1584
96
12.2880
18.4320
24.5760
36.8640
49.1520
Table 9. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies
Sample Rate
(kHz)
MCLK (MHz)
See Note
64x
96x
128x
192x
256x
176.4
11.2896
16.9344
22.5792
33.8688
45.1584
192
12.2880
18.4320
24.5760
36.8640
49.1520
Table 10. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies
M3
M1
(DIF1)
M0
(DIF0)
DESCRIPTION
FORMAT
FIGURE
0
0
0
Left Justified, up to 24-bit data
0
7
0
0
1
I
2
S, up to 24-bit data
1
8
0
1
0
Right Justified, 16-bit Data
2
9
0
1
1
Right Justified, 24-bit Data
3
10
Table 11. Single Speed (4 to 50 kHz) Digital Interface Format, Stand-Alone Mode Options
M3
M2
(DEM)
DESCRIPTION
FIGURE
0
0
No De-Emphasis
13
0
1
De-Emphasis Enabled
13
Table 12. Single Speed Only (4 to 50 kHz) De-Emphasis, Stand-Alone Mode Options
M3
M2
M1
M0
DESCRIPTION
FORMAT
FIGURE
1
0
0
0
Left Justified up to 24-bit data
0
7
1
0
0
1
I
2
S up to 24-bit data
1
8
1
0
1
0
Right Justified 16-bit data
2
9
1
0
1
1
Right Justified 24-bit data
3
10
Table 13. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options
CS4391A
30
DS600PP3
M3
M2
M1
M0
DESCRIPTION
FORMAT
FIGURE
1
1
0
0
Left Justified up to 24-bit data
0
7
1
1
0
1
I
2
S up to 24-bit data
1
8
1
1
1
0
Right Justified 16-bit data
2
9
1
1
1
1
Right Justified 24-bit data
3
10
Table 14. Quad Speed (100 to 200 kHz) Digital Interface Format, Stand-Alone Mode Options
DSD_Mode
M2
M1
M0
DESCRIPTION
1
0
0
0
64x oversampled DSD data with a 4x MCLK to DSD data rate
1
0
0
1
64x oversampled DSD data with a 6x MCLK to DSD data rate
1
0
1
0
64x oversampled DSD data with a 8x MCLK to DSD data rate
1
0
1
1
64x oversampled DSD data with a 12x MCLK to DSD data rate
1
1
0
0
128x oversampled DSD data with a 2x MCLK to DSD data rate
1
1
0
1
128x oversampled DSD data with a 3x MCLK to DSD data rate
1
1
1
0
128x oversampled DSD data with a 4x MCLK to DSD data rate
1
1
1
1
128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 15. Direct Stream Digital (DSD), Stand-Alone Mode Options
CS4391A
DS600PP3
31
Figure 7. Format 0, Left Justified up to 24-Bit Data
L R C K
S C L K
L eft C ha n n el
R igh t C ha n n el
S D A T A
+3 +2 +1 LS B
+5 +4
M SB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
M SB -1 -2 -3 -4
Figure 8. Format 1, I
2
S up to 24-Bit Data
L R C K
S C L K
L eft C ha n n el
R igh t C ha n n el
S D A T A
+3 +2 +1 LS B
+5 +4
MS B -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4
LRCK
SCLK
Le ft C h a n ne l
R ig h t C h a nn e l
SDATA
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
3 2 clo cks
Figure 9. Format 2, Right Justified 16-Bit Data
Figure 10. Format 3, Right Justified 24-Bit Data
LRCK
SCLK
L e ft C h a n ne l
SDATA
6
5
4
3
2
1
0
7
23 22 21 20 19 18
6
5
4
3
2
1
0
7
23 22 21 20 19 18
3 2 clo cks
0
R ig h t C h a n ne l
CS4391A
32
DS600PP3
L R C K
S C L K
L e ft C h a n n e l
R ig h t C h a n n e l
S D A T A
6
5
4
3
2
1
0
9
8
7
15 14 1 3 1 2 11 10
1
0
6
5
4
3
2
1
0
9
8
7
1 5 1 4 1 3 1 2 1 1 1 0
17 16
1 7 1 6
3 2 cloc ks
1 9 1 8
1 9 1 8
Figure 11. Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only)
L R C K
S C L K
L eft C h a nn e l
R ig h t C h a n ne l
S D A T A
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
1
0
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
17 16
17 16
32 clocks
Figure 12. Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)
Gain
dB
-10dB
0dB
Frequency
T2 = 15 s
T1=50 s
F1
F2
3.183 kHz
10.61 kHz
Figure 13. De-Emphasis Curve
A Channel
Volume
Control
AoutA
AoutB
Left Channel
Audio Data
Right Channel
Audio Data
B Channel
Volume
Control
MUTE
MUTE
Figure 14. ATAPI Block Diagram
CS4391A
DS600PP3
33
7. APPLICATIONS
7.1
Recommended Power-up
Sequence for Hardware Mode
1) Hold
RST
low until the power supplies, master,
and left/right clocks are stable.
2) Bring
RST
high.
7.2
Recommended Power-up
Sequence and Access to Control
Port Mode
1) Hold
RST
low until the power supply, master,
and left/right clocks are stable. In this state, the
control port is reset to its default settings and
CMOUT will remain low.
2) Bring
RST
high. The device will remain in a
low power state with CMOUT low and the con-
trol port is accessible.
3) Write 30h to register 5 within 10 ms cycles fol-
lowing the release of RST.
4) The desired register settings can be loaded
while keeping the PDN bit set to 1.
5) Set the PDN bit to 0 which will initiate the pow-
er-up sequence which requires approximately
10 S.
7.3
Analog Output and Filtering
The application note "Design Notes for a 2-Pole
Filter with Differential Input" discusses the second-
order Butterworth filter and differential to single-
ended converter which was implemented on the
CS4391A evaluation board, CDB4391A. The
CS4391A filter, as seen in Figure 14, is a linear
phase design and does not include phase or ampli-
tude compensation for an external filter. Therefore,
the DAC system phase and amplitude response will
be dependent on the external analog circuitry.
AMUTEC
AOUTA+
GND
C43
10UF
GND
GND
GND
1.18K
R17
NC
4
3
2
1
CON_RCA_RA
J3
2
3
1
2SC2878
Q1
2K
R25
3
1
2
Q3
MMUN2111LT1
12
HDR8
HDR1X2
AOUTA
VA+3/+5
R20
560
3
1
2
Q4
MMUN2211LT1
R24
5.62K
R5
47K
R28
5.62K
1.18K
R18
5.62K
R15
5.62K
R26
C49
.1UF
V-
V+
+
-
4
8
1
2
3
U11
MC33078D
C48
.1UF
GND
GND
GND
GND
GND
GND
C42
10UF
COG
2700PF
C7
COG
560PF
C6
COG
C5
560PF
COG
2700PF
C14
VCC
VEE
AOUTA-
Figure 15. CS4391A Output Filter
CS4391A
34
DS600PP3
8. CONTROL PORT INTERFACE
The control port is used to load all the internal set-
tings of the CS4391A. The operation of the control
port may be completely asynchronous to the audio
sample rate. However, to avoid potential interfer-
ence problems, the control port pins should remain
static if no operation is required.
The control port has 2 modes: SPI and I
2
C, with the
CS4391A operating as a slave device in both
modes. If I
2
C operation is desired, AD0/CS should
be tied to VA or AGND. If the CS4391A ever de-
tects a high to low transition on AD0/CS after pow-
er-up, SPI mode will be selected. The control port
registers are write-only in SPI mode.
8.1
SPI Mode
In SPI mode, CS is the CS4391A chip select signal,
CCLK is the control port bit clock, CDIN is the in-
put data line from the microcontroller and the chip
address is 0010000. All signals are inputs and data
is clocked in on the rising edge of CCLK.
Figure 16 shows the operation of the control port in
SPI mode. To write to a register, bring CS low. The
first 7 bits on CDIN form the chip address, and
must be 0010000. The eighth bit is a read/write in-
dicator (R/W), which must be low to write. The
next 8 bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next 8 bits are the data
which will be placed into the register designated by
the MAP. See Table 16.
The CS4391A has MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is 0, then the MAP will stay constant for suc-
cessive writes. If INCR is set to 1, then MAP will
auto increment after each byte is written, allowing
block reads or writes of successive registers.
8.2
I
2
C Mode
In I
2
C mode, SDA is a bi-directional data line. Data
is clocked into and out of the part by the clock,
SCL, with the clock to data relationship as shown
in Figure 3. There is no CS pin. Pin AD0 forms the
partial chip address and should be tied to VA or
AGND as required. The upper 6 bits of the 7-bit ad-
dress field must be 001000. To communicate with
the CS4391A the LSB of the chip address field,
which is the first byte sent to the CS4391A, should
match the setting of the AD0 pin. The eighth bit of
the address byte is the R/W bit (high for a read, low
for a write). If the operation is a write, the next byte
is the Memory Address Pointer, MAP, which se-
lects the register to be read or written. The MAP is
then followed by the data to be written. If the op-
eration is a read, then the contents of the register
pointed to by the MAP will be output after the chip
address.
The CS4391A has MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is 0, then the MAP will stay constant for suc-
cessive writes. If INCR is set to 1, then MAP will
auto increment after each byte is written, allowing
block reads or writes of successive registers.
For more information on I
2
C, please see "The I2C-
Bus Specification: Version 2.0", listed in the Ref-
erences section.
CS4391A
DS600PP3
35
7
6
5
4
3
2
1
0
INCR
Reserved
Reserved
Reserved
Reserved
MAP2
MAP1
MAP0
0
0
0
0
0
0
0
0
INCR (Auto MAP Increment Enable)
Default = `0'.
0 - Disabled
1 - Enabled
MAP0-2 (Memory Address Pointer)
Default = `000'.
Table 16. Memory Address Pointer (MAP)
M A P
MSB
LS B
DATA
b yte 1
b yte n
R/W
M AP = M e m ory Ad d re s s P o in te r
ADDRESS
C H IP
C D IN
C C L K
CS
0 01 00 0 0
Figure 16. Control Port Timing, SPI mode
S D A
S C L
0 010 00
A D D R
A D 0
R /W
S ta rt
A C K
D A T A
1 -8
A C K
D A T A
1-8
A C K
Stop
N o te : If o p e ra tio n is a w rite , th is b yte co n ta in s th e M e m o ry A d d re ss P o in te r, M A P .
N o te 1
Figure 17. Control Port Timing, I
2
C Mode
CS4391A
36
DS600PP3
-0.25
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (normalized to Fs)
A
mp
li
tu
d
e
dB
Figure 18. Single-Speed Frequency Response
Figure 19. Single-Speed Transition Band
Figure 20. Single-Speed Transition Band
Figure 21. Single-Speed Stopband Rejection
-0.25
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (normalized to Fs)
Am
pl
it
ude
dB
Figure 22. Double-Speed Frequency Response
Figure 23. Double-Speed Transition Band
CS4391A
DS600PP3
37
Figure 24. Double-Speed Transition Band
Figure 25. Double-Speed Stopband Rejection
CS4391A
38
DS600PP3
9. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
effect the measurement. This measurement technique has been accepted by the Audio Engineering So-
ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/C.
10.REFERENCES
1. "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris.
Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2. CDB4391A Evaluation Board Datasheet
3. "The I
2
C-Bus Specification: Version 2.0" Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
CS4391A
DS600PP3
39
11.PACKAGE DIMENSIONS
Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not
reduce dimension "b" by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
INCHES
MILLIMETERS
NOTE
DIM
MIN
NOM
MAX
MIN
NOM
MAX
A
--
--
0.043
--
--
1.10
A1
0.002
0.004
0.006
0.05
--
0.15
A2
0.03346
0.0354
0.037
0.85
0.90
0.95
b
0.00748
0.0096
0.012
0.19
0.245
0.30
2,3
D
0.252
0.256
0.259
6.40
6.50
6.60
1
E
0.248
0.2519
0.256
6.30
6.40
6.50
E1
0.169
0.1732
0.177
4.30
4.40
4.50
1
e
--
--
0.026
--
--
0.65
L
0.020
0.024
0.028
0.50
0.60
0.70
0
4
8
0
4
8
JEDEC #: MO-153
Controlling Dimension is Millimeters.
20L TSSOP (4.4 mm BODY) PACKAGE DRAWING
E
N
1 2 3
e
b
2
A1
A2
A
D
SEATING
PLANE
E1
1
L
SIDE VIEW
END VIEW
TOP VIEW
CS4391A
40
DS600PP3
PACKAGE DIMENSIONS
(cont.).
INCHES
MILLIMETERS
DIM
MIN
NOM
MAX
MIN
NOM
MAX
A 0.093
0.098
0.104
2.35
2.50
2.65
A1
0.004
0.008
0.012
0.10
0.20
0.30
b
0.013
0.017
0.020
0.33
0.43
0.51
C
0.009
0.011
0.013
0.23
0.28
0.32
D
0.496
0.504
0.512
12.60
12.80
13.00
E
0.291
0.295
0.299
7.40
7.50
7.60
e
0.040
0.050
0.060
1.02
1.27
1.52
H
0.394
0.407
0.419
10.00
10.34
10.65
L
0.016
0.025
0.050
0.40
0.64
1.27
0
4
8
0
4
8
JEDEC #: MS-013
Controlling Dimension is Millimeters
20L SOIC (300 MIL BODY) PACKAGE DRAWING
D
H
E
b
A1
A
c
L
SEATING
PLANE
e
1
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