Document Outline
- CS43L41 Low Power 24-Bit, 96 kHz DAC with Volume Control
- Features
- Description
- ORDERING INFORMATION
- TABLE OF CONTENTS
- LIST OF FIGURES
- LIST OF TABLES
- 1. CHARACTERISTICS AND SPECIFICATIONS
- ANALOG CHARACTERISTICS
- POWER AND THERMAL CHARACTERISTICS
- DIGITAL CHARACTERISTICS
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- SWITCHING CHARACTERISTICS
- SWITCHING CHARACTERISTICS - CONTROL PORT
- 2. TYPICAL CONNECTION DIAGRAM
- 3. REGISTER QUICK REFERENCE
- 3.1 MCLK Control (address 00h)
- 3.2 Mode Control (address 01h)
- 3.3 Volume and Mixing Control (address 02h)
- 3.4 Channel A Volume Control (address 03h)
- 3.5 Channel B Volume Control (address 04h)
- 4. REGISTER BIT DESCRIPTION
- 4.1 MASTER CLOCK DIVIDE ENABLE
- 4.2 AUTO-MUTE
- 4.3 DIGITAL INTERFACE FORMAT
- 4.4 DE-EMPHASIS CONTROL
- 4.5 POWER ON/OFF QUIESCENT VOLTAGE RAMP
- 4.6 POWER DOWN
- 4.7 CHANNEL A VOLUME = CHANNEL B VOLUME
- 4.8 SOFT RAMP OR ZERO CROSS ENABLE
- 4.9 ATAPI CHANNEL MIXING AND MUTING
- 4.10 MUTE
- 4.11 VOLUME CONTROL
- 5. PIN DESCRIPTION
- Analog Power - VA
- Analog Ground - AGND
- Analog Output - AOUTA and AOUTB
- Reference Ground - REF_GND
- Positive Voltage Reference - FILT+
- Quiescent Voltage - VQ
- Master Clock - MCLK
- Left/Right Clock - LRCK
- Serial Audio Data - SDATA
- Serial Clock - SCLK
- Reset - RST
- Serial Control Interface Clock - SCL/CCLK
- Serial Control Data I/O - SDA/CDIN
- Address Bit / Chip Select - AD0/CS
- Mute Control - MUTEC
- 6. APPLICATIONS
- 6.1 Grounding and Power Supply Decoupling
- 6.2 Oversampling Modes
- 6.3 Recommended Power-up Sequence
- 6.4 Use of the Power ON/OFF Quiescent Voltage Ramp
- 7. CONTROL PORT INTERFACE
- 7.1 SPI Mode
- 7.2 I 2 C Compatible Mode
- 7.3 MEMORY ADDRESS POINTER (MAP)
- 8. PARAMETER DEFINITIONS
- Total Harmonic Distortion + Noise (THD+N)
- Dynamic Range
- Interchannel Isolation
- Interchannel Gain Mismatch
- Gain Error
- Gain Drift
- 9. REFERENCES
- 10. PACKAGE DIMENSIONS
Advanced Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 1999
(All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CS43L41
Low Power 24-Bit, 96 kHz DAC with Volume Control
Features
l
Complete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
l
ATAPI Mixing
l
101 dB Dynamic Range
l
89 dBFS THD+N
l
Low Clock Jitter Sensitivity
l
+2.4 V to +5 V Power Supply
l
Filtered Line Level Outputs
l
On-Chip Digital De-emphasis for 32, 44.1,
and 48 kHz
l
Digital Volume Control with Soft Ramp
94 dB Attenuation
1 dB Step Size
Zero Crossing Click-Free Transitions
l
24 mW with 2.4 V supply
Description
The CS43L41 is a complete stereo digital-to-analog sys-
tem including digital interpolation, fourth-order delta-
sigma digital-to-analog conversion, digital de-emphasis,
volume control, channel mixing and analog filtering. The
advantages of this architecture include: ideal differential
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and tempera-
ture and a high tolerance to clock jitter.
The CS43L41 accepts data at audio sample rates from
2 kHz to 100 kHz, consumes very little power and oper-
ates over a wide power supply range. These features are
ideal for portable DVD, portable MP3, Mini-Disc, and
mobile phones.
ORDERING INFORMATION
CS43L41-KZ
16-pin TSSOP, -10 to 70 C
I
Volume Control
Interpolation Filter
DAC
Analog Filter
Control Port
Volume Control
Interpolation Filter
Analog Filter
Se
r
i
al
P
ort
SCL/CCLK
MUTEC
AD0/CS
AOUTA
AOUTB
RST
LRCK
SDATA
MCLK
SDA/CDIN
DAC
External
Mute Control
SCLK
Mixer
2
SEP `99
DS473PP1
CS43L41
2
DS473PP1
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5
ANALOG CHARACTERISTICS ................................................................................................ 5
POWER AND THERMAL CHARACTERISTICS....................................................................... 7
DIGITAL CHARACTERISTICS ................................................................................................. 7
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 7
RECOMMENDED OPERATING CONDITIONS ....................................................................... 7
SWITCHING CHARACTERISTICS .......................................................................................... 8
SWITCHING CHARACTERISTICS - CONTROL PORT......................................................... 10
2. TYPICAL CONNECTION DIAGRAM .................................................................................... 11
3. REGISTER QUICK REFERENCE .......................................................................................... 14
3.1 MCLK Control (address 00h) ............................................................................................ 14
3.2 Mode Control (address 01h) ............................................................................................. 14
3.3 Volume and Mixing Control (address 02h)........................................................................ 15
3.4 Channel A Volume Control (address 03h) ........................................................................ 15
3.5 Channel B Volume Control (address 04h) ........................................................................ 15
4. REGISTER BIT DESCRIPTION .............................................................................................. 16
4.1 Master Clock Divide Enable.............................................................................................. 16
4.2 Auto-Mute ......................................................................................................................... 16
4.3 Digital Interface Format..................................................................................................... 17
4.4 De-emphasis Control ........................................................................................................ 17
4.5 Power On/Off Quiescent Voltage Ramp ........................................................................... 18
4.6 Power Down...................................................................................................................... 18
4.7 Channel A Volume = Channel B Volume .......................................................................... 19
4.8 Soft Ramp or Zero Cross Enable...................................................................................... 19
4.9 ATAPI Channel Mixing and Muting ................................................................................... 20
4.10 Mute ................................................................................................................................ 21
4.11 Volume Control ............................................................................................................... 22
5. PIN DESCRIPTION ................................................................................................................. 23
Analog Power - VA.................................................................................................................. 23
Analog Ground - AGND .......................................................................................................... 23
Analog Output - AOUTA and AOUTB ..................................................................................... 23
Reference Ground - REF_GND .............................................................................................. 23
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
I
2
C is a registered trademark of Philips Semiconductors.
SPI is a registered trademark of International Business Machines Corporation.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.
CS43L41
DS473PP1
3
Confidential Draft
9/23/99
Positive Voltage Reference - FILT+........................................................................................ 22
Quiescent Voltage - VQ .......................................................................................................... 22
Master Clock - MCLK ............................................................................................................. 23
Left/Right Clock - LRCK ......................................................................................................... 23
Serial Audio Data - SDATA .................................................................................................... 23
Serial Clock - SCLK ................................................................................................................ 24
Reset - RST ............................................................................................................................ 24
Serial Control Interface Clock - SCL/CCLK ........................................................................... 24
Serial Control Data I/O - SDA/CDIN ....................................................................................... 24
Address Bit / Chip Select - AD0/CS........................................................................................ 24
Mute Control - MUTEC ........................................................................................................... 24
6. APPLICATIONS ..................................................................................................................... 25
6.1 Grounding and Power Supply Decoupling ....................................................................... 25
6.2 Oversampling Modes ....................................................................................................... 25
6.3 Recommended Power-up Sequence ............................................................................... 25
6.4 Use of the Power ON/OFF Quiescent Voltage Ramp ..................................................... 25
7. CONTROL PORT INTERFACE .............................................................................................. 26
7.1 SPI Mode ......................................................................................................................... 26
7.2 I
2
C Compatible Mode ...................................................................................................... 26
7.3 Memory Address Pointer (MAP) ....................................................................................... 27
8. PARAMETER DEFINITIONS .................................................................................................. 33
Total Harmonic Distortion + Noise (THD+N) .......................................................................... 33
Dynamic Range ...................................................................................................................... 33
Interchannel Isolation ............................................................................................................. 33
Interchannel Gain Mismatch ................................................................................................... 33
Gain Error ............................................................................................................................... 33
Gain Drift ................................................................................................................................ 33
9. REFERENCES ........................................................................................................................ 33
10. PACKAGE DIMENSIONS .................................................................................................... 34
CS43L41
4
DS473PP1
LIST OF FIGURES
Figure 1.
External Serial Mode Input Timing ................................................................................. 9
Figure 2.
Internal Serial Mode Input Timing .................................................................................. 9
Figure 3.
Internal Serial Clock Generation .................................................................................... 9
Figure 4.
I
2
C Control Port Timing ................................................................................................ 10
Figure 5.
SPI Control Port Timing ............................................................................................... 12
Figure 6.
Typical Connection Diagram ........................................................................................ 13
Figure 7.
SPI Mode Control Port Formatting ............................................................................... 28
Figure 8.
I
2
C Mode Control Port Formatting ................................................................................ 28
Figure 9.
Base-Rate Stopband Rejection .................................................................................... 29
Figure 10. Base-Rate Transition Band .......................................................................................... 29
Figure 11. Base-Rate Transition Band (Detail) ............................................................................. 29
Figure 12. Base-Rate Passband Ripple ........................................................................................ 29
Figure 13. High-Rate Stopband Rejection ..................................................................................... 29
Figure 14. High-Rate Transition Band ........................................................................................... 29
Figure 15. High-Rate Transition Band (Detail) .............................................................................. 30
Figure 16. High-Rate Passband Ripple ......................................................................................... 30
Figure 17. Output Test Load ......................................................................................................... 30
Figure 18. Maximum Loading ........................................................................................................ 30
Figure 19. Power vs. Sample Rate (VA = 5V) ............................................................................... 30
Figure 20. CS43L41 Format 0 (I
2
S) .............................................................................................. 31
Figure 21. CS43L41 Format 1 (I
2
S) .............................................................................................. 31
Figure 22. CS43L41 Format 2 ....................................................................................................... 31
Figure 23. CS43L41 Format 3 ....................................................................................................... 32
Figure 24. CS43L41 Format 4 ....................................................................................................... 32
Figure 25. CS43L41 Format 5 ....................................................................................................... 32
Figure 26. CS43L41 Format 6 ....................................................................................................... 33
Figure 27. De-Emphasis Curve ..................................................................................................... 33
Figure 28. ATAPI Block Diagram .................................................................................................. 33
LIST OF TABLES
Table 1. Master Clock Divide Enable ............................................................................................... 16
Table 2. Auto-Mute Enable ............................................................................................................... 16
Table 3. Digital Interface Formats .................................................................................................... 17
Table 4. De-emphasis Filter Configurations ..................................................................................... 17
Table 5. Power On/Off Ramp Enable ............................................................................................... 18
Table 6. Power Down Enable ........................................................................................................... 18
Table 7. A=B Volume Control Enable............................................................................................... 19
Table 8. Soft Ramp and Zero Cross Enable..................................................................................... 20
Table 9. ATAPI Decode .................................................................................................................... 20
Table 10. Mute Enable ..................................................................................................................... 21
Table 11. Digital Volume Settings .................................................................................................... 22
Table 12. Common Clock Frequencies ............................................................................................ 24
CS43L41
DS473PP1
5
1.
CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS
(T
A
= 25 C; Logic "1" = VA; Logic "0" = AGND;
Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz,
Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for High-Rate Mode = 96 kHz,
SCLK = 6.144 MHz, Measurement Bandwidth 10 Hz to 40 kHz, unless otherwise specified. Test load R
L
= 10 k
,
C
L
= 10 pF (see Figure 17)),
Notes: 1. One-half LSB of triangular PDF dither is added to data.
Parameter
Base-rate Mode
High-Rate Mode
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Dynamic Performance for VA = 5 V
Specified Temperature Range
T
A
-10
-
70
-10
-
70
C
Dynamic Range
(Note 1)
18 to 24-Bit
unweighted
A-Weighted
16-Bit unweighted
A-Weighted
92
96
-
-
97
101
95
99
-
-
-
-
91
95
-
-
96
100
94
98
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 1)
18 to 24-Bit
0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
THD+N
-
-
-
-
-
-
-89
-77
-37
-88
-75
-35
-84
-72
-32
-
-
-
-
-
-
-
-
-
-89
-74
-36
-89
-73
-34
-84
-69
-31
-
-
-
dB
dB
dB
dB
dB
dB
Interchannel Isolation
(1 kHz)
-
100
-
-
100
-
dB
Dynamic Performance for VA = 2.4 V
Specified Temperature Range
T
A
-10
-
70
-10
-
70
C
Dynamic Range
(Note 1)
18 to 24-Bit
unweighted
A-Weighted
16-Bit unweighted
A-Weighted
TBD
TBD
-
-
92
95
91
94
-
-
-
-
TBD
TBD
-
-
91
95
90
94
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 1)
18 to 24-Bit
0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
THD+N
-
-
-
-
-
-
-91
-72
-32
-90
-71
-31
TBD
TBD
TBD
-
-
-
-
-
-
-
-
-
-89
-71
-31
-88
-70
-30
TBD
TBD
TBD
-
-
-
dB
dB
dB
dB
dB
dB
Interchannel Isolation
(1 kHz)
-
100
-
-
100
-
dB
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