Document Outline

• 1. Characteristics and Specifications
  • Figure 1. Performance Characteristics Evaluation Active Filter Circuit
  • Figure 2. XTI Timings
  • Figure 3. SYS_CLK Timings
  • Figure 4. PWMOUTxx Timings
  • Figure 5. PS_SYNC Timings
  • Figure 6. Serial Audio Interface Timing
  • Figure 7. Serial Audio Interface Timing - TDM Mode
  • Figure 8. Control Port Timing - I�C Format
  • Figure 9. Control Port Timing - SPI Format
• 2. Pin Descriptions
  • Figure 10. CS44600 Pinout Diagram
  • 2.1 I/O Pin Characteristics
• 3. Typical Connection Diagrams
  • Figure 11. Typical Full-Bridge Connection Diagram
  • Figure 12. Typical Half-Bridge Connection Diagram
• 4. Applications
  • 4.1 Overview
  • 4.2 Feature Set Summary
    • Figure 13. CS44600 Data Flow Diagram (Single Channel Shown)
  • 4.3 Clock Generation
    • 4.3.1 FsIn Domain Clocking
    • Table 1. Common DAI_MCLK Frequencies
    • 4.3.2 FsOut Domain Clocking
    • Figure 14. Fundamental Mode Crystal Configuration
    • Figure 15. 3rd Overtone Crystal Configuration
    • Figure 16. CS44600 Internal Clock Generation
  • 4.4 FsIn Clock Domain Modules
    • 4.4.1 Digital Audio Input Port
    • Table 2. DAI Serial Audio Port Channel Allocations
    • Figure 17. I�S Serial Audio Formats
    • Figure 18. Left-Justified Serial Audio Formats
    • Figure 19. Right-Justified Serial Audio Formats
    • Figure 20. One Line Mode #1 Serial Audio Format
    • Figure 21. One Line Mode #2 Serial Audio Format
    • Figure 22. TDM Mode Serial Audio Format
    • 4.4.2 Auto Rate Detect
    • 4.4.3 De-Emphasis
    • Figure 23. De-Emphasis Curve
  • 4.5 FsOut Clock Domain Modules
    • 4.5.1 Sample Rate Converter
    • 4.5.2 Load Compensation Filter
    • Table 3. Load Compensation Example Settings
    • 4.5.3 Digital Volume and Mute Control
    • 4.5.4 Peak Detect / Limiter
    • 4.5.5 PWM Engines
    • Table 4. Typical PWM Switch Rate Settings
    • 4.5.6 Interpolation Filter
    • 4.5.7 Quantizer
    • 4.5.8 Modulator
    • 4.5.9 PWM Outputs
    • 4.5.10 Power Supply Rejection (PSR) Real-Time Feedback
  • 4.6 Control Port Description and Timing
    • 4.6.1 SPI Mode
    • Figure 24. Control Port Timing in SPI Mode
    • 4.6.2 I�C Mode
    • Figure 25. Control Port Timing, I�C Slave Mode Write
    • Figure 26. Control Port Timing, I�C Slave Mode Read
    • 4.6.3 GPIOs
    • 4.6.4 Host Interrupt
• 5. Power Supply, Grounding, and PCB layout
  • Figure 27. Recommended CS44600 Power Supply Decoupling Layout
  • Figure 28. Recommended CS44600 Crystal Circuit Layout
  • Figure 29. Recommended PSR Circuit Layout
  • 5.1 Reset and Power-Up
    • 5.1.1 PWM PopGuard� Transient Control
    • 5.1.2 Recommended Power-Up Sequence
    • 5.1.3 Recommended PSR Calibration Sequence
    • Figure 30. PSR Calibration Sequence
    • 5.1.4 Recommended Power-Down Sequence
• 6. Register Quick Reference
• 7. Register Description
  • 7.1 Memory Address Pointer (MAP)
    • 7.1.1 Increment (INCR)
    • 7.1.2 Memory Address Pointer (MAPx)
  • 7.2 CS44600 I.D. and Revision Register (address 01h) (Read Only)
    • 7.2.1 Chip I.D. (Chip_IDx)
    • 7.2.2 Chip Revision (Rev_IDx)
  • 7.3 Clock Configuration and Power Control (address 02h)
    • 7.3.1 Enable SYS_CLK Output (EN_SYS_CLK)
    • 7.3.2 SYS_CLK Clock Divider Settings (SYS_CLK_DIV[1:0])
    • 7.3.3 PWM Master Clock Divider Settings (PWM_MCLK_DIV[1:0])
    • 7.3.4 Power Down XTAL (PDN_XTAL)
    • 7.3.5 Power Down Output Mode (PDN_OUTPUT_MODE)
    • 7.3.6 Power Down (PDN)
  • 7.4 PWM Channel Power Down Control (address 03h)
    • 7.4.1 Power Down PWM Channels (PDN_PWMB3:PDN_PWMA1)
  • 7.5 Misc. Configuration (address 04h)
    • 7.5.1 Digital Interface Format (DIFX)
    • Table 5. Digital Audio Interface Formats
    • 7.5.2 AM Frequency Hopping (AM_FREQ_HOP)
    • 7.5.3 Freeze Controls (FREEZE)
    • 7.5.4 De-Emphasis Control (DEM[1:0])
  • 7.6 Ramp Configuration (address 05h)
    • 7.6.1 Ramp-Up/Down Setting (RAMP[1:0])
    • 7.6.2 Ramp Speed (RAMP_SPD[1:0])
  • 7.7 Volume Control Configuration (address 06h)
    • 7.7.1 Single Volume Control (SNGVOL)
    • 7.7.2 Soft Ramp and Zero Cross Control (SZC[1:0])
    • 7.7.3 Enable 50% Duty Cycle for Mute Condition (MUTE_50/50)
    • 7.7.4 Soft Ramp-Down on Interface Error (SRD_ERR)
    • 7.7.5 Soft Ramp-Up on Recovered Interface Error (SRU_ERR)
    • 7.7.6 Auto-Mute (AMUTE)
  • 7.8 Master Volume Control - Integer (address 07h)
    • 7.8.1 Master Volume Control - Integer (MSTR_IVOL[7:0])
    • Table 6. Master Integer Volume Settings
  • 7.9 Master Volume Control - Fraction (address 08h)
    • 7.9.1 Master Volume Control - Fraction (MSTR_FVOL[1:0])
    • Table 7. Master Fractional Volume Settings
  • 7.10 Channel XX Volume Control - Integer (addresses 09h - 0Eh)
    • 7.10.1 Channel Volume Control - Integer (CHXx_IVOL[7:0])
    • Table 8. Channel Integer Volume Settings
  • 7.11 Channel XX Volume Control1 - Fraction (address 11h)
  • 7.12 Channel XX Volume Control2 - Fraction (address 12h)
    • 7.12.1 Channel Volume Control - Fraction (CHXX_FVOL[1:0])
    • Table 9. Channel Fractional Volume Settings
  • 7.13 Channel Mute (address 13h)
    • 7.13.1 Independent Channel Mute (CHXX_MUTE)
  • 7.14 Channel Invert (address 14h)
    • 7.14.1 Invert Signal Polarity (CHXX_INV)
  • 7.15 Peak Limiter Control Register (address 15h)
    • 7.15.1 Peak Signal Limit All Channels (LIMIT_ALL)
    • 7.15.2 Peak Signal Limiter Enable (LIMIT_EN)
  • 7.16 Limiter Attack Rate (address 16h)
    • 7.16.1 Attack Rate (ARATE[7:0])
    • Table 10. Limiter Attack Rate Settings
  • 7.17 Limiter Release Rate (address 17h)
    • 7.17.1 Release Rate (RRATE[7:0])
    • Table 11. Limiter Release Rate Settings
  • 7.18 Chnl XX Load Compensation Filter - Coarse Adjust (addresses18h,1Ah,1Ch,1Eh,20h,22h)
    • 7.18.1 Channel Compensation Filter - Coarse Adjust (CHXX_CORS[5:0])
    • Table 12. Channel Load Compensation Filter Coarse Adjust
  • 7.19 Chnl XX Load Compensation Filter - Fine Adjust (addresses19h,1Bh,1Dh,1Fh,21h,23h)
    • 7.19.1 Channel Compensation Filter - Fine Adjust (CHXX_FINE[5:0])
    • Table 13. Channel Load Compensation Filter Fine Adjust
  • 7.20 Interrupt Mode Control (address 28h)
    • 7.20.1 Interrupt Pin Control (INT1/INT0)
    • 7.20.2 Overflow Level/Edge Select (OVFL_L/E)
  • 7.21 Interrupt Mask (address 29h)
  • 7.22 Interrupt Status (address 2Ah) (Read Only)
    • 7.22.1 SRC Unlock Interrupt (SRC_UNLOCK)
    • 7.22.2 SRC Lock Interrupt (SRC_LOCK)
    • 7.22.3 Ramp-Up Complete Interrupt (RMPUP_DONE)
    • 7.22.4 Ramp-Down Complete Interrupt (RMPDN_DONE)
    • 7.22.5 Mute Complete Interrupt (Mute_DONE)
    • 7.22.6 Channel Over Flow Interrupt (OVFL_INT)
    • 7.22.7 GPIO Interrupt Condition (GPIO_INT)
  • 7.23 Channel Over Flow Status (address 2Bh) (Read Only)
    • 7.23.1 ChXX_OVFL
  • 7.24 GPIO Pin In/Out (address 2Ch)
    • 7.24.1 GPIO In/Out Selection (GPIOX_I/O)
  • 7.25 GPIO Pin Polarity/Type (address 2Dh)
    • 7.25.1 GPIO Polarity/Type Selection (GPIOX_P/T)
  • 7.26 GPIO Pin Level/Edge Trigger (address 2Eh)
    • 7.26.1 GPIO Level/Edge Input Sensitive (GPIOX_L/E)
  • 7.27 GPIO Status Register (address 2Fh)
    • 7.27.1 GPIO Pin Status (GPIOX_STATUS)
  • 7.28 GPIO Interrupt Mask Register (address 30h)
    • 7.28.1 GPIO Pin Interrupt Mask (M_GPIOX)
  • 7.29 PWM Configuration Register (address 31h)
    • 7.29.1 Over Sample Rate Selection (OSRATE)
    • 7.29.2 Channels A1 and B1 Output Configuration (A1/B1_OUT_CNFG)
    • 7.29.3 Channels A2 and B2 Output Configuration (A2/B2_OUT_CNFG)
    • 7.29.4 Channel A3 Output Configuration (A3_OUT_CNFG)
    • 7.29.5 Channel B3 Output Configuration (B3_OUT_CNFG)
  • 7.30 PWM Minimum Pulse Width Register (address 32h)
    • 7.30.1 Disable PWMOUTXX - Signal (DISABLE_PWMOUTXX-)
    • 7.30.2 Minimum PWM Output Pulse Settings (MIN_PULSE[4:0])
    • Table 14. PWM Minimum Pulse Width Settings
  • 7.31 PWMOUT Delay Register (address 33h)
    • 7.31.1 Differential Signal Delay (DIFF_DLY[2:0])
    • Table 15. Differential Signal Delay Settings
    • 7.31.2 Channel Delay Settings (CHNL_DLY[4:0])
    • Table 16. Channel Delay Settings
    • Figure 31. PWM Output Delay
  • 7.32 PSR and Power Supply Configuration (address 34h)
    • 7.32.1 Power Supply Rejection Enable (PSR_EN)
    • 7.32.2 Power Supply Rejection Reset (PSR_RESET)
    • 7.32.3 Power Supply Rejection Feedback Enable (FEEDBACK_EN)
    • 7.32.4 Power Supply Sync Clock Divider Settings (PS_SYNC_DIV[2:0])
    • Table 17. Power Supply Sync Clock Divider Settings
  • 7.33 Decimator Shift/Scale (addresses35h,36h,37h)
    • 7.33.1 Decimator Shift (DEC_SHIFT[2:0])
    • 7.33.2 Decimator Scale (DEC_SCALE[18:0])
    • Table 18. Decimator Shift/Scale Coefficient Calculation Examples
  • 7.34 Decimator Outd (addresses3Bh,3Ch,3Dh)
    • 7.34.1 Decimator Outd (DEC_OUTD[23:0])
• 8. Parameter Definitions
• 9. References
• 10. Package Dimensions
  • Figure 32. 64-Pin LQFP Package Drawing
• 11. Thermal Characteristics
• 12. Revision History
  • Table 19. Revision History