Copyright
Cirrus Logic, Inc. 2005
(All Rights Reserved)
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
Low Voltage Class-D PWM Headphone Amplifier
Features
Up to 95 dB Dynamic Range
1.8 V to 2.4 V Analog and Digital Supplies
Sample Rates up to 96 kHz
Digital Tone Control
3 Selectable HPF and LPF Corner
Frequencies
12 dB Boost for Bass and Treble - 1 dB step
size
Programmable Digital Volume Control
+18 to -96 dB in 1 dB steps
Peak Signal Soft Limiting
De-emphasis for 32 kHz, 44.1 kHz, and 48 kHz
Selectable Outputs for Each Channel, including
Channel A: R, L, mono (L + R) / 2, mute
Channel B: R, L, mono (L + R) / 2, mute
PWM PopGuard
23 mW/Channel into 16
@ 2.4 V
Description
The CS44L11 is a complete stereo digital-to-PWM
Class-D audio amplifier system controller including in-
terpolation, volume control, and a headphone amplifier
in a 16-pin TSSOP package.
The CS44L11 architecture uses a direct-to-digital ap-
proach that maintains digital signal integrity to the final
output filter. This minimizes analog interference effects
that can negatively affect system performance.
The CS44L11 contains on-chip digital bass and treble
boost, peak signal limiting, and de-emphasis. The PWM
amplifier can achieve greater than 90% efficiency. This
efficiency leads to longer battery life for portable sys-
tems, smaller device package, less heat sink
requirements, and smaller power supplies.
The CS44L11 is ideal for portable audio, headphone
amplifiers, and mobile phones.
ORDERING INFORMATION
CS44L11-CZZ, Lead Free -10 to 70 C 16-pin TSSOP
Multibit
Modulator with
Correction
Multibit
Modulator with
Correction
Digital Volume
Control,
Bass/Treble
Boost,
Compression
Limiting,
De-emphasis
Control Port
SCL/DIF0
MCLK
Serial
Port
SDA/DEM
PWM
Conversion
PWM
Conversion
HP_B
VA_HPB
GND_HPB
Level
Shifter
VA_HPA
Level
Shifter
HP_A
GND_HPA
RST
Interpolation
SCLK
LRCK
Input Sampling Rate
LRCLK/MCLK Ratio
SDIN
Audio
VD
CS44L11
JULY '05
DS640PP4
2
DS640PP4
CS44L11
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 4
PERFORMANCE SPECIFICATIONS.................................................................................................... 5
SWITCHING CHARACTERISTICS ....................................................................................................... 8
SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT ............................................... 9
2. TYPICAL CONNECTION DIAGRAMS ................................................................................................ 10
3. REGISTER QUICK REFERENCE ................................................................................................... 12
4. REGISTER DESCRIPTIONS ............................................................................................................... 13
4.1 Power and Muting Control (address 02h) ..................................................................................... 13
4.1.1 Soft Ramp and Zero Cross Control (SZC) ....................................................................... 13
4.1.2 Power Down (PDN) ......................................................................................................... 13
4.1.3 Float Output (FLT) .......................................................................................................... 13
4.1.4 Ramp-Up Bypass (RUPBYP) ........................................................................................... 14
4.1.5 Ramp-Down Bypass (RDNBYP) ...................................................................................... 14
4.2 Channel A Volume Control (address 03h) (VOLA) ....................................................................... 14
4.3 Channel B Volume Control (address 04h) (VOLB) ....................................................................... 14
4.4 Tone Control (address 05h) .......................................................................................................... 15
4.4.1 Bass Boost Level (BB) ..................................................................................................... 15
4.4.2 Treble Boost Level (TB) ................................................................................................... 15
4.5 Mode Control 1 (address 06h) ...................................................................................................... 15
4.5.1 Bass Boost Corner Frequency (BBCF) ............................................................................ 16
4.5.2 Treble Boost Corner Frequency (TBCF) .......................................................................... 16
4.5.3 Tone Control Mode (TC) .................................................................................................. 17
4.5.4 Tone Control Enable (TC_EN) ........................................................................................ 17
4.5.5 Peak Signal Limiter Enable (LIM_EN) ............................................................................. 17
4.6 Limiter Attack Rate (address 07h) (ARATE) ................................................................................. 18
4.7 Limiter Release Rate (address 08h) (RRATE) ........................................................................ 18
4.8 Volume and Mixing Control (address 09h) ................................................................................... 19
4.8.1 Ramp Speed (RMP_SP) .................................................................................................. 19
4.8.2 ATAPI Channel Mixing and Muting (ATAPI) .................................................................... 19
4.9 Mode Control 2 (address 0Ah) ..................................................................................................... 20
4.9.1 Master Clock Divide Enable (MCLKDIV) ......................................................................... 20
4.9.2 Clock Divide (CLKDIV) ..................................................................................................... 20
4.9.3 Double-Speed Mode (DBS) ............................................................................................. 21
4.9.4 Frequency Shift (FRQSFT) .............................................................................................. 21
4.9.5 De-Emphasis Control (DEM) .......................................................................................... 22
4.10 Mode Control 3 (address 0Bh) ................................................................................................... 23
4.10.1 Digital Interface Formats (DIF) ....................................................................................... 23
4.10.2 Channel A Volume = Channel B Volume (A=B) ............................................................. 23
4.10.3 Volume Control Bypass (VCBYP) .................................................................................. 23
4.10.4 Control Port Enable (CP_EN) ........................................................................................ 23
4.10.5 Freeze (FREEZE) .......................................................................................................... 24
4.11 Revision Indicator (address 0Ch)[Read Only] ........................................................................... 24
5. PIN DESCRIPTION .............................................................................................................................. 25
6. APPLICATIONS ................................................................................................................................. 26
6.1 Grounding and Power Supply Decoupling .................................................................................... 26
6.2 Clock Modes ................................................................................................................................. 26
6.3 De-Emphasis ................................................................................................................................ 26
6.4 PWM PopGuard Transient Control ............................................................................................... 26
6.5 Recommended Power-Up Sequence ........................................................................................... 27
6.5.1 Stand-Alone Mode ........................................................................................................... 27
6.5.2 Control Port Mode ............................................................................................................ 27
7. CONTROL PORT INTERFACE ........................................................................................................... 28
DS640PP4
3
CS44L11
7.1 IC Format .................................................................................................................................... 28
7.1.1 Writing in IC Format ........................................................................................................ 28
7.1.2 Reading in IC Format ...................................................................................................... 28
7.2 Memory Address Pointer (MAP) ................................................................................................. 28
7.2.1 INCR (Auto Map Increment Enable) ................................................................................ 28
7.2.2 MAP3-0 (Memory Address Pointer) ................................................................................. 29
8. PARAMETER DEFINITIONS ............................................................................................................... 32
9. REFERENCES ..................................................................................................................................... 32
10. PACKAGE DIMENSIONS ................................................................................................................. 33
11. REVISION HISTORY ......................................................................................................................... 34
LIST OF FIGURES
Figure 1. Serial Audio Data Interface Timing ............................................................................................... 8
Figure 2. Control Port Timing - IC Format................................................................................................... 9
Figure 3. Typical CS44L11 Connection Diagram Stand-Alone Mode ........................................................ 10
Figure 4. Typical CS44L11 Connection Diagram Control Port Mode......................................................... 11
Figure 5. Dynamics Control Block Diagram ............................................................................................... 20
Figure 6. De-Emphasis Curve.................................................................................................................... 22
Figure 7. Control Port Timing, IC Format.................................................................................................. 29
Figure 8. Single-Speed Stopband Rejection .............................................................................................. 29
Figure 9. Single-Speed Transition Band .................................................................................................... 29
Figure 10. Single-Speed Transition Band (Detail)...................................................................................... 29
Figure 11. Single-Speed Passband Ripple ................................................................................................ 29
Figure 12. Double-Speed Stopband Rejection........................................................................................... 30
Figure 13. Double-Speed Transition Band................................................................................................. 30
Figure 14. Double-Speed Transition Band (Detail) .................................................................................... 30
Figure 15. Double-Speed Passband Ripple............................................................................................... 30
Figure 16. Left-Justified, up to 24-Bit Data................................................................................................. 31
Figure 17. Right-Justified, 24-Bit Data ....................................................................................................... 31
Figure 18. IS, Up to 24-Bit Data................................................................................................................ 31
Figure 19. Right-Justified, 16-Bit Data ....................................................................................................... 31
LIST OF TABLES
Table 1. Register Quick Reference ............................................................................................................ 12
Table 2. Example Volume Settings ............................................................................................................ 14
Table 3. Example Bass Boost Settings ...................................................................................................... 15
Table 4. Example Treble Boost Settings.................................................................................................... 15
Table 5. Base Boost Corner Frequencies in Single-Speed Mode.............................................................. 16
Table 6. Base Boost Corner Frequencies in Double-Speed Mode ............................................................ 16
Table 7. Treble Boost Corner Frequencies in Single-Speed Mode............................................................ 16
Table 8. Example Limiter Attack Rate Settings.......................................................................................... 18
Table 9. Example Limiter Release Rate Settings....................................................................................... 18
Table 10. ATAPI Decode ........................................................................................................................... 19
Table 11. Single-Speed Clock Modes - Control Port Mode ....................................................................... 21
Table 12. Single-Speed Clock Modes - Stand-Alone Mode....................................................................... 21
Table 13. Double-Speed Clock Modes - Control Port Mode ...................................................................... 22
Table 14. Digital Interface Format (Stand-Alone Mode)............................................................................. 25
Table 15. Revision History ......................................................................................................................... 34
4
DS640PP4
CS44L11
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per-
formance characteristics and specifications are derived from measurements taken at nominal supply voltages and
TA = 25C.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V)
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the
device. Normal operation is not guaranteed at these extremes.)
Parameters
Symbol Min Typ
Max
Units
DC Power Supplies:
Headphone
Digital
VA_HPx
VD
1.7
1.7
-
-
2.5
2.5
V
V
Ambient Temperature
T
A
-10
-
70
C
Parameters
Symbol
Min
Max
Units
DC Power Supplies:
Headphone
Digital
VA_HPx
VD
-0.3
-0.3
3.0
3.0
V
V
Input Current, Any Pin Except Supplies
I
in
10
mA
Digital Input Voltage
V
IND
-0.3
VD + 0.4
V
Ambient Operating Temperature (power applied)
T
A
-55
125
C
Storage Temperature
T
stg
-65
150
C
DS640PP4
5
CS44L11
PERFORMANCE SPECIFICATIONS
(Full-Scale Output Sine Wave, 997 Hz, MCLK = 12.288 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless
otherwise specified; Fs for Single-Speed Mode = 48 kHz, SCLK = 3.072 MHz; Fs for Double-Speed Mode =
96 kHz, SCLK = 6.144 MHz. Test load RL= 16
, CL = 10 pF. Performance results are measured in production
using a 4700
F capacitor on the VA_HPx pins. Results will be degraded if smaller value capacitors are used.)
Parameter
Symbol
Min
Typ
Max
Unit
Headphone Output Dynamic Performance for VD = VA_HPx = 2.4 V
Dynamic Range
18 to 24-Bit
A-Weighted
UnWeighted
16-Bit
A-Weighted
Unweighted
90
88
88
86
95
93
93
91
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
0 dBFS
-20 dBFS
-60 dBFS
THD+N
-
-
-
-60
-73
-33
-55
-
-
dB
dB
dB
Interchannel Isolation
(1 kHz)
-
TBD
-
dB
Headphone Output Dynamic Performance for VD = VA_HPx = 1.8 V
Dynamic Range
18 to 24-Bit
A-Weighted
UnWeighted
16-Bit
A-Weighted
Unweighted
87
85
85
83
92
90
90
88
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
0 dB
-20 dB
-60 dB
THD+N
-
-
-
-55
-70
-30
-50
-
-
dB
dB
dB
Interchannel Isolation
(1 kHz)
-
60
-
dB
PWM Headphone Output
Full-Scale Headphone Output Voltage
-
0.75 x
VA_HP
-
Vpp
Headphone Output Quiescent Voltage
-
0.5 x
VA_HP
-
VDC
Interchannel Gain Mismatch
-
0.1
-
dB
Modulation Index
-
-
85
%
Maximum Headphone Output
VA_HPx=2.4 V
RMS AC-Current
VA_HPx=1.8 V
I
HP
-
-
38
28
-
-
mA
mA
Parameter
Single-Speed Mode
Double-Speed Mode
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Digital Filter Response
(Note 1)
)
Passband
to -0.05 dB corner
(Note 2)
to -0.1 dB corner
to -3 dB corner
0
-
0
-
-
-
.4535
-
.4998
-
0
0
-
-
-
-
.4426
.4984
Fs
Fs
Fs
Frequency Response 10 Hz to 20 kHz
(Note 3)
-.02
-
+.08
0
-
+0.11
dB
StopBand
.5465
-
-
.577
-
-
Fs
StopBand Attenuation
(Note 4)
50
-
-
55
-
-
dB
Group Delay
tgd
-
9/Fs
-
-
4/Fs
-
s
6
DS640PP4
CS44L11
Notes:
1. Filter response is not tested but is guaranteed by design.
2. Response is clock-dependent and will scale with Fs. Note that the response plots (
Figures 8
-
15
) have been
normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
3. Referenced to a 1 kHz, full-scale sine wave.
4. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.
5. De-emphasis is not available in Double-Speed Mode.
Passband Group Delay Deviation
0 - 40 kHz
0 - 20 kHz
-
-
-
0.36/Fs
-
-
-
-
1.39/Fs
0.23/Fs
-
-
s
s
De-emphasis Error
Fs = 32 kHz
(Relative to 1 kHz)
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
+.2/-.1
+.05/-.14
+0/-.22
(Note 5)
dB
dB
dB
Parameter
Single-Speed Mode
Double-Speed Mode
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
DS640PP4
7
CS44L11
DIGITAL CHARACTERISTICS
(GND = 0 V; all voltages with respect to 0 V.)
POWER AND THERMAL CHARACTERISTICS
(GND = 0 V; all voltages with respect to 0 V. HP_x outputs unloaded.)
Notes:
6. Power Down Mode is defined as RST = LOW with all clocks and data lines held static.
7. Normal operation is defined as RST = HI.
Parameters
Symbol
Min Typ
Max
Units
High-Level Input Voltage
V
IH
0.7 x VD
-
-
V
Low-Level Input Voltage
V
IL
-
-
0.3 x VD
V
Input Leakage Current
I
in
-
-
10
A
Input Capacitance
-
8
-
pF
Parameters
Symbol
Min
Typ
Max
Units
Power Down
(Note 6)
Power Supply Current
VD = VA_HPx = 2.4 V
VD = VA_HPx = 1.8 V
-
-
380
110
-
-
A
A
Normal Operation
(Note 7)
Power Supply Current
VD = VA_HPx = 2.4 V
VD = VA_HPx = 1.8 V
-
-
14
9
-
-
mA
mA
Total Power Dissipation-
VD = VA_HPx = 2.4 V
Normal Operation
(Note 6)
VD = VA_HPx = 1.8 V
-
-
34
16
-
-
mW
mW
Maximum Headphone Power Output
(1 kHz full-scale sine wave
VA_HPx = 2.4 V
into 16
load)
VA_HPx = 1.8 V
-
-
23
13
-
-
mW
mW
Power Supply Rejection Ratio
PSRR
-
0
-
dB
Package Thermal Resistance
JA
-
75
-
C/Watt
8
DS640PP4
CS44L11
SWITCHING CHARACTERISTICS
(GND = 0 V; all voltages with respect to 0 V.)
Parameters
Symbol Min Typ
Max
Units
Input Sample Rate
Single-Speed Mode
Double-Speed Mode
Fs
Fs
8
50
-
-
50
100
kHz
kHz
MCLK Duty Cycle
40
50
60
%
LRCK Duty Cycle
40
50
60
%
SCLK Pulse Width Low
t
sclkl
20
-
-
ns
SCLK Pulse Width High
t
sclkh
20
-
-
ns
SCLK Period
Single-Speed Mode
t
sclkw
-
-
ns
Double-Speed Mode
t
sclkw
-
-
ns
SCLK rising to LRCK edge delay
t
slrd
20
-
-
ns
SCLK rising to LRCK edge setup time
t
slrs
20
-
-
ns
SDIN valid to SCLK rising setup time
t
sdlrs
20
-
-
ns
SCLK rising to SDIN hold time
t
sdh
20
-
-
ns
1
128
(
)
Fs
----------------------
1
64
( )
Fs
-------------------
sclkh
t
slrs
t
slrd
t
sdlrs
t
sdh
t
sclkl
t
SDIN
SCLK
LRCK
sclkw
t
Figure 1. Serial Audio Data Interface Timing
DS640PP4
9
CS44L11
SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT
(GND = 0 V; all voltages with respect to 0 V.)
Notes:
8. Data must be held for sufficient time to bridge the transition time, t
fc
, of SCL.
9. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
10.
for Single-Speed Mode and
for Double-Speed Mode.
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
f
scl
-
100
kHz
RST Rising Edge to Start
t
irs
500
-
ns
Bus Free Time Between Transmissions
t
buf
4.7
-
s
Start Condition Hold Time (prior to first clock pulse)
t
hdst
4.0
-
s
Clock Low time
t
low
4.7
-
s
Clock High Time
t
high
4.0
-
s
Setup Time for Repeated Start Condition
t
sust
4.7
-
s
SDA Hold Time from SCL Falling
(Note 8)
t
hdd
0
-
s
SDA Setup time to SCL Rising
t
sud
250
-
ns
Rise Time of SCL and SDA
t
rc
, t
rc
-
1
s
Fall Time SCL and SDA
t
fc
, t
fc
-
300
ns
Setup Time for Stop Condition
t
susp
4.7
-
s
Acknowledge Delay from SCL Falling
(Note 9)
t
ack
-
(Note 10)
ns
5
256 Fs
---------------------
5
128 Fs
---------------------
t buf
t hdst
t
lo w
t
hdd
t high
t sud
Stop
Start
S D A
S C L
t irs
R S T
t
hdst
t rc
t fc
t sust
t susp
Start
Stop
R epe ate d
t rd
t fd
t ack
Figure 2. Control Port Timing - IC Format
10
DS640PP4
CS44L11
2. TYPICAL CONNECTION DIAGRAMS
RST
VA_HPB
1.8 to 2.4 V
Supply
100F
+
VA_HPA
VD
12
13
7
6
Supply
+
1.8 to 2.4 V
10
15
GND
GND
GND
Digital
Audio
Source
DIF0
DEM
Mode
Control
11
14
0.22
F
0.22
F
HP_A
HP_B
100 H
100 H
220 F
220 F
+
+
16
Headphones
Low ESR
Tantalum
1.0F
0.1F
5
4
3
2
1
MCLK
SCLK
LRCK
SDIN
1.0F
0.1F
9
16
8
VD
Figure 3. Typical CS44L11 Connection Diagram Stand-Alone Mode
CS44L11
* Filter component values shown are for a 16
load. Please see the CDB44L11 datasheet for information
on how to calculate filter values for other loads.
DS640PP4
11
CS44L11
VA_H PB
.8 to 2.4 V
Supply
100F
+
VA_HPA
VD
12
13
7
6
Supply
+
1.8 to 2.4 V
10
15
GND
GND
GND
Digital
Audio
Source
Control
Logic
11
14
0.22
F
0.22
F
HP_A
HP_B
100 H
100 H
220 F
220 F
+
+
16
Headphones
Low ESR
Tantalum
1.0F
0.1F
5
4
3
2
1
MCLK
SCLK
LRCK
SDIN
1.0F
0.1F
8
SCL
RST
16
SDA
9
Supply
1.8 to 2.4 V
Rpullup
VD
Figure 4. Typical CS44L11 Connection Diagram Control Port Mode
CS44L11
* Filter component values shown are for a 16
load. Please see the CDB44L11 datasheet for infor-
mation on how to calculate filter values for other loads.
12
DS640PP4
CS44L11
3. REGISTER QUICK REFERENCE
Addr
Function
7
6
5
4
3
2
1
0
2h
Power and Muting
Control
SZC1
SZC0
PDN
FLT
RUPBYP RDNBYP Reserved Reserved
default
1
0
1
0
0
0
0
0
3h
Channel A
Volume Control
VOLA7
VOLA6
VOLA5
VOLA4
VOLA3
VOLA2
VOLA1
VOLA0
default
0
0
0
0
0
0
0
0
4h
Channel B
Volume Control
VOLB7
VOLB6
VOLB5
VOLB4
VOLB3
VOLB2
VOLB1
VOLB0
default
0
0
0
0
0
0
0
0
5h
Tone Control
BB3
BB2
BB1
BB0
TB3
TB2
TB1
TB0
default
0
0
0
0
0
0
0
0
6h
Mode Control 1
BBCF1
BBCF0
TBCF1
TBCF0
TC1
TC0
TC_EN
LIM_EN
default
0
0
0
0
0
0
0
0
7h
Limiter Attack Rate
ARATE7 ARATE6 ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0
default
0
0
0
1
0
0
0
0
8h
Limiter Release Rate
RRATE7 RRATE6 RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0
default
0
0
1
0
0
0
0
0
9h
Volume and Mixing
Control
Reserved Reserved RMP_SP
1
RMP_SP
0
ATAPI3
ATAPI2
ATAPI1
ATAPI0
default
0
0
0
1
1
0
0
1
Ah
Mode Control2
mclkdiv
CLKDV1 CLKDV0
DBS
FRQSFT
1
FRQSFT
0
DEM1
DEM0
default
0
0
0
0
0
0
0
0
Bh
Mode Control 3
DIF1
DIF0
A=B
VCBYP
CP_EN
FREEZE Reserved Reserved
default
0
0
0
0
0
0
0
0
Ch
Revision Indicator
Reserved Reserved Reserved Reserved
REV3
REV2
REV1
REV0
default
0
0
0
0
Read
Only
Read
Only
Read
Only
Read
Only
Table 1. Register Quick Reference
DS640PP4
13
CS44L11
4. REGISTER DESCRIPTIONS
4.1
Power and Muting Control (address 02h)
4.1.1
Soft Ramp and Zero Cross Control (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross Control
10 - Ramped Control
11 - Reserved
Function:
Immediate Change
When Immediate Change is selected, all level changes will take effect immediately in one step.
Zero Cross Control
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a
time-out period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a
zero crossing. The zero cross function is independently monitored and implemented for each channel.
Ramped Control
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Note:
Ramped Control is not available in Double-Speed Mode.
4.1.2
Power Down (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to `enabled' on power-up and must be
disabled before normal operation in Control Port Mode can occur.
4.1.3
Float Output (FLT)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, this bit will cause the headphone output of the CS44L11 to float when in the power down
state (PDN=1). The float function can be used in single-ended applications to maintain the charge on the
7
6
5
4
3
2
1
0
SZC1
SZC0
PDN
FLT
RUPBYP
RDNBYP
Reserved
Reserved
1
0
1
0
0
0
0
0
14
DS640PP4
CS44L11
DC-blocking capacitor during power transients. On power transitions, the output will quickly change to the
bias point; however, if the DC-blocking capacitor still has a full charge, as in short power cycles, the tran-
sition will be very small, often inaudible. Refer to
Section 6.4.
4.1.4
Ramp-Up Bypass (RUPBYP)
Default = 0
0 - Normal
1 - Bypass
Function:
When in normal mode, the duty cycle of the output PWM signal is increased at a rate determined by the
Ramp Speed variable (RMP_SPx). Normal mode is used in Single-Ended applications to reduce pops in
the output caused by the DC-blocking capacitor. When the ramp-up function is bypassed in Single-Ended
applications, there will be an abrupt change in the output signal. Refer to
Section 6.4
.
4.1.5
Ramp-Down Bypass (RDNBYP)
Default = 0
0 - Disabled
1 - Enabled
Function:
When in normal mode, the duty cycle of the output PWM signal is decreased at a rate determined by the
Ramp Speed variable (RMP_SPx). Normal mode is used in Single-Ended applications to reduce pops in
the output caused by the DC-blocking capacitor and changes in bias conditions. When the ramp-down
function is bypassed in Single-Ended applications, there will be an abrupt change in the output signal.
Refer to
Section 6.4
.
4.2
Channel A Volume Control (address 03h) (VOLA)
4.3
Channel B Volume Control (address 04h) (VOLB)
Default = 0 dB (No attenuation)
Function:
The Volume Control registers allow independent control of the signal levels in 1 dB increments from +18 to
-96 dB. Volume settings are decoded using a 2's complement code, as shown in
Table 2
. The volume
changes are implemented as dictated by the Soft and Zero Cross bits. All volume settings less than -96 dB
are equivalent to muting the channel via the ATAPI bits (see
Section 4.8.2
).
Note:
All volume settings greater than +18 dB are interpreted as +18 dB.
7
6
5
4
3
2
1
0
VOLx7
VOLx6
VOLx5
VOLx4
VOLx3
VOLx2
VOLx1
VOLx0
0
0
0
0
0
0
0
0
Binary Code
Decimal Value
Volume Setting
00001100
12
+12 dB
00000111
7
+7 dB
00000000
0
0 dB
11000100
-60
-60 dB
10100110
-90
-90 dB
Table 2. Example Volume Settings
DS640PP4
15
CS44L11
4.4
Tone Control (address 05h)
4.4.1
Bass Boost Level (BB)
Default = 0 dB (No Bass Boost)
Function:
The level of the shelving Bass Boost filter is set by Bass Boost Level. The level can be adjusted in 1 dB
increments from 0 to +12 dB of boost. Boost levels are decoded as shown in
Table 3
. Levels above
+12 dB are interpreted as +12 dB.
4.4.2
Treble Boost Level (TB)
Default = 0 dB (No Treble Boost)
Function:
The level of the shelving Treble Boost filter is set by Treble Boost Level. The level can be adjusted in 1 dB
increments from 0 to +12 dB of boost. Boost levels are decoded as shown in
Table 4
. Levels above
+12 dB are interpreted as +12 dB.
Note:
Treble Boost is not available in Double-Speed Mode.
4.5
Mode Control 1 (address 06h)
7
6
5
4
3
2
1
0
BB3
BB2
BB1
BB0
TB3
TB2
TB1
TB0
0
0
0
0
0
0
0
0
Binary Code
Decimal Value
Boost Setting
0000 0000
0
0 dB
0000 0010
2
+2 dB
0000 0110
6
+6 dB
0000 1001
9
+9 dB
0000 1100
12
+12 dB
Table 3. Example Bass Boost Settings
Binary Code
Decimal Value
Boost Setting
0000 0000
0
0 dB
0000 0010
2
+2 dB
0000 0110
6
+6 dB
0000 1001
9
+9 dB
0000 1100
12
+12 dB
Table 4. Example Treble Boost Settings
7
6
5
4
3
2
1
0
BBCF1
BBCF0
TBCF1
TBCF0
TC1
TC0
TC_EN
LIM_EN
0
0
0
0
0
0
0
0
16
DS640PP4
CS44L11
4.5.1
Bass Boost Corner Frequency (BBCF)
Default = 00
00 - 50 Hz
01 - 100 Hz
10 - 200 Hz
11 - Reserved
Function:
The Bass Boost corner frequency is user-selectable. The corner frequency is a function of LRCK (sam-
pling frequency), the DBS bit and the BBCF bits as shown in
Table 5
and
Table 6
.
4.5.2
Treble Boost Corner Frequency (TBCF)
Default = 00
00 - 2 kHz
01 - 4 kHz
10 - 7 kHz
11 - Reserved
Function:
The Treble Boost corner frequency is user selectable. The corner frequency is a function of LRCK (sam-
pling frequency) and the TBCF bits as shown in
Table 7
.
Note:
Treble Boost is not available in Double-Speed Mode.
BBCF
Fs
LRCK in Single-Speed Mode (DBS=0)
48 kHz
24 kHz
12 kHz
8 kHz
00
50 Hz
25 Hz
12.5 Hz
8.33 Hz
01
100 Hz
50 Hz
25 Hz
16.7 Hz
10
200 Hz
100 Hz
50 Hz
33.3 Hz
11
Reserved
Reserved
Reserved
Reserved
Table 5. Base Boost Corner Frequencies in Single-Speed Mode
BBCF
Fs
LRCK in Double-Speed Mode (DBS=1)
96 kHz
48 kHz
24 kHz
16 kHz
00
50 Hz
25 Hz
12.5 Hz
8.33 Hz
01
100 Hz
50 Hz
25 Hz
16.7 Hz
10
200 Hz
100 Hz
50 Hz
33.3 Hz
11
Reserved
Reserved
Reserved
Reserved
Table 6. Base Boost Corner Frequencies in Double-Speed Mode
TBCF
Fs
LRCK in Single-Speed Mode (DBS=0)
48 kHz
24 kHz
12 kHz
8 kHz
00
2 kHz
1 kHz
0.5 kHz
0.33 kHz
01
4 kHz
2 kHz
1 kHz
0.67 kHz
10
7 kHz
3.5 kHz
1.75 kHz
1.17 kHz
11
Reserved
Reserved
Reserved
Reserved
Table 7. Treble Boost Corner Frequencies in Single-Speed Mode
DS640PP4
17
CS44L11
4.5.3
Tone Control Mode (TC)
Default = 00
00 - All settings are taken from user registers
01 - 12 dB of Bass Boost at 100 Hz and 6 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)
10 - 8 dB of Bass Boost at 100 Hz and 4 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)
11 - 4 dB of Bass Boost at 100 Hz and 2 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)
Function:
The Tone Control Mode bits determine how the Bass Boost and Treble Boost features are configured.
The user-defined settings from the Bass and Treble Boost Level and Corner Frequency registers are used
when these bits are set to `00'. Alternately, one of three pre-defined settings may be used (these settings
are a function of LRCK - refer to
Tables 5
,
6
, and
7
).
Note:
Treble Boost is not available in Double-Speed Mode.
4.5.4
Tone Control Enable (TC_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Bass Boost and Treble Boost features are active when this function is enabled.
4.5.5
Peak Signal Limiter Enable (LIM_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The CS44L11 will limit the maximum signal amplitude to prevent clipping when this function is enabled.
Peak Signal Limiting is performed by first decreasing the Bass and Treble Boost Levels. If the signal is
still clipping, the digital attenuation is increased. The attack rate is determined by the Limiter Attack Rate
register.
Once the signal has dropped below the clipping level, the attenuation is decreased back to the user-se-
lected level, followed by the Bass Boost being increased back to the user-selected level. The release rate
is determined by the Limiter Release Rate register.
Note:
The A=B bit should be set to `1' for optimal limiter performance.
18
DS640PP4
CS44L11
4.6
Limiter Attack Rate (address 07h) (ARATE)
Default = 10h - 2 LRCK's per 1/8 dB
Function:
The limiter attack rate is user-selectable. The rate is a function of sampling frequency, Fs, and the value in
the Limiter Attack Rate register. Rates are calculated using the function RATE = 32/{value}, where {value}
is the decimal value in the Limiter Attack Rate register and RATE is in LRCK's per 1/8 dB of change.
A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter. Use the
LIM_EN bit to disable the limiter function (see
"Peak Signal Limiter Enable (LIM_EN)"
).
4.7
Limiter Release Rate (address 08h) (RRATE)
Default = 20h - 16 LRCK's per 1/8 dB
Function:
The limiter release rate is user-selectable. The rate is a function of sampling frequency, Fs, and the value
in the Limiter Release Rate register. Rates are calculated using the function RATE = 512/{value}, where
{value} is the decimal value in the Limiter Release Rate register and RATE is in LRCK's per 1/8 dB of
change.
Note:
A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.
Use the LIM_EN bit to disable the limiter function (see
"Peak Signal Limiter Enable (LIM_EN)"
).
7
6
5
4
3
2
1
0
ARATE7
ARATE6
ARATE5
ARATE4
ARATE3
ARATE2
ARATE1
ARATE0
0
0
0
1
0
0
0
0
Binary Code
Decimal Value
LRCK's per 1/8 dB
00000001
1
32
00010100
20
1.6
00101000
40
0.8
00111100
60
0.53
01011010
90
0.356
Table 8. Example Limiter Attack Rate Settings
7
6
5
4
3
2
1
0
RRATE7
RRATE6
RRATE5
RRATE4
RRATE3
RRATE2
RRATE1
RRATE0
0
0
1
0
0
0
0
0
Binary Code
Decimal Value
LRCK's per 1/8 dB
00000001
1
512
00010100
20
25
00101000
40
12
00111100
60
8
01011010
90
5
Table 9. Example Limiter Release Rate Settings
DS640PP4
19
CS44L11
4.8
Volume and Mixing Control (address 09h)
4.8.1
Ramp Speed (RMP_SP)
Default = 01
00 - Ramp speed = approximately 0.1 seconds
01 - Ramp speed = approximately 0.2 seconds
10 - Ramp speed = approximately 0.3 seconds
11 - Ramp speed = approximately 0.65 seconds
Function:
This feature is used in Single-Ended applications to reduce pops in the output caused by the DC-blocking
capacitor. When in Control Port Mode, the Ramp Speed sets the time for the PWM signal to linearly ramp
up and down from the bias point (50% PWM duty cycle). Refer to
Section 6.4
.
4.8.2
ATAPI Channel Mixing and Muting (ATAPI)
Default = 1001 - HP_A = L, HP_B = R (Stereo)
Function:
The CS44L11 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to
Table 10
and
Figure 5
for additional information.
Note:
All mixing functions occur prior to the digital volume control.
7
6
5
4
3
2
1
0
Reserved
Reserved
RMP_SP1
RMP_SP0
ATAPI3
ATAPI2
ATAPI1
ATAPI0
0
0
0
0
1
0
0
1
ATAPI3
ATAPI2
ATAPI1
ATAPI0
HP_A
HP_B
0
0
0
0
MUTE
MUTE
0
0
0
1
MUTE
R
0
0
1
0
MUTE
L
0
0
1
1
MUTE
[(L+R)/2]
0
1
0
0
R
MUTE
0
1
0
1
R
R
0
1
1
0
R
L
0
1
1
1
R
[(L+R)/2]
1
0
0
0
L
MUTE
1
0
0
1
L
R
1
0
1
0
L
L
1
0
1
1
L
[(L+R)/2]
1
1
0
0
[(L+R)/2]
MUTE
1
1
0
1
[(L+R)/2]
R
1
1
1
0
[(L+R)/2]
L
1
1
1
1
[(L+R)/2]
[(L+R)/2]
Table 10. ATAPI Decode
20
DS640PP4
CS44L11
4.9
Mode Control 2 (address 0Ah)
4.9.1
Master Clock Divide Enable (MCLKDIV)
Default = 0
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other
internal circuitry. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user's MCLK and LRCK require-
ments. Refer to
Tables 11
,
12
,
13
, and
Section 6.2
.
4.9.2
Clock Divide (CLKDIV)
Default = 00
Function:
MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user's MCLK and LRCK requirements. Refer to
Tables 11
,
12
,
13
, and
Section 6.2.
7
6
5
4
3
2
1
0
mclkdiv
CLKDV1
CLKDV0
DBS
FRQSFT1
FRQSFT0
DEM1
DEM0
0
0
0
0
0
0
0
0
HP_A
HP_B
Left Channel
Audio Data
Right Channel
Audio Data
Channel B
Digital
Volume
Control
EQ
Channel A
Digital
Volume
Control
EQ
& Mute
& Mute
Figure 5. Dynamics Control Block Diagram
DS640PP4
21
CS44L11
4.9.3
Double-Speed Mode (DBS)
Default = 0
0 - Single-Speed
1 - Double-Speed (DBS)
Function:
Single-Speed supports 8 kHz to 50 kHz sample rates and Double-Speed supports 50 kHz to 96 kHz sam-
ple rates. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user's MCLK and LRCK requirements.
Refer to
Tables 11
,
12
,
13
, and
Section 6.2
.
Note:
De-emphasis, ramp control, and treble control are not available in Double-Speed Mode.
4.9.4
Frequency Shift (FRQSFT)
Default = 00
Function:
MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user's MCLK and LRCK requirements. Refer to
Tables 11
,
12
,
13
, and
Section 6.2
.
DBS = 0
MCLKDIV = 0
DBS = 0
MCLKDIV = 1
LRCK
(kHz)
MCLK/
LRCK
MCLK
(MHz)
MCLK/
LRCK
MCLK
(MHz)
FRQSFT1 FRQSFT0 CLKDIV1 CLKDIV0
PWM
Switching
Freq.
(kHz)
48
256
12.288
512
24.576
0
0
0
0
384
48
512
24.576
1024
49.152
0
0
1
0
44.1
256
11.2896
512
22.5792
0
0
0
0
352.8
44.1
512
22.5792
1024
45.1584
0
0
1
0
32
512
16.384
1024
32.768
0
1
0
0
512
32
1024
32.768
2048
65.536
0
1
1
0
24
512
12.288
1024
24.576
0
1
0
0
384
24
1024
24.576
2048
49.152
0
1
1
0
12
1024
12.288
2048
24.576
1
0
0
0
384
12
2048
24.576
4096
49.152
1
0
1
0
Table 11. Single-Speed Clock Modes - Control Port Mode
LRCK
(kHz)
MCLK/
LRCK
MCLK
(MHz)
PWM
Switching
Freq. (kHz)
48
256
12.288
384
48
512
24.576
44.1
256
11.2896
352.8
44.1
512
22.5792
32
1024
32.768
512
24
1024
24.576
384
12
2048
24.576
Table 12. Single-Speed Clock Modes - Stand-Alone Mode
22
DS640PP4
CS44L11
4.9.5
De-Emphasis Control (DEM)
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Selects the appropriate digital filter to maintain the standard 15
s/50
s digital de-emphasis filter re-
sponse at 32, 44.1 or 48 kHz sample rates (see
Figure 6
).
Note:
De-emphasis is not available in Double-Speed Mode.
DBS = 1
MCLKDIV = 0
DBS = 1
MCLKDIV = 1
LRCK
(kHz)
MCLK/
LRCK
MCLK
(MHz)
MCLK/
LRCK
MCLK
(MHz)
FRQSFT1 FRQSFT0 CLKDIV1 CLKDIV0
PWM
Switching
Freq.
(kHz)
96
128
12.288
256
24.576
0
0
0
0
384
96
256
24.576
512
49.152
0
0
1
0
88.2
128
11.2896
256
22.5792
0
0
0
0
352.8
88.2
256
22.5792
512
45.1584
0
0
1
0
Table 13. Double-Speed Clock Modes - Control Port Mode
Gain
dB
-10dB
0dB
Frequency
T2 = 15 s
T1=50 s
F1
F2
3.183 kHz
10.61 kHz
Figure 6. De-Emphasis Curve
DS640PP4
23
CS44L11
4.10 Mode Control 3 (address 0Bh)
4.10.1 Digital Interface Formats (DIF)
Default = 00
00 - IS
01 - Right Justified, 16 bit
10 - Left Justified
11 - Right Justified, 24 bit
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in
Figures 16
through
19
.
4.10.2 Channel A Volume = Channel B Volume (A=B)
Default = 0
0 - Disabled
1 - Enabled
Function:
The HP_A and HP_B volume levels are independently controlled by the A and the B Channel Volume
Control Bytes when this function is disabled. The volume on both HP_A and HP_B are determined by the
A Channel Volume Control Byte and the B Channel Byte is ignored when this function is enabled.
4.10.3 Volume Control Bypass (VCBYP)
Default = 0
0 - Disabled
1 - Enabled
Function:
The digital volume control section is bypassed when this function is enabled. This disables the digital vol-
ume control, muting, bass boost, treble boost, limiting, and ATAPI functions.
4.10.4 Control Port Enable (CP_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control Port Mode can
be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the reg-
isters and the pin definitions will conform to Control Port Mode. Refer to
Section 6.5.2
.
7
6
5
4
3
2
1
0
DIF1
DIF0
A=B
VCBYP
CP_EN
FREEZE
HPSEN
Reserved
0
0
0
0
0
0
0
0
24
DS640PP4
CS44L11
4.10.5 Freeze (FREEZE)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes being taking effect until
the FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneous-
ly, you will first enable the FREEZE Bit, then make all register changes, then Disable the FREEZE bit.
4.11 Revision Indicator (address 0Ch)[Read Only]
Default = none
0001 - Revision A
0010 - Revision B
0011 - Revision C
etc.
Function:
This read-only register indicates the revision level of the device.
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
REV3
REV2
REV1
REV0
0
0
0
0
0
0
0
0
DS640PP4
25
CS44L11
5. PIN DESCRIPTION
SDIN
1
Serial Audio Data Input (Input) - Input for two's complement serial audio data.
LRCK
2
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial
audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
SCLK
3
Serial Clock (Input) - Serial clock for the serial audio interface.
MCLK
4
Master Clock (Input) - Clock source for the PWM modulator and digital filters.
Tables 11
,
12
,
13
and
14
illustrate several standard audio sample rates and required master clock frequencies.
VD
5
7
Digital Power (Input) - Positive power supply for the digital section. Refer to
"Specified Operating
Conditions"
for appropriate voltages.
GND
6, 10
& 15
Ground (Input) - Ground Reference.
HP_A
HP_B
11
14
Headphone Outputs (Output) - PWM Headphone Outputs. An external LC filter should be added to
suppress high frequency switching noise. A DC blocking capacitor is also required. Refer to Typical
Connection Diagrams.
VA_HPA
VA_HPB
12
13
Headphone Amplifier Power (Input) - Positive power supply for the headphone amplifier. Refer to
"Specified Operating Conditions"
for appropriate voltages.
RST
16
Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low. The control port cannot be accessed when Reset is low. See
Section 6.5
.
Control Port Definitions
SCL
8
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an
external pull-up resistor to VD in IC mode.
SDA
9
Serial Control Data (Input/Output) - SDA is a data I/O line in IC mode and requires an external pull-up
resistor to the logic interface voltage.
Stand-Alone Definitions
DIF0
8
Digital Interface Format (Input) - The required relationship between the Left/Right clock, serial clock
and serial data is defined by the Digital Interface Format and the options are detailed below
DEM
9
De-emphasis Control (Input) - Selects the standard 15
s/50
s digital de-emphasis filter response at
44.1 kHz sample rates. NOTE: De-emphasis is not available in Double- or Quad-Speed Modes. When
DEM is grounded, de-emphasis is disabled.
Serial Data
SDIN
RST
Reset
Left/Right Clock
LRCK
GND
Headphone B Ground
Serial Clock
SCLK
HP_B
Headphone B Output
Master Clock
MCLK
VA_HPB
Headphone B Power
Digital Power
VD
VA_HPA Headphone A Power
Ground
GND
HP_A
Headphone A Output
Digital Power
VD
GND
Headphone A Ground
SCL/DIF0
SCL/DIF0
SDA/DEM SDA/DEM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
DIF0
DESCRIPTION
FIGURE
0
IS, up to 24-bit data
18
1
Right Justified, 16-bit Data
19
Table 14. Digital Interface Format (Stand-Alone Mode)
26
DS640PP4
CS44L11
6. APPLICATIONS
6.1
Grounding and Power Supply Decoupling
As with any switching converter, the CS44L11 requires careful attention to power supply and grounding ar-
rangements to optimize performance.
Figures 3
and
4
show the recommended power arrangement with VD
and VA_HPx connected to clean supplies. Decoupling capacitors should be located as close to the device
package as possible. If desired, all supply pins may be connected to the same supply, but a decoupling ca-
pacitor should still be used on each supply pin.
6.2
Clock Modes
One of the characteristics of a PWM amplifier is that the frequency content of out-of-band noise generated
by the modulator is dependent on the PWM switching frequency. The systems designer will specify the ex-
ternal filter based on this switching frequency. The obvious implementation in a digital PWM system is to
directly lock the PWM switching rate to the incoming data sample rate. However, this would require a tun-
able filter to attenuate the switching frequency across the range of possible sample rates. To simplify the
external filter design and to accommodate sample rates ranging from 8 kHz to 96 kHz the CS44L11 Con-
troller uses several clock modes that keep the PWM switching frequency in a small range.
In Control Port Mode, for operation at a particular sample rate the user selects register settings (refer to
Section 4.9
and
Tables 11
and
13
) based on their MCLK and MCLK/LRCK parameters. When using
Stand-Alone mode, refer to Tables
Tables 12
and
14
for available clock modes.
6.3
De-Emphasis
The CS44L11 includes on-chip digital de-emphasis.
Figure 6
shows the de-emphasis curve. The frequency
response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs.
The de-emphasis feature is included to accommodate older audio recordings that utilize pre-emphasis
equalization as a means of noise reduction.
6.4
PWM PopGuard Transient Control
The CS44L11 uses PopGuard
technology to minimize the effects of output transients during power-up and
power-down. This technique minimizes the audio transients commonly produced by a single-ended, sin-
gle-supply converter when it is implemented with external DC-blocking capacitors connected in series with
the audio outputs.
When the device is initially powered-up, the HP_x outputs are clamped to GND. Following a delay each out-
put begins to increase the PWM duty cycle toward the quiescent voltage point. By a speed set by the
RMP_SP bit, the HP_x outputs will later reach the bias point (50% PWM duty cycle), and audio output be-
gins. This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to the qui-
escent voltage, minimizing the power-up transient.
To prevent transients at power-down, the device must first enter its power-down state. When this occurs,
audio output ceases and the PWM duty cycle is decreased until the HP_x outputs reach GND. The time
required to reach GND is determined by the RMP_SP bits. This allows the DC-blocking capacitors to slowly
discharge. Once this charge is dissipated, the power to the device may be turned off, and the system is
ready for the next power-on.
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before
turning off the power or exiting the power-down state. If full discharge does not occur, a transient will occur
when the audio outputs are initially clamped to GND. The time that the device must remain in the pow-
er-down state is related to the value of the DC-blocking capacitance and the output load. For example, with
DS640PP4
27
CS44L11
a 220 F capacitor and a 16
load on the headphone outputs, the minimum power-down time will be ap-
proximately 0.4 seconds.
Note that ramp-up and ramp-down period can be set to zero with the RUPBYP and RDNBYP bits respec-
tively.
6.5
Recommended Power-Up Sequence
6.5.1
Stand-Alone Mode
1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control
port is reset to its default settings and the HP_x lines will remain low.
2. Bring RST high. The device will remain in a low power state and will initiate the Stand-Alone power-up
sequence. The control port will be accessible at this time.
6.5.2
Control Port Mode
1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control
port is reset to its default settings and the HP_x lines will remain low.
2. Bring RST high. The device will remain in a low power state and will initiate the Stand-Alone power-up
sequence. The control port will be accessible at this time.
3. On the CS44L11 the control port pins are shared with stand-alone configuration pins. To enable the
control port, the user must set the CP_EN bit. This is done by performing an IC write. Once the
control port is enabled, these pins are dedicated to control port functionality.
To prevent audible artifacts, the CP_EN bit (see
Section 4.10.4
) should be set prior to the completion of
the Stand-Alone power-up sequence (1024/Fs: approximately 21 ms at Fs=48 kHz). Writing this bit will
halt the Stand-Alone power-up sequence and initialize the control port to its default settings. Note, the
CP_EN bit can be set any time after RST goes high; however, setting this bit after the Stand-Alone pow-
er-up sequence has completed can cause audible artifacts.
28
DS640PP4
CS44L11
7. CONTROL PORT INTERFACE
The control port is used to load all the internal settings. The operation of the control port may be completely asyn-
chronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The CS44L11 has MAP auto increment capability, enabled by the INCR bit in the MAP register, which is the MSB.
If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment
after each byte is written, allowing block reads or writes of successive registers.
7.1
IC Format
SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with a clock to
data relationship as shown in
Figure 7
. The receiving device should send an acknowledge (ACK) after each
byte received. The chip address is 0010011.
Note:
MCLK is required during all IC transactions.
7.1.1
Writing in IC Format
To communicate with the CS44L11, initiate a START condition of the bus. Next, send the chip address.
The eighth bit of the address byte is the R/W bit (low for a write). The next byte is the Memory Address
Pointer, MAP, which selects the register to be read or written. The MAP is then followed by the data to be
written. To write multiple registers, continue providing a clock and data, waiting for the CS44L11 to ac-
knowledge between each byte. To end the transaction, send a STOP condition.
7.1.2
Reading in IC Format
To communicate with the CS44L11, initiate a START condition of the bus. Next, send the chip address.
The eighth bit of the address byte is the R/W bit (high for a read). The contents of the register pointed to
by the MAP will be output after the chip address. To read multiple registers, continue providing a clock
and issue an ACK after each byte. To end the transaction, send a STOP condition.
7.2
Memory Address Pointer (MAP)
7.2.1
INCR (Auto Map Increment Enable)
Default = `0'
0 - Disabled
1 - Enabled
7
6
5
4
3
2
1
0
INCR
Reserved
Reserved
Reserved
MAP3
MAP2
MAP1
MAP0
0
0
0
0
0
0
0
0
DS640PP4
29
CS44L11
7.2.2
MAP3-0 (Memory Address Pointer)
Default = `0000'
SDA
SCL
R/W
Start
ACK
DATA
1-8
ACK
DATA
1-8
ACK
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Note 1
0010011
Figure 7. Control Port Timing, IC Format
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency (norm alized to Fs)
Am
p
l
i
t
u
d
e
(
d
B)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
Frequency (norm alized to Fs)
Am
p
l
i
t
u
d
e
(
d
B)
Figure 8. Single-Speed Stopband Rejection
Figure 9. Single-Speed Transition Band
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
Frequency (norm alized to Fs)
Am
p
l
i
t
u
d
e
(
d
B)
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (norm alized to Fs)
Am
p
l
i
t
u
d
e
(
d
B)
Figure 10. Single-Speed Transition Band (Detail)
Figure 11. Single-Speed Passband Ripple
30
DS640PP4
CS44L11
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency (norm alized to Fs)
Am
p
l
i
t
u
d
e
(
d
B)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
Frequency (norm alized to Fs)
Am
p
l
i
t
u
d
e
(
d
B)
Figure 12. Double-Speed Stopband Rejection
Figure 13. Double-Speed Transition Band
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
Frequency (norm alized to Fs)
Am
p
l
i
t
u
d
e
(
d
B
)
-0.50
-0.40
-0.30
-0.20
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
0. 00
0.05
0. 10
0. 15
0. 20
0. 25
0.30
0. 35
0.40
0. 45
0.50
F reque nc y ( no rm a lized t o F s)
Figure 14. Double-Speed Transition Band (Detail)
Figure 15. Double-Speed Passband Ripple
DS640PP4
31
CS44L11
Figure 16. Left-Justified, up to 24-Bit Data
LRCK
SCLK
Left Channel
Right Channel
SDATA
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4
Figure 17. Right-Justified, 24-Bit Data
LRCK
SCLK
Left Channel
SDATA
6 5 4 3 2 1 0
7
23 22 21 20 19 18
6 5 4 3 2 1 0
7
23 22 21 20 19 18
32 clocks
0
Right Channel
LRCK
SCLK
Left Channel
Right Channel
SDATA
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4
Figure 18. IS, Up to 24-Bit Data
Figure 19. Right-Justified, 16-Bit Data
LRCK
SCLK
Left Channel
Right Channel
SDATA
6 5 4 3 2 1 0
9 8 7
15 14 13 12 11 10
6 5 4 3 2 1 0
9 8 7
15 14 13 12 11 10
32 clocks
32
DS640PP4
CS44L11
8. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made
with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full
scale. This technique ensures that the distortion components are below the noise level and do not effect the
measurement. This measurement technique has been accepted by the Audio Engineering Society,
AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in deci-
bels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
9. REFERENCES
"The IC-Bus Specification: Version 2.0" Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
DS640PP4
33
CS44L11
10.PACKAGE DIMENSIONS
Notes:
1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mis-
match and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.
2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm
total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimen-
sion "b" by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
INCHES
MILLIMETERS
NOTE
DIM
MIN
NOM
MAX
MIN
NOM
MAX
A
--
--
0.043
--
--
1.10
A1
0.002
0.004
0.006
0.05
--
0.15
A2
0.03346
0.0354
0.037
0.85
0.90
0.95
b
0.00748
0.0096
0.012
0.19
0.245
0.30
2,3
D
0.193
0.1969
0.201
4.90
5.00
5.10
1
E
0.248
0.2519
0.256
6.30
6.40
6.50
E1
0.169
0.1732
0.177
4.30
4.40
4.50
1
e
--
0.026 BSC
--
--
0.065 BSC
--
L
0.020
0.024
0.028
0.50
0.60
0.70
0
4
8
0
4
8
JEDEC #: MO-153
Controlling Dimension is Millimeters
16L TSSOP (4.4 mm BODY) PACKAGE DRAWING
E
N
1 2 3
e
b
2
A1
A2
A
D
SEATING
PLANE
E1
1
L
SIDE VIEW
END VIEW
TOP VIEW
34
DS640PP4
CS44L11
11.REVISION HISTORY
Release
Date
Changes
PP1
April 2004
Initial Preliminary Release
PP2
September
2004
Added Lead-free device ordering information.
PP3
March 2005
-Corrected
"Features" on page 1
.
-Corrected
Table 11, "Single-Speed Clock Modes - Control Port Mode," on page 21
.
-Corrected
Table 12, "Single-Speed Clock Modes - Stand-Alone Mode," on page 21
.
-Corrected
Table 13, "Double-Speed Clock Modes - Control Port Mode," on page 22
.
PP4
July 2005
Added last two rows to
Table 13, "Double-Speed Clock Modes - Control Port Mode," on
page 22
.
Table 15. Revision History
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to
www.cirrus.com
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