Advance Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 2000
(All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CS4811
Fixed Function Multi-Effects Audio Processor
Features
l
Audio Processor for embedded
reverb/effects applications
Proprietary 24-bit Audio Processing Engine
On-chip RAM (No external RAM required)
On-chip 24-bit
ADC with 100 dB Dyn. Range
On-chip 24-bit
DAC with 100 dB Dyn. Range
Automatically boots firmware from external
serial EEPROM
l
Firmware available for Guitar Effects or Mixer
Effects applications
l
Single +5 V Supply
l
100-pin Metric Quad Flat Pack (MQFP)
Description
The CS4811 is a complete audio effects processing
system on a chip. This device integrates a proprietary 24-
bit audio processing engine, large on-chip RAM
memories, and a high performance 24-bit audio codec. A
serial control port allows the device to boot firmware from
a compact and low cost SPI or I
2
C serial EEPROM. Other
features such as single +5 V operation simplify system
design.
Firmware for the CS4811 is provided by Cirrus Logic.
There are two different firmware codes available; one for
guitar effects and one for audio mixers. The guitar effects
firmware provides a host of electric guitar effects includ-
ing spring reverb, delay, chorus, flange and tremolo.
The mixer effects firmware provides a suite of effects
such as digital reverb, delay and chorus which are suit-
able for use in audio mixers, karaoke and acoustic
instrument amplifiers. The CDB4811GTR and
CDB4811MXR evaluation boards allow easy evaluation
of the CS4811 device and the associated firmware.
ORDERING INFO
CS4811-KM
-10 to +70C
100-pin MQFP
CDB4811GTR-01
Guitar Effects Evaluation Board
CDB4811MXR-01
Mixer Effects Evaluation Board
I
CMOUT
CMFILT+
CMFILT-
AIN+
AIN-
XTO
XTI
CLOCK
MANAGER
AOUT+
24-BIT AUDIO
VOLTAGE
REFERENCE
PIO3
PIO2
PIO1
PIO0
DIGITAL FILTER
DAC
AN
AL
O
G
L
P
F
AN
D
O
U
T
P
UT
S
T
AG
E
DI
GITA
L H
P
F
SERIAL CONTROL PORT (SPI or I
2
C)
ADC
SPI/I
2
C
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
RST
OVL
AOUT-
PROCESSING
ENGINE
RAM
SEP `00
DS486PP2
CS4811
2
DS486PP2
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
ADC CHARACTERISTICS ....................................................................................................... 4
DAC CHARACTERISTICS ....................................................................................................... 5
SWITCHING CHARACTERISTICS .......................................................................................... 6
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MASTER.................................. 7
SWITCHING CHARACTERISTICS - CONTROL PORT - I
2
C MASTER .................................. 8
RECOMMENDED OPERATING CONDITIONS ....................................................................... 9
DIGITAL CHARACTERISTICS ................................................................................................. 9
SWITCHING CHARACTERISTICS - PROGRAMMABLE I/O................................................... 9
2. TYPICAL CONNECTION DIAGRAMS ................................................................................... 10
3. FUNCTIONAL DESCRIPTION ............................................................................................... 12
3.1 Overview .......................................................................................................................... 12
3.2 Analog Inputs ................................................................................................................... 12
3.2.1 Line Level Inputs ................................................................................................. 12
3.2.2 Digital High Pass Filter ........................................................................................ 12
3.3 Analog Outputs ................................................................................................................ 13
3.3.1 Line Level Outputs .............................................................................................. 13
3.4 Clock Generation ............................................................................................................. 13
3.4.1 Clock Source ....................................................................................................... 13
3.5 Serial Control Port ............................................................................................................ 14
3.5.1 SPI Bus ............................................................................................................... 14
3.5.1.1 SPI Mode ................................................................................................ 14
3.5.2 I
2
C Bus ................................................................................................................ 14
3.5.2.1 I
2
C Mode ................................................................................................ 14
3.6 Resets .............................................................................................................................. 15
4. POWER SUPPLY AND GROUNDING ................................................................................... 16
5. PIN DESCRIPTIONS .............................................................................................................. 17
6. PARAMETER DEFINITIONS .................................................................................................. 21
7. PACKAGE DIMENSIONS ..................................................................................................... 22
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.
CS4811
DS486PP2
3
LIST OF FIGURES
Figure 1. SPI Control Port Timing ............................................................................. 7
Figure 2. I
2
C Control Port Timing .............................................................................. 8
Figure 3. Typical Connection Diagram, Single-ended Input .................................... 10
Figure 4. Typical Connection Diagram, I
2
C Mode .................................................. 11
Figure 5. Typical Connection Diagram, SPI Mode .................................................. 11
Figure 6. Optional Line Input Buffer ........................................................................ 12
Figure 7. Butterworth Output Filters ........................................................................ 13
Figure 8. Output Mute Circuit .................................................................................. 13
Figure 9. Control Port Timing, SPI Master Mode Self-Boot ..................................... 14
Figure 10.Control Port Timing, I2C Master Mode Self-Boot ..................................... 15
Figure 11.CS4811 Suggested Layout ...................................................................... 16
Figure 12.Pin Assignments ...................................................................................... 17
CS4811
4
DS486PP2
1. CHARACTERISTICS AND SPECIFICATIONS
ADC CHARACTERISTICS
(T
A
= 25 C; VA, VD = + 5 V; -1 dB Full Scale Input Sine wave, 997 Hz; Fs =
48 kHz; XTI = 12.2880 MHz; Measurement Bandwidth is 20 Hz to 20 kHz)
Notes: 1. Referenced to typical full-scale differential input voltage (2 V
rms
).
2. Bench tested only.
3. Filter characteristics scale with output sample rate.
4. Measured using differential analog input circuit, see Figure 6.
5. Filter response is not tested but is guaranteed by design.
Parameters
Symbol Min Typ
Max
Units
Analog Input Characteristics
ADC Conversion
Stereo Audio channels
16
-
24
Bits
Dynamic Range
(A weighted, Note 4)
(unweighted, Note 4)
93
90
100
97
-
-
dB
dB
Total Harmonic Distortion + Noise
(Note 1,4)
THD+N
-
-92
-87
dB
Offset Error (with internal high pass filter enabled)
(Note 5)
-
-
0
LSB
Full Scale Input Voltage (Differential)
1.9
2.0
2.1
V
rms
Gain Drift
(Note 2)
-
100
-
ppm/C
Input Resistance
10
-
-
k
Input Capacitance
-
-
15
pF
CMOUT Output Voltage
-
2.3
-
V
Common Mode Rejection Ratio
(Note 2)
CMRR
60
dB
High Pass Filter Characteristics
Frequency Response
-3dB (Note 3)
-0.14dB (Note 3)
-
-
3.7
20
-
-
Hz
Hz
Phase Deviation
@ 20 Hz (Note 3)
-
10
-
Degree
Passband Ripple
-
-
0
dB
CS4811
DS486PP2
5
DAC CHARACTERISTICS
(T
A
= 25 C; VA, VD = + 5 V; Full Scale Output Sine wave, 997 Hz; Fs =
48 kHz; XTI = 12.288 MHz; Measurement Bandwidth is 20 Hz to 20 kHz)
Notes: 6. Measured with DAC calibration disabled.
7. Measured with XTI clock disabled.
Specifications are subject to change without notice.
Parameters
Symbol Min Typ
Max
Units
Analog Output Characteristics - Minimum Attenuation, 10 k
, 100 pF load; unless otherwise specified.
DAC Resolution
16
-
24
Bits
Dynamic Range
(DAC not muted, A weighted)
95
100
-
dB
Total Harmonic Distortion + Noise
THD+N
-
-90
-85
dB
Offset Voltage (differential)
(Note 6)
-
-205
-
mV
Offset Voltage (V+/V- relative to CMOUT)
(Note 6)
-
-45/-28
-
mV
Full Scale Output Voltage
(Differential)
1.9
2.0
2.1
V
rms
Gain Drift
(Note 2)
-
100
-
ppm/C
Out of Band Energy
(Fs/2 to 2Fs, Note 2)
-
-60
-
dBFS
Analog Output Load
Resistance
Capacitance
10
-
-
-
-
100
k
pF
Analog Loopback Performance
Signal-to-Noise Ratio (CCIR-2K weighted, -20 dB input)
CCIR-2K
-
74
-
dB
Power Supply
Power Supply Current
Operating
Power Down
(Note 7)
-
-
200
1
-
-
mA
mA
Power Supply Rejection
(1 kHz, 10 mV
rms,
, Note 2)
-
50
-
dB
CS4811
6
DS486PP2
SWITCHING CHARACTERISTICS
(T
A
= 25 C; VA, VD = +5 V, outputs loaded with 30 pF)
Notes: 8. Guaranteed by characterization but not tested.
9. On power-up, the CS4811 RST pin should be asserted until the power supplies have reached steady
state.
Parameters
Symbol
Min
Typ
Max
Units
ADC & DAC Sample Rate
Fs
30
-
50
kHz
XTI Frequency XTI = 256Fs
7.68
-
12.8
MHz
XTI Duty Cycle XTI =256Fs
(Note 8)
40
-
60
%
XTI Jitter Tolerance
-
500
-
ps
RST Low Time
(Note 9)
500
-
-
ns
CS4811
DS486PP2
7
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MASTER
(TA = 25 C,
VA, VD = 5 V; Inputs: logic 0 = DGND, logic 1 = VD, C
L
= 30 pF)
Notes: 10. Measured with a 2.2 k
pullup resistor to VD.
Parameter
Symbol
Min
Typ
Max
Units
SPI Master (Self-Boot) Mode
(SPI/I2C = 0, SCPM/S = 1)
CCLK Clock Frequency
f
sck
-
Fs
-
kHz
CCLK Low Time
t
scl
-
1/(2*Fs)
-
ns
CCLK High Time
t
sch
-
1/(2*Fs)
-
ns
CCLK Rise Time
(Note 10)
t
r2
-
12
-
ns
CCLK Fall Time
(Note 10)
t
f2
-
12
-
ns
RST rising to CS falling
t
srs
-
42
-
s
CS High Time Between Transmissions
t
csh
37
-
-
s
CS Falling to CCLK Edge
t
css
5
-
-
s
CS Falling to CDOUT valid
t
dv
-
-
50
ns
CCLK Falling to CDOUT valid
t
pd
-
-
100
ns
CDIN to CCLK Rising Setup Time
t
dsu
80
-
-
ns
CCLK Rising to DATA Hold Time
t
dh
80
-
-
ns
CCLK Falling to CS rising
t
clcs
40
-
-
ns
t r2
t f2
t dsu t dh
t sch
t scl
CS
CCLK
CDIN
t css
t csh
t clcs
t srs
RST
t pd
CDOUT
t dv
Figure 1. SPI Control Port Timing
CS4811
8
DS486PP2
SWITCHING CHARACTERISTICS - CONTROL PORT - I
2
C MASTER
(T
A
= 25 C;
VA, VD = 5 V; Inputs: logic 0 = DGND, logic 1 = VD, C
L
= 30 pF)
Notes: 11. Use of the I
2
C bus interface requires a license from Philips. I
2
C is a registered trademark of Philips
Semiconductors.
12. Data must be held for sufficient time to bridge the worst case fall time of 300 ns for CCLK/SCL.
13. For both SDA transmitting and receiving.
Parameter
Symbol
Min
Typ
Max
Units
I
2
C
Master (Self-Boot) Mode
(SPI/I2C = 1, SCPM/S = 1) (Note 11)
SCL Clock Frequency
f
scl
-
Fs
-
kHz
Clock Low Time
t
low
-
1/(2*Fs)
-
s
Clock High Time
t
high
-
1/(2*Fs)
-
s
Bus Free Time Between Transmissions
t
buf
4.7
-
-
s
RST rising to start condition
t
irs
-
22
-
s
Start Condition Hold Time
t
hdst
4.0
-
-
s
Setup Time for Repeated Start Condition
t
sust
13.5
-
-
s
SDA Setup Time to SCL Rising
t
sud
250
-
-
ns
SDA Hold Time from SCL Falling
(Note 12)
t
hdd
0
-
-
ns
SCL falling to SDA Output Valid
t
cldv
-
-
1.5
s
SCL and SDA Rise Time
(Note 13)
t
r
-
-
1
s
SCL and SDA Fall Time
(Note 13)
t
f
-
-
300
ns
Setup Time for Stop Condition
t
susp
4.7
-
-
s
t
buf
t
hdst
t
hdst
t
low
t r
t f
t
hdd
t
high
t sud
tsust
t susp
Stop
Start
Start
Stop
Repeated
SDA
SCL
t
irs
RST
t
cldv
(output)
Figure 2. I
2
C Control Port Timing
CS4811
DS486PP2
9
ABSOLUTE MAXIMUM RATINGS
(All voltages with respect to AGND = DGND = 0 V.)
Notes: 14. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause
SCR latch-up.
15. The maximum over or under voltage is limited by the input current.
Warning:
Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(All voltages with respect to AGND = DGND =
0 V.)
DIGITAL CHARACTERISTICS
(T
A
= 25 C; VA, VD = 5 V)
SWITCHING CHARACTERISTICS - PROGRAMMABLE I/O
(T
A
= 25 C; VA, VD = 5 V
5%; Inputs: logic 0 = DGND, logic 1 = VD, C
L
= 30 pF)
Parameters
Symbol
Min Typ
Max
Units
Power Supplies
Digital
Analog
VD
VA
-0.3
-0.3
-
-
6.0
6.0
V
V
Input Current
(Note 14)
-
-
10.0
mA
Analog Input Voltage
(Note 15)
-0.7
-
(VA)+0.7
V
Digital Input Voltage
(Note 15)
-0.7
-
(VD)+0.7
V
Ambient Temperature
(Power Applied)
-55
-
+125
C
Storage Temperature
-65
-
+150
C
Parameters
Symbol
Min Typ
Max
Units
Power Supplies
Digital
|VA - VD| < 0.4V
Analog
VD
VA
4.75
4.75
5.0
5.0
5.25
5.25
V
V
Operating Ambient Temperature
T
A
-10
25
70
C
Parameters
Symbol
Min Typ
Max
Units
High-level Input Voltage
(except XTI)
V
IH
2.8
-
(VD)+0.3
V
Low-level Input Voltage
(except XTI)
V
IL
-0.3
-
0.8
V
High-level Output Voltage at I
0
= -2.0 mA
(except XTO)
V
OH
(VD)-1.0
-
-
V
Low-level Output Voltage at I
0
= 2.0 mA
(except XTO)
V
OL
-
-
0.4
V
High-level Input Voltage
(XTI)
V
IH
2.8
-
-
V
Low-level Input Voltage
(XTI)
V
IL
-
-
2.3
V
Input Leakage Current
(Digital Inputs)
-
-
10
A
Output Leakage Current
(High-Z Digital Outputs)
-
-
10
A
Parameters
Symbol
Min
Typ
Max
Units
Output Rise Time
t
rpo
-
200
-
ns
Output Fall Time
t
fpo
-
200
-
ns
CS4811
10
DS486PP2
2. TYPICAL CONNECTION DIAGRAMS
D
D
A
+
1
F
0.1
F
AGND1..4
DGND1..4
XTO XTI
46
45
Caps, Xtal, and
resistor not needed
with external clock
input to XTI.
44
7
AOUT +
63
62
68
67
SCL/CCLK
SDA/CDOUT
AD0/CS
AD1/CDIN
92
1
F
CMOUT
86
To Optional
Input and
Output Buffers
AIN+
87
37
PIO2
35
PIO3
Control/
Monitor
Circuitry
72
69
SPI/I2C
Mode/Reset
Circuit
All unused inputs
should be tied to ground.
CS4811
40
PIO1
41
ANALOG
FILTER
R
= 33
S
150
2.2 nF
66
64
93
94
0.1 F
1 F
+
CMFILT+
CMFILT-
RST
PIO0
8
AOUT -
2.2 K
2.2 K
VD VD
13
89
19
42
11
39 pF
22 F
+
AIN -
0.1 F
100 F
+
RESET
Serial EEPROM
1 M
0.1 F
39 pF
39
OVL
A
A
A
A
A
A
A
D
D
D
A
VA 1..3
88
18
12
+ 1
F
0.1
F
43
65
VD 1..2
+5 V Supply
Ferrite Bead
RES-DGND
RES-DGND
RES-DGND
RES-DGND
D
RES-DGND
RES-DGND
32, 36, 38, 48, 96, 82, 83
1, 2, 3, 4, 5, 6
31, 33, 49, 50, 51, 52, 53
24, 25, 26, 27, 28, 29, 30
78, 79, 80, 81, 84, 85, 98, 99, 100
54, 55, 56, 74, 75, 76, 77
RES-NC
RES-NC
9, 10, 14, 15, 16, 17, 20
RES-NC
21, 22, 23, 47, 57, 58, 59
60, 61, 71, 95, 97, 90, 91
RES-VD
70, 73
VD
Figure 3. Typical Connection Diagram, Single-ended Input
CS4811
DS486PP2
11
63
62
68
67
I C
EEPROM
SCL/CCLK
SDA/CDOUT
AD0/CS
AD1/CDIN
72
69
SPI/I2C
Reset
Circuit
RST
CS4811
2
2.2 K
2.2 K
VD VD
A0
A1
A2
VD
RESET
D
D
Figure 4. Typical Connection Diagram, I
2
C Mode
63
62
68
67
SPI
EEPROM
SCL/CCLK
SDA/CDOUT
AD0/CS
AD1/CDIN
72
69
SPI/I2C
Reset
Circuit
RST
CS4811
RESET
2.2 K
2.2 K
VD VD
D
Figure 5. Typical Connection Diagram, SPI Mode
CS4811
12
DS486PP2
3. FUNCTIONAL DESCRIPTION
3.1
Overview
The CS4811 is a complete audio subsystem on a
chip, integrating a proprietary 24-bit audio process-
ing engine with large on chip RAM memories and
a single channel 24-bit audio codec.
The delta-sigma ADC includes linear phase digital
anti-aliasing filters and only requires a single-pole
external passive filter.
The sigma-delta DAC includes a switched-capaci-
tor anti-image filter and requires an external 2nd or
3rd order active filter that can be easily integrated
into the output differential-to-single-ended con-
verter circuit.
The serial control port is designed to accommodate
I
2
C
or SPI interfaces for stand-alone operation
with an external non-volatile memory.
3.2
Analog Inputs
3.2.1
Line Level Inputs
AIN+ and AIN- are the differential line level ana-
log inputs (See Figure 3). These pins are internally
biased to the CMOUT voltage of 2.3 V. A DC
blocking capacitor placed in series with the input
pins allows signals centered around 0 V to be input
to the CS4811. Figure 3 shows operation with a
single-ended input source. This source may be sup-
plied to either the positive or negative input as long
as the unused input is connected to ground through
capacitors as shown. When operated with single-
ended inputs, distortion will increase at input levels
higher than -1 dB Full Scale. If better performance
is required, a single-ended-to-differential convert-
er, shown in Figure 6, may be used. This circuit
provides unity gain, DC blocking on the input and
anti-alias filtering.
The OVL output pin asserts when the analog input
is out-of-range.
3.2.2
Digital High Pass Filter
In DC coupled systems, a small DC offset may ex-
ist between the input circuitry and the A/D con-
verters. The CS4811 includes a high pass filter
after the decimator to remove these DC compo-
nents. The high pass filter response, given in High
Pass Filter Characteristics, scales linearly with
sample rate. Thus, the -3 dB frequency at a
44.1 kHz sample rate will be equal to 44.1/48 times
that at a sample rate of 48 kHz.
+
-
10 k
+
-
4.7 k
AIN -
10
F
+
AIN +
2.2 nf
150
150
10 k
10 k
input signal
+
(2 Vrms max)
+5 V
CMOUT
from
CS4811
+
-
0.1
F
10
f
GND
Buffered
CMOUT
Figure 6. Optional Line Input Buffer
CS4811
DS486PP2
13
3.3
Analog Outputs
3.3.1
Line Level Outputs
The CS4811 contains on-chip differential buffer
amplifiers that produce line level outputs AOUT+
and AOUT-, which are capable of driving 10 k
loads. These amplifiers are internally biased to the
CMOUT voltage of 2.3 V.
The recommended off-chip analog filter is a 2nd
order Butterworth with a -3 dB corner at Fs. A third
order Butterworth filter with a -3 dB corner at
0.75 Fs can be used if greater out of band noise fil-
tering is desired. These filters can be easily inte-
grated into a differential-to-single-ended converter
circuit as shown in the 2-pole and 3-pole Butter-
worth filters of Figure 7. Figure 8 shows the rec-
ommended mute circuit referenced in Figure 7.
Activating the mute circuit is recommended on
power-up and power-down to avoid the output of
undesirable audio signals.
3.4
Clock Generation
The master clock to operate the CS4811 may be gen-
erated by using the on-chip oscillator with an exter-
nal crystal or may be input from an external clock
source.
3.4.1
Clock Source
The CS4811 requires a 256 Fs master clock to run
the internal logic. The two possible clock sources
are the on-chip crystal oscillator or an external clock
input to the XTI pin.
The master clock may be generated directly from
the on-chip crystal oscillator circuit. When using
the on-chip crystal oscillator, external loading ca-
pacitors are required. (see Figure 3) High frequen-
cy crystals (>8 MHz) should be parallel resonant,
fundamental mode and designed for 20 pF loading.
(equivalent to 40 pF to ground on each leg)
The master clock may also be generated directly
from an external CMOS clock input to the XTI pin.
2-Pole Butterworth Filter
BUFFERED
CMOUT
_
+
Example
Op-Amps
are
MC33078
A
OU T-
MUTE
Line
Out
14.0 k
14.0 k
A
OU T+
3.24 k
3.24 k
1000 pF
1000 pF
14.0 k
220 pF
220 pF
14.0 k
GND
+5 V
BUFFERED
CMOUT
_
+
MUTE
Line
Out
A
OU T+
A
OU T-
220 pF
220 pF
2200 pF
2.8k
2.8k
2.8k
2.8k
11.0k
11.0k
14.0k
14.0k
2200 pF
2200 pF
2200 pF
GND
+5 V
3-Pole Butterworth Filter
Figure 7. Butterworth Output Filters
Line Out
VA
From
CS4811
PIO
MMBT3906
MMBT3904
MMBT3906
10 k
10 k
10 k
GND
3.3 k
10
F
1 k
10
F
+
Figure 8. Output Mute Circuit
CS4811
14
DS486PP2
3.5
Serial Control Port
The serial control port is used for self-booting from
an external EEPROM and supports both the SPI
bus and the I
2
C
bus interfaces. The desired inter-
face is selected via the SPI/I
2
C pin, which is sam-
pled during de-assertion of the RST pin.
3.5.1
SPI Bus
The SPI bus interface consists of 4 digital signals,
CCLK, CDIN, CDOUT and CS. CCLK, the control
port bit clock, is used to clock individual data bits.
CDIN, the control data input, is the serial data input
line to the CS4811. CDOUT, the control data output,
is the output data line from the CS4811. CS, the chip
select signal, is asserted to enable an external SPI
port. Data is clocked in on the rising edge of CCLK
and clocked out on the falling edge.
3.5.1.1
SPI Mode
The SPI master mode is designed for read-only op-
eration during self-booting from a serial EEPROM.
A typical self-boot sequence with a Xicor X25650 se-
rial EEPROM, or equivalent, is shown in Figure 9. On
exit from reset, the CS4811 asserts CS. The 8-bit read
instruction (00000011) is sent to the EEPROM fol-
lowed by a pre-defined 16-bit start address. The
CS4811 then automatically clocks out sequential
bytes from the EEPROM until the last byte has
been received. These bytes include initialization
and configuration data for the device along with the
application firmware code. After the last byte is re-
ceived, the CS4811 deasserts CS and begins program
execution. At this point, the serial control port be-
comes inactive and cannot be accessed.
3.5.2
I
2
C Bus
The I
2
C bus interface implemented on the CS4811
consists of 2 digital signals, SCL and SDA. SCL or
serial clock, is used to clock individual data bits.
SDA or serial data, is a bidirectional data line. Two
additional pins, AD1 and AD0, are inputs which
determine the 2 lowest order bits of the 7-bit I
2
C
device address and should be tied to ground.
3.5.2.1
I
2
C Mode
The I
2
C master mode is designed for read-only op-
eration during self-booting from a serial EEPROM.
A typical self-boot sequence with a Microchip
X24256 serial EEPROM, or equivalent, is shown
in Figure 10. On exit from reset, the CS4811 sends
an initial write preamble to the EEPROM which
consists of a I
2
C start condition and the slave ad-
0 1 2
21 22 23 24
CS
CDOUT
READ
COMMAND
16-BIT
ADDRESS = 0X0000
CDIN
DATA
MSB
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0
0 0 0 0 0 0 1 1
CLK
7 8 9 10 11
3 4 5 6
30 31
25 26 27 28 29
DATA + n
7 6 5 4 3 2 1 0
Figure 9. Control Port Timing, SPI Master Mode Self-Boot
CS4811
DS486PP2
15
dress byte. The slave address consists of the 4 most
significant bits set to 1010, the following 3 bits cor-
responding to the device select bits, A2, A1 and A0
set to 000 and the last bit (R/
W
) set to 0. Following
this, a 2-byte EEPROM starting address of 0x0000
is sent to the EEPROM. The 2-byte EEPROM
starting address uses only the lowest 13 bits and
sets the highest 3 bits to zero. To begin reading
from the EEPROM, the CS4811 sends another start
condition followed by a read preamble. The read
preamble is identical to the write preamble except
for the state of the R/
W
bit. The CS4811 then auto-
matically clocks out sequential bytes from the EE-
PROM until the last byte has been received. These
bytes include initialization and configuration data
for the device along with the application firmware
code. After the last byte, the CS4811 initiates a stop
condition and begins program execution. At this
point, the serial control port becomes inactive and
cannot be accessed.
3.6
Resets
Full chip reset can only be achieved by asserting
the RST pin. With RST asserted, the chip enters
low power mode during which the control port,
CODEC and Audio Processor are reset, all registers
are returned to their default values and the DAC
outputs are muted. The RST pin should be asserted
during power-up until the power supplies have
reached steady state.
If the supply voltage drops below 4 Volts, the CO-
DEC is reset, the DAC outputs are muted and the
Audio Processor automatically executes a soft re-
set.
Upon exit from a CODEC reset, the Audio Proces-
sor restarts the application code and the CODEC
performs the following procedure:
The CODEC resynchronizes.
The DAC outputs unmute.
0 1 2 3
16 17 18 19
25 26 27 28 29
CHIP ADDRESS (WRITE)
CHIP ADDRESS (READ)
MEMORY ADDRESS
DATA
DATA +n
START
ACK
NO
START
STOP
ACK
ACK
ACK
ACK
1 0 1 0 A
2
A
1
A
0
0
0 0 0
0 0 0
1 0 1 0 A
2
A
1
A
0
1
7 0
7 0
SCL
SDA
34 35 36 37
30 31 32 33
8 9 10
4 5 6 7
Figure 10. Control Port Timing, I
2
C Master Mode Self-Boot
CS4811
16
DS486PP2
4. POWER SUPPLY AND GROUNDING
Proper layout and grounding is critical to obtaining
optimal audio performance in your system. The
most important rule to remember is to not allow
currents from digital circuitry to couple into sensi-
tive analog circuitry. This is generally done by us-
ing a separate or filtered power supply for the
analog circuitry, physically separating the analog
and digital components and traces in the pcb layout
and using wide traces or planes for ground and
power. One misplaced component or trace can se-
verely degrade overall system performance.
When using separate supplies, the analog and digi-
tal power should be connected via a ferrite bead,
positioned closer than 1" to the device (see
Figure 11). The CS4811 VA pin should be derived
from the quietest power source available. If only
one supply is available, use the suggested arrange-
ment in Figure 3.
A single solid ground plane is the simplest ground-
ing scheme that works well in many cases. In this
case, all analog and digital grounds shown in
Figure 3 are tied to the same ground plane. Howev-
er, if separate analog and digital grounds are used,
they should be tied together at one point with the
location of this point determined by the circuit lay-
out. By considering where the digital ground cur-
rents will return to their supply, the connection
point can be chosen to keep those currents from
flowing through sensitive analog circuit areas.
Decoupling capacitors should be placed as close as
possible to the device with the lowest value capac-
itor closest to the chip. Any power and ground con-
nection vias should be placed near their respective
component pins and should be attached directly to
the appropriate plane. If traces are used for the
power supplies to the CS4811, they should be as
wide as possible to maintain low impedance.
It is recommended to solder the CS4811 directly to
the printed circuit board. Soldering improves per-
formance and enhances reliability.
For an example layout, please refer to the
CDB4811 data sheet.
Digital
Power
Plane
Note that the CS4811
is oriented with its
digital pins towards the
digital end of the board.
Digital Interface
Analog Signals &
Components
Analog
Power
Plane
1/8"
>
CS4811
Ferrite
Bead
Figure 11. CS4811 Suggested Layout
CS4811
DS486PP2
17
5. PIN DESCRIPTIONS
DGND
AD1/CDIN
AD0/CS
SPI/I2C
RES-VD
RES-NC
RST
RES-VD
NC
NC
NC
NC
NC
NC
NC
NC
RES-DGND
RES-DGND
NC
NC
AIN+
AIN-
VA
AGND
RES-NC
RES-NC
CMOUT
CMFILT+
CMFILT-
RES-NC
RES-DGND
RES-NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AOUT+
AOUT-
RES-NC
RES-NC
AGND
VA
AGND
RES-NC
RES-NC
1
2
3 4 5
6 7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VD
DGND
SCL/CCLK
SDA/CDOUT
RES-NC
RES-NC
RES-NC
RES-NC
RES-NC
NC
NC
NC
NC
NC
NC
NC
NC
RES-DGND
RES-NC
XTO
XTI
DGND
VD
DGND
PIO0
PIO1
OVL
RES-DGND
PIO2
RES-DGND
PIO3
RES-DGND
NC
RES-DGND
NC
NC
NC
NC
NC
NC
NC
NC
RES-NC
RES-NC
RES-NC
RES-NC
AGND
VA
RES-NC
RES-NC
CS4811
100-PIN MQFP
1
2
3 4 5
6 7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VD
DGND
SCL/CCLK
SDA/CDOUT
RES-NC
RES-NC
RES-NC
RES-NC
RES-NC
NC
NC
NC
NC
NC
NC
NC
NC
RES-DGND
RES-NC
XTO
XTI
DGND
VD
DGND
PIO0
PIO1
OVL
RES-DGND
PIO2
RES-DGND
PIO3
RES-DGND
NC
RES-DGND
NC
NC
NC
NC
NC
NC
NC
NC
RES-NC
RES-NC
RES-NC
RES-NC
AGND
VA
RES-NC
RES-NC
CS4811
100-PIN MQFP
Figure 12. Pin Assignments
CS4811
18
DS486PP2
Power Supply
VA - Analog Power
Power:
analog supply, +5 V.
AGND - Analog Ground
Ground:
analog ground.
VD - Digital Power
Power:
digital supply, +5 V.
DGND - Digital Ground
Ground:
digital ground.
Analog Input
AIN+/- - Differential Audio Input
Inputs:
These pins accept differential analog input signals and are biased to the internal reference
voltage of approximately 2.3 V. The + and - input signals should be 180 out of phase resulting in a
nominal differential input voltage of twice the input pin voltage. A single-ended signal may also be
directly applied to either the + or - input with the other input AC coupled to ground through a capacitor.
In general, differential input signals provide better performance. However, singled-ended inputs may
result in reduced cost. Inputs may be AC or DC coupled. DC coupled input signals must be biased at
2.3 V. Any remaining DC offset is removed by an internal digital HPF. For best performance, a passive
anti-aliasing filter is required. The typical connection diagram in Figure 3. shows the recommended
single-ended input circuit. Figure 6 shows the recommended differential input circuit.
OVL - ADC Overload Indicator
Output:
This pin is asserted when the ADC is clipping. The pin does not latch and de-asserts when
clipping stops.
Analog Output
AOUT+/- - Differential Audio Output
Outputs:
These pins output differential analog signals which are biased to the internal reference voltage
of approximately 2.3 V. The + and - output signals are 180 out of phase resulting in a nominal
differential output voltage of twice the output pin voltage. For best performance, an anti-imaging filter is
required. Figure 7 shows the recommended second and third order Butterworth differential-to-single-
ended output buffer circuits.
CS4811
DS486PP2
19
Voltage Reference
CMOUT - Common Mode Output
Output:
This pin provides an internally generated reference of 2.3 V to be used for biasing external
analog circuitry. The load on CMOUT must be DC only, with an impedance of not less than 50 kilohms.
CMFILT+,CMFILT- - Common Mode Filter Connections
Inputs:
These pins are connections for external filter components required by the internal common mode
reference circuit. See the typical connection diagram in Figure 3. for details.
Serial Control Port
SPI
/I
2
C - Serial Control Port Format Select
Input:
This pin configures the control port for I
2
C format if tied to VD or SPI format if tied to DGND.
SCL/CCLK - Serial Control Port Clock
Output:
This pin clocks serial control port data into and out of SDA in I
2
C mode. In SPI mode, it clocks
control port data into CDIN and out of CDOUT.
AD0/
CS
- I
2
C Address Bit 0 / SPI Chip Select
Input/Output:
In I
2
C
mode, AD0 is an input and must be tied to ground. In SPI mode, CS is an output
and is used to select the boot EEPROM.
AD1/CDIN - I
2
C Address Bit 1 / SPI Data Input
Input:
In I
2
C
mode, AD1 is an input and must be tied to ground. In SPI mode, CDIN is the serial
control port data input and is clocked in on the rising edge of CCLK.
SDA/CDOUT - I
2
C Data / SPI Data Output
Bidirectional/Output:
In I
2
C
mode, SDA is the bidirectional data I/O line. In SPI mode, CDOUT is the
serial control port data output and is clocked out on the falling edge of CCLK.
Clock and Crystal
XTI, XTO - Crystal Oscillator Connections (Master Clock)
Input, Output:
These pins provide connections for an external parallel resonant quartz crystal.
Alternately, an external clock source may be applied to XTI. The clock frequency must be 256xFs.
CS4811
20
DS486PP2
Miscellaneous
PIO0:3 - General Purpose Inputs/Outputs
Bidirectional:
These pins are general-purpose digital I/O pins. The Default state is input. The
functionality of these pins after boot-up is determined by the application firmware.
RST - Reset
Input:
This pin causes the device to enter a low power mode and forces all control port and I/O registers
to be reset to their default values. The control port can not be accessed when reset is low.
NC - No Connect
Input:
These pins are not internally connected and should be tied to ground for optimal performance.
RES-NC - Reserved, No Connect
These pins are reserved and must be left unconnected for normal operation.
RES-VD - Reserved, Connect to VD
These pins are reserved and must be tied to VD for normal operation.
RES-DGND - Reserved, Connect to DGND
These pins are reserved and must be tied to digital ground for normal operation.
RES-AGND - Reserved, Connect to AGND
These pins are reserved and must be tied to analog ground for normal operation.
CS4811
DS486PP2
21
6. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the full scale RMS value of the signal to the RMS sum of all other spectral components
over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified
bandwidth made with a -60 dbFs signal. 60 dB is then added to the resulting measurement to refer the
measurement to full scale. This technique ensures that the distortion components are below the noise
level and do not effect the measurement. This measurement technique has been accepted by the Audio
Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Total Harmonic Distortion + Noise
The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the
specified bandwidth (typically 20 Hz to 20 kHz), including distortion components. Expressed in decibels.
ADCs are measured at -1 dBFs as suggested in AES 17-1991 Annex A.
Idle Channel Noise / Signal-to-Noise-Ratio
The ratio of the RMS analog output level with 1 kHz full scale digital input to the RMS analog output
level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz bandwidth. Units
in decibels. This specification has been standardized by the Audio Engineering Society, AES17-1991,
and referred to as Idle Channel Noise. This specification has also been standardized by the Electronic
Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio.
Total Harmonic Distortion (THD)
THD is the ratio of the test signal amplitude to the RMS sum of all the in-band harmonics of the test
signal. Units in decibels.
Interchannel Isolation
A measure of crosstalk between channels. Measured for each channel at the converter's output with no
signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Frequency Response
A measure of the amplitude response variation from 20 Hz to 20 kHz relative to the amplitude response
at 1 kHz. Units in decibels.
Interchannel Gain Mismatch
For the ADCs, the difference in input voltage that generates the full scale code for each channel. For
the DACs, the difference in output voltages for each channel with a full scale digital input. Units are in
decibels.
Gain Error
The deviation from the nominal full scale output for a full scale input.
Gain Drift
The change in gain value with temperature. Units in ppm/C.
Offset Error
For the ADCs, the deviation in LSB's of the output from mid-scale with the selected input grounded. For
the DAC's, the deviation of the output from zero (relative to CMOUT) with mid-scale input code. Units
are in volts.
CS4811
22
DS486PP2
7. PACKAGE DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN
NOM
MAX
MIN
NOM
MAX
A
--
--
0.134
--
--
3.400
A1
0.010
0.012
0.014
0.250
0.30
0.350
B
0.009
0.012
0.015
0.220
0.30
0.380
D
0.667
0.677
0.687
16.950
17.20
17.450
D1
0.547
0.551
0.555
13.900
14.00
14.100
E
0.904
0.91
0.923
22.950
23.20
23.450
E1
0.783
0.79
0.791
19.900
20.0
20.100
e*
0.022
0.026
0.030
0.550
0.65
0.750
0.000
4.00
7.000
0.00
4.00
7.00
L
0.029
0.035
0.041
0.73
0.88
1.03
* Nominal pin pitch is 0.65 mm = 0.65 BSC
Controlling dimension is mm.
JEDEC Designation: MS022
ASE/SPIL
100L MQFP PACKAGE DRAWING
E1
E
D1
D
1
e
L
B
A1
A
Notes
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