1
Copyright
Cirrus Logic, Inc. 2004
(All Rights Reserved)
www.cirrus.com
CS8406
192 kHz Digital Audio Interface Transmitter
Features
Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF compatible transmitter
+3.3 V or 5.0 V Digital Supply (VD)
+3.3 V or 5.0 V Digital Interface (VL)
On-chip Channel Status and User bit buffer
memories allow block sized updates
Flexible 3-wire serial digital audio input port
Up to 192 kHz frame rate
Microcontroller write access to Channel
Status and User bit data
On-chip differential line driver
Generates CRC codes and parity bits
Standalone mode allows use without a
microcontroller
28-pin SOIC/TSSOP package
General Description
The CS8406 is a monolithic CMOS device which en-
codes and transmits audio data according to the AES3,
IEC60958, S/PDIF, or EIAJ CP1201. The CS8406 ac-
cepts audio and digital data, which is then multiplexed,
encoded and driven onto a cable.
The audio data is input through a configurable, 3-wire
input port. The channel status and user bit data are input
through an SPI or IC microcontroller port, and may be
assembled in block sized buffers. For systems with no
microcontroller, a stand alone mode allows direct ac-
cess to channel status and user bit data pins.
Target applications include A/V Receivers, CD-R, DVD
receivers, digital mixing consoles, effects processors,
set-top boxes, and computer and automotive audio
systems.
ORDERING INFORMATION
CS8406-CS
28-pin SOIC
-10 to +70C
CS8406-CZ
28-pin TSSOP -10 to +70C
CS8406-IS
28-pin SOIC
-40 to +85C
CS8406-IZ
28-pin TSSOP -40 to +85C
CS8406-DS
28-pin SOIC
-40 to +85C
CS8406-DZ
28-pin TSSOP -40 to +85C
CDB84
16
Evaluation Board
I
Serial
Audio
Input
Misc.
Control
AES3
S/PDIF
Encoder
C & U bit
Data
Buffer
Control
Port &
Registers
Output
Clock
Generator
RXP
ILRCK
ISCLK
SDIN
TXP
TXN
RST
OMCK
U
SDA/
CDOUT
SCL/
CCLK
AD1/
CDIN
AD0/
CS
INT
VL
GND
Driver
AD2
H/S
VD
TCBL
JUL `04
DS580F1
CS8406
2
DS580F1
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5
SPECIFIED OPERATING CONDITIONS ................................................................................. 5
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5
DC ELECTRICAL CHARACTERISTICS................................................................................... 6
DIGITAL INPUT CHARACTERISTICS ..................................................................................... 6
DIGITAL INTERFACE SPECIFICATIONS................................................................................ 6
TRANSMITTER CHARACTERISTICS ..................................................................................... 6
SWITCHING CHARACTERISTICS .......................................................................................... 7
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS................................................. 7
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE...................................... 9
SWITCHING CHARACTERISTICS - CONTROL PORT - IC MODE..................................... 10
2. TYPICAL CONNECTION DIAGRAMS ................................................................................... 11
3. GENERAL DESCRIPTION ..................................................................................................... 13
3.1 AES3 and S/PDIF Standards Documents ........................................................................ 13
4. THREE-WIRE SERIAL INPUT AUDIO PORT ........................................................................ 14
5. AES3 TRANSMITTER ............................................................................................................ 16
5.1 Transmitted Frame and Channel Status Boundary Timing .............................................. 16
5.2 TXN and TXP Drivers ...................................................................................................... 16
5.3 Mono Mode Operation ..................................................................................................... 17
6. CONTROL PORT DESCRIPTION .......................................................................................... 19
6.1. SPI Mode ........................................................................................................................ 19
6.2. IC Mode ......................................................................................................................... 20
6.3. Memory Address Pointer (MAP) ..................................................................................... 21
6.3.1. Memory Address Pointer (MAP) Register Detail ........................................... 21
6.3.2. INCR (Auto Map Increment Enable) .................................................................. 21
6.3.3. MAP6-0 (Memory Address Pointer) ................................................................... 21
7. CONTROL PORT REGISTER SUMMARY ............................................................................. 22
8. CONTROL PORT REGISTER BIT DEFINITIONS .................................................................. 23
8.1 Control 1 (01h) .................................................................................................................. 23
8.2 Control 2 (02h) .................................................................................................................. 24
8.3 Data Flow Control (03h).................................................................................................... 24
8.4 Clock Source Control (04h)............................................................................................... 25
8.5 Serial Audio Input Port Data Format (05h)........................................................................ 25
8.6 Interrupt 1 Status (07h) (Read Only)................................................................................. 26
8.7 Interrupt 2 Status (08h) (Read Only)................................................................................. 27
8.8 Interrupt 1 Mask (09h)....................................................................................................... 27
8.9 Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh) ......................................... 27
8.10 Interrupt 2 Mask (0Ch) .................................................................................................... 27
8.11 Interrupt 2 Mode MSB (0Dh) and Interrupt Mode 2 LSB (0Eh)....................................... 28
8.12 Channel Status Data Buffer Control (12h) ...................................................................... 28
8.13 User Data Buffer Control (13h) ....................................................................................... 29
8.14 Channel Status bit or User bit Data Buffer (20h - 37h) ................................................... 29
8.15 CS8406 I.D. and Version Register (7Fh) (Read Only).................................................... 29
9. PIN DESCRIPTION - SOFTWARE MODE .......................................................................... 30
10. HARDWARE MODE ............................................................................................................. 32
10.1 Channel Status, User and Validity Data ......................................................................... 32
10.2 Serial Audio Port ............................................................................................................ 33
11. PIN DESCRIPTION - HARDWARE MODE .......................................................................... 34
12. APPLICATIONS .................................................................................................................... 36
12.1 Reset, Power Down and Start-up .................................................................................. 36
12.2 ID Code and Revision Code .......................................................................................... 36
CS8406
DS580F1
3
12.3 Power Supply, Grounding, and PCB layout ................................................................... 36
12.4 Synchronization of Multiple CS8406s ............................................................................ 36
13. PACKAGE DIMENSIONS .................................................................................................. 37
14. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER COMPONENTS ...... 39
14.1 AES3 Transmitter External Components ....................................................................... 39
14.2 Isolating Transformer Requirements ............................................................................. 39
15. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........... 40
15.1 AES3 Channel Status(C) Bit Management .................................................................... 40
15.1.1 Accessing the E buffer ...................................................................................... 40
15.1.2 Serial Copy Management System (SCMS) ....................................................... 41
15.1.3 Channel Status Data E Buffer Access .............................................................. 41
15.2 AES3 User (U) Bit Management .................................................................................... 42
15.2.1 Mode 1: Transmit All Zeros ............................................................................... 42
15.2.2 Mode 2: Block Mode ......................................................................................... 42
16. REVISION HISTORY ............................................................................................................ 43
CS8406
4
DS580F1
LIST OF FIGURES
Figure 1. Audio Port Master Mode Timing....................................................................................... 8
Figure 2. Audio Port Slave Mode and Data Input Timing ................................................................ 8
Figure 3. SPI Mode timing ............................................................................................................... 9
Figure 4. IC Mode timing .............................................................................................................. 10
Figure 5. Recommended Connection Diagram for Software Mode............................................... 11
Figure 6. Recommended Connection Diagram for Hardware Mode ............................................. 12
Figure 7. Serial Audio Input Example Formats.............................................................................. 15
Figure 8. AES3 Transmitter Timing for C, U, and V Pin Input Data .............................................. 18
Figure 9. Control Port Timing in SPI Mode.................................................................................... 19
Figure 10. Control Port Timing, IC Slave Mode Write .................................................................. 20
Figure 11. Control Port Timing, IC Slave Mode Read .................................................................. 20
Figure 12. Hardware Mode Data Flow .......................................................................................... 32
Figure 13. Professional Output Circuit .......................................................................................... 39
Figure 14. Consumer Output Circuit (VL = 5.0 V) ......................................................................... 39
Figure 15. TTL/CMOS Output Circuit ............................................................................................ 39
Figure 16. Channel Status Data Buffer Structure .......................................................................... 40
Figure 17. Flowchart for Writing the E Buffer ................................................................................ 41
LIST OF TABLES
Table 1. Control Register Map Summary ...................................................................................... 22
Table 2. Hardware Mode COPY/C and ORIG pin functions.......................................................... 33
Table 3. Hardware Mode Serial Audio Port Format Selection....................................................... 33
Table 4. Hardware Mode OMCK Clock Ratio Selection ................................................................ 33
Table 5. Equivalent Register Settings of Serial Audio Input Formats
Available in Hardware Mode ............................................................................... 33
Table 6. Revision History .............................................................................................................. 43
CS8406
DS580F1
5
1.
CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per-
formance characteristics and specifications are derived from measurements taken at nominal supply voltages and
T
A
= 25C.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V)
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to 0 V. Operation beyond
these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.)
Notes: 1. Transient currents of up to 100 mA will not cause SCR latch-up.
Parameter
Symbol Min
Typ
Max
Units
Power Supply Voltage
VD
VL
3.14
3.14
3.3 or 5.0
3.3 or 5.0
5.25
5.25
V
V
Ambient Operating Temperature:
`-CS' & `-CZ'
`-IS', `-IZ', `-DS', & `-DZ'
T
A
T
A
-10
-40
-
-
+70
+85
C
C
Parameter
Symbol
Min
Max
Units
Power Supply Voltage
VD, VL
-
6.0
V
Input Current, Any Pin Except Supplies
(Note 1)
I
in
-
10
mA
Input Voltage
V
in
-0.3
VL + 0.3
V
Ambient Operating Temperature (power applied)
T
A
-55
125
C
Storage Temperature
T
stg
-65
150
C
CS8406
6
DS580F1
DC ELECTRICAL CHARACTERISTICS
(GND = 0 V; all voltages with respect to 0 V.)
Notes: 2. Power Down Mode is defined as RST = LO with all clocks and data lines held static.
3. Normal operation is defined as RST = HI.
4. Assumes that no inputs are left floating. It is recommended that all digital inputs be driven high or low
at all times.
DIGITAL INPUT CHARACTERISTICS
DIGITAL INTERFACE SPECIFICATIONS
(GND = 0 V; all voltages with respect to 0 V.)
TRANSMITTER CHARACTERISTICS
Parameters
Symbol
Min
Typ
Max
Units
Power-down Mode
(Note 2)
Supply Current in power down
VD = 3.3 V
VD = 5.0 V
VL = 3.3 V
VL = 5.0 V
ID
ID
IL
IL
-
-
-
-
20
40
0
0
-
-
-
-
A
A
A
A
Normal Operation
(Note 3)
Supply Current at 48 kHz frame rate (Note 4)
VD = 3.3 V
VD = 5.0 V
VL = 3.3 V
VL = 5.0 V
ID
ID
IL
IL
-
-
-
-
1.9
3.5
6.5
10.6
-
-
-
-
mA
mA
mA
mA
Supply Current at 192 kHz frame rate (Note 4)
VD = 3.3 V
VD = 5.0 V
VL = 3.3 V
VL = 5.0 V
ID
ID
IL
IL
-
-
-
-
7.6
12.7
7.2
12
-
-
-
-
mA
mA
mA
mA
Parameters
Symbol Min Typ
Max
Units
Input Leakage Current
I
in
-
-
0.5
A
Input Hysteresis (all inputs except OMCK)
-
0.25
-
V
Parameters
Symbol Min
Max
Units
High-Level Output Voltage (I
OH
= -3.2 mA), except TXP/TXN
V
OH
VL - 1.0
-
V
Low-Level Output Voltage (I
OH
= 3.2 mA), except TXP/TXN
V
OL
-
0.4
V
High-Level Output Voltage, TXP, TXN
(21 mA at VL = 5.0 V)
(15 mA at VL = 3.3 V)
VL - 0.7
VL - 0.7
VL
VL
V
V
Low-Level Output Voltage, TXP, TXN
(21 mA at VL = 5.0 V)
(16 mA at VL = 3.3 V)
-
-
0.7
0.7
V
V
High-Level Input Voltage
VD = 5.0 V
VD = 3.3 V
V
IH
2.75
2.0
VL + 0.3
VL + 0.3
V
V
Low-Level Input Voltage
VD = 5.0 V
VD = 3.3 V
V
IL
-0.3
-0.3
0.8
0.8
V
V
Parameters
Symbol Typ
Units
TXP Output Resistance
VL = 5.0 V
VL = 3.3 V
R
TXP
26.5
33.5
TXN Output Resistance
VL = 5.0 V
VL = 3.3 V
R
TXN
26.5
33.5
CS8406
DS580F1
7
SWITCHING CHARACTERISTICS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C
L
= 20 pF)
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C
L
= 20 pF)
Notes: 5. The active edge of ISCLK is programmable in Software mode.
6. The polarity of ILRCK is programmable in Software mode.
7. Prevents the previous ISCLK edge from being interpreted as the first one after ILRCK has changed.
8. This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed.
Parameter
Symbol Min Typ
Max
Units
RST pin Low Pulse Width
200
-
-
s
OMCK Frequency for OMCK = 512*Fs
4.1
-
98.4
MHz
OMCK Low and High Width for OMCK = 512*Fs
4.1
-
-
ns
OMCK Frequency for OMCK = 384*Fs
3.1
-
73.8
MHz
OMCK Low and High Width for OMCK = 384*Fs
6.1
-
-
ns
OMCK Frequency for OMCK = 256*Fs
2.0
-
49.2
MHz
OMCK Low and High Width for OMCK = 256*Fs
8.1
-
-
ns
OMCK Frequency for OMCK = 128*Fs
1.0
-
24.6
MHz
OMCK Low and High Width for OMCK = 128*Fs
18.3
-
-
ns
Frame Rate
8
-
192
kHz
AES3 Transmitter Output Jitter
-
200
-
ps
Parameter
Symbol Min Typ
Max
Units
SDIN Setup Time Before ISCLK Active Edge
(Note 5)
t
ds
10
-
-
ns
SDIN Hold Time After ISCLK Active Edge
(Note 5)
t
dh
8
-
-
ns
Master Mode
OMCK to ISCLK active edge delay
(Note 5)
t
smd
0
-
17
ns
OMCK to ILRCK delay
(Note 6)
t
lmd
0
-
16
ns
ISCLK and ILRCK Duty Cycle
-
50
-
%
Slave Mode
ISCLK Period
t
sckw
36
-
-
ns
ISCLK Input Low Width
t
sckl
14.4
-
-
ns
ISCLK Input High Width
t
sckh
14.4
-
-
ns
ISCLK Active Edge to ILRCK Edge
(Note 7)
t
lrckd
10
-
-
ns
ILRCK Edge Setup Before ISCLK Active Edge
(Note 8)
t
lrcks
10
-
-
ns
CS8406
8
DS580F1
ISCLK
ILRCK
(output)
(output)
OMCK
(input)
t smd
t
lmd
sckh
sckl
sckw
t
t
t
(input)
(input)
SDIN
dh
t
ds
t
lrcks
t
lrckd
t
ISCLK
ILRCK
Figure 1. Audio Port Master Mode Timing
Figure 2. Audio Port Slave Mode and Data Input
Timing
CS8406
DS580F1
9
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C
L
= 20 pF)
Notes: 9. If Fs is lower than 51.850 kHz, the maximum CCLK frequency should be less than 115 Fs. This is
dictated by the timing requirements necessary to access the Channel Status and User Bit buffer
memory. Access to the control register file can be carried out at the full 6 MHz rate.
10. T
sch
must be greater than the larger of the two values, either 1/256FS + 8 ns, or 66 ns.
11. Data must be held for sufficient time to bridge the transition time of CCLK.
12. For f
sck
< 1 MHz.
Parameter
Symbol Min Typ
Max
Units
CCLK Clock Frequency
(Note 9)
f
sck
0
-
6.0
MHz
CS High Time Between Transmissions
t
csh
1.0
-
-
s
CS Falling to CCLK Edge
t
css
20
-
-
ns
CCLK Low Time
t
scl
66
-
-
ns
CCLK High Time
(Note 10)
t
sch
MAX ((1/256 F
S
+ 8), 66)
ns
CDIN to CCLK Rising Setup Time
t
dsu
40
-
-
ns
CCLK Rising to DATA Hold Time
(Note 11)
t
dh
15
-
-
ns
CCLK Falling to CDOUT Stable
t
pd
-
-
50
ns
Rise Time of CDOUT
t
r1
-
-
25
ns
Fall Time of CDOUT
t
f1
-
-
25
ns
Rise Time of CCLK and CDIN
(Note 12)
t
r2
-
-
100
ns
Fall Time of CCLK and CDIN
(Note 12)
t
f2
-
-
100
ns
t r2
t f2
t dsu
t dh
t sch
t scl
CS
CCLK
CDIN
t css
t pd
CDOUT
t csh
Figure 3. SPI Mode timing
CS8406
10
DS580F1
SWITCHING CHARACTERISTICS - CONTROL PORT - IC MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C
L
= 20 pF)
13. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Parameter
Symbol Min Typ
Max
Units
SCL Clock Frequency
f
scl
-
-
100
kHz
Bus Free Time Between Transmissions
t
buf
4.7
-
-
s
Start Condition Hold Time (prior to first clock pulse)
t
hdst
4.0
-
-
s
Clock Low Time
t
low
4.7
-
-
s
Clock High Time
t
high
4.0
-
-
s
Setup Time for Repeated Start Condition
t
sust
4.7
-
-
s
SDA Hold Time from SCL Falling
(Note 13)
t
hdd
0
-
-
s
SDA Setup Time to SCL Rising
t
sud
250
-
-
ns
Rise Time of Both SDA and SCL Lines
t
r
-
-
1000
ns
Fall Time of Both SDA and SCL Lines
t
f
-
-
300
ns
Setup Time for Stop Condition
t
susp
4.7
-
-
s
t buf
t
hdst
t
hdst
t
low
t r
t f
t
hdd
t high
t sud
t sust
t susp
Stop
Start
Start
Stop
Repeated
SDA
SCL
Figure 4. IC Mode timing
CS8406
DS580F1
11
2.
TYPICAL CONNECTION DIAGRAMS
CS8406
+3.3 V or +5.0 V
GND
RXP
ILRCK
ISCLK
SDIN
AES3 /
S/PDIF
Source
Microcontroller
SCL / CCLK
SDA / CDOUT
RST
AD1 / CDIN
VD
VL
TXP
0.1 F
AD0 / CS
Serial
Audio
Source
Clock Source
and Control
OMCK
AD2
TXN
H/S
TCBL
To/from other
CS8406's
INT
47k
U
Transmission
Interface
User Data
Source
+3.3 V or +5.0 V
0.1 F
Figure 5. Recommended Connection Diagram for Software Mode
CS8406
12
DS580F1
CS8406
+3.3 V or +5.0 V
GND
ILRCK
ISCLK
SDIN
Hardware
Control
APMS
TCBLD
RST
SFMT0
VD
VL
TXP
0.1 F
Serial
Audio
Source
Clock Source
and Control
OMCK
SFMT1
TXN
H/S
TCBL
To/from other
CS8406's
CEN
47k
U
Transmission
Interface
User Data
Source
EMPH
AUDIO
ORIG
V
Validity
Source
+3.3 V or +5.0 V
0.1 F
47k
C Data
Source
COPY/C
HWCK1
HWCK0
Figure 6. Recommended Connection Diagram for Hardware Mode
CS8406
DS580F1
13
3. GENERAL DESCRIPTION
The CS8406 is a monolithic CMOS device which encodes and transmits audio data according to
the AES3, IEC60958, S/PDIF, and EIAJ CP1201 interface standards. The CS8406 accepts au-
dio, channel status and user data, which is then multiplexed, encoded, and driven onto a cable.
The audio data is input through a configurable, 3-wire input port. The channel status bits and user
bit data are input through an SPI or IC Mode microcontroller port and may be assembled in sep-
arate block sized buffers.
For systems with no microcontroller, a stand alone mode allows direct access to channel status
and user data input pins.
Target applications include CD-R, DAT, DVD, MD and VTR equipment, mixing consoles, digital
audio transmission equipment, high quality A/D converters, effects processors, set-top TV box-
es, and computer audio systems.
Figure 5 shows the supply and external connections to the CS8406 when configured for opera-
tion with a microcontroller. Figure 6 shows the supply and external connections to the CS8406
when configured for operation without a microcontroller.
3.1
AES3 and S/PDIF Standards Documents
This data sheet assumes that the user is familiar with the AES3 and S/PDIF data formats. It is
advisable to have current copies of the AES3 and IEC60958 specifications on hand for easy ref-
erence.
The latest AES3 standard is available from the Audio Engineering Society or ANSI at
www.aes.org or www.ansi.org. Obtain the latest IEC60958 standard from ANSI or from the Inter-
national Electrotechnical Commission at www.iec.ch. The latest EIAJ CP-1201 standard is avail-
able from the Japanese Electronics Bureau.
Application Note 22:
Overview of Digital Audio Interface Data Structures contains a useful tutorial
on digital audio specifications, but it should not be considered a substitute for the standards.
The paper
An Understanding and Implementation of the SCMS Serial Copy Management Sys-
tem for Digital Audio Transmission, by Clifton Sanchez, is an excellent tutorial on SCMS. It is
available from the AES as reprint 3518.
CS8406
14
DS580F1
4. THREE-WIRE SERIAL INPUT AUDIO PORT
A 3-wire serial audio input port is provided. The interface format can be adjusted to suit the at-
tached device through the control registers. The following parameters are adjustable:
Master or slave
Serial clock frequency
Audio data resolution
Left or right justification of the data relative to left/right clock
Optional one-bit cell delay of the first data bit
Polarity of the bit clock
Polarity of the left/right clock. (By setting the appropriate control bits, many formats are pos-
sible).
Figure 7 shows a selection of common input formats with the corresponding control bit settings.
In master mode, the left/right clock and the serial bit clock are outputs, derived from the OMCK
input pin master clock.
In slave mode, the left/right clock and the serial bit clock are inputs. The left/right clock must be
synchronous to the OMCK master clock, but the serial bit clock can be asynchronous and dis-
continuous if required. The left/right clock should be continuous, but the duty cycle can be less
than the specified typical value of 50% if enough serial clocks are present in each phase to clock
all the data bits.
CS8406
DS580F1
15
ILRCK
ISCLK
SDIN
2
Left
Justified
(In)
MSB
LSB
Left
Right
MSB
I S
(In)
Right
Justified
(In)
MSB
LSB
MSB
LSB
MSB
Left
Right
MSB
LSB
MSB
LSB
Left
Right
LSB
MSB
LSB
ILRCK
ISCLK
SDIN
ILRCK
ISCLK
SDIN
Figure 7. Serial Audio Input Example Formats
X = don't care to match format, but does need to be set to the desired setting
+ IS can accept an arbitrary number of bits, determined by the number of ISCLK cycles
* See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit
SIMS*
SISF*
SIRES[1:0]*
SIJUST*
SIDEL*
SISPOL*
SILRPOL*
Left Justified
X
X
00+
0
0
0
0
IS
X
X
00+
0
1
0
1
Right Justified
X
X
XX
1
0
0
0
CS8406
16
DS580F1
5. AES3 TRANSMITTER
The CS8406 includes an AES3 digital audio transmitter. A comprehensive buffering scheme pro-
vides write access to the channel status and user data. This buffering scheme is described in
Appendix B: Channel Status and User Data Buffer Management.
The AES3 transmitter encodes and transmits audio and digital data according to the AES3,
IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. Audio and control data are multi-
plexed together and bi-phase mark encoded. The resulting bit stream is driven to an output con-
nector either directly or through a transformer. The transmitter is clocked from the clock input pin,
OMCK. If OMCK is asynchronous to the data source, an interrupt bit (TSLIP) is provided that will
go high every time a data sample is dropped or repeated.
The channel status (C) and user (U) bits in the transmitted data stream are taken from storage
areas within the CS8406. The user can manually access the internal storage or configure the
CS8406 to run in one of several automatic modes. Appendix B: Channel Status and User Data
Buffer Management provides detailed descriptions of each automatic mode and describes meth-
ods of manually accessing the storage areas. The transmitted user bit data can optionally be in-
put through the U pin, under the control of a control port register bit.
Figure 8 shows the C/U/V timing requirements.
5.1
Transmitted Frame and Channel Status Boundary Timing
The TCBL pin is used to control or indicate the start of transmitted channel status block bound-
aries and may be an input or an output.
In some applications, it may be necessary to control the precise timing of the transmitted AES3
frame boundaries. This may be achieved in two ways:
a) With TCBL set to input, driving TCBL high for >3 OMCK clocks will cause a frame start, as well
as a new channel status block start.
b) If the serial audio input port is in slave mode and TCBL is set to output, the start of the A chan-
nel sub-frame will be aligned with the leading edge of ILRCK.
5.2
TXN and TXP Drivers
The line drivers are low skew, low impedance, differential outputs capable of driving cables di-
rectly. Both drivers are set to ground during reset (RST = LOW), when no AES3 transmit clock
is provided, and optionally under the control of a register bit. The CS8406 also allows immediate
muting of the AES3 transmitter audio data through a control register bit.
External components are used to terminate and isolate the external cable from the CS8406.
These components are detailed in "Appendix A: External AES3/SPDIF/IEC60958 Transmitter
Components" on page 39.
CS8406
DS580F1
17
5.3
Mono Mode Operation
An alternate method for transmitting an AES3 192 kHz sample rate stream is mono mode. Mono
mode is implemented by using the two sub-frames in a 96 kHz biphase encoded stream to carry
consecutive samples of a single channel of a 192 kHz PCM stream (i.e. a mono signal). This al-
lows older equipment, whose AES3 transmitters and receivers are not rated for 192 kHz frame
rate operation, to handle 192 kHz sample rate information. In this mono mode, two AES3 cables
and two CS8406's are needed for stereo data transfer. The CS8406 is set to mono mode by the
MMT control bit.
In mono mode, the input port will run at the audio sample rate (Fs), while the AES3 transmitter
frame rate will be at Fs/2. Consecutive left or right channel serial audio data samples may be se-
lected for transmission on the A and B sub-frames, and the channel status block transmitted is
also selectable.
Using mono mode is only necessary if the incoming audio sample rate is already at 192 kHz and
contains both left and right audio data words. The "mono mode" AES3 output stream may also
be achieved by keeping the CS8406 in normal stereo mode, and placing consecutive audio sam-
ples in the left and right positions in an incoming 96 kHz word rate data stream.
Figure 8 shows the C/U/V timing requirements.
CS8406
18
DS580F1
AES3 Transmitter in Stereo mode
U[0]
U[2]
Data [4]
Data [5]
Data [6]
Data [7]
Data [8]
Data [0]*
Data [2]*
Data [4]*
Z
Y
X
* Assume MMTLR = 0
Data [1]*
Data [3]*
Data [5]*
Z
Y
X
* Assume MMTLR = 1
VLRCK is a virtual word clock, which may not exist, and is used to illustrate the CUV timing.
VLRCK duty cycle is 50%.
In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, VLRCK frequency = 2xAES3 frame rate.
If the serial audio input port is on slave mode and TCBL is an output, then VLRCK = ILRCK if SILRPOL = 0
and VLRCK = ILRCK if SILRPOL =1.
If the serial audio input port is in master mode and TCBL is an input, then VLRCK = ILRCK if SILRPOL = 0
and VLRCK = ILRCK if SILRPOL =1.
Tth
VCU[0]
VCU[1]
VCU[2]
VCU[3]
VCU[4]
VLRCK
V/C/U
(Input)
Data [4]
Data [5]
Data [6]
Data [7]
Data [8]
SDIN
(Input)
Data [0]
Data [1]
Data [2]
Data [3]
Data [4]
TXP(N)
(Output)
Z
Y
X
Y
X
Tsetup
Thold
Tth
Thold = 0
Tth > 3 OMCK clocks, if TCBL is Input
Tsetup
7.5% AES3 frame time
TCBL
(In/Output)
VLRCK
U
(Input)
SDIN
(Input)
TXP(N)
(Output)
TCBL
(In/Output)
TXP(N)
(Output)
AES3 Transmitter in Mono mode
Thold = 0
Tth > 3 OMCK clocks, if TCBL is Input
Tsetup
15% AES3 frame time
Figure 8. AES3 Transmitter Timing for C, U, and V Pin Input Data
CS8406
DS580F1
19
6.
CONTROL PORT DESCRIPTION
The control port is used to access the registers, allowing the CS8406 to be configured for the
desired operational modes and formats. The operation of the control port may be completely
asynchronous with respect to the audio sample rates. However, to avoid potential interference
problems, the control port pins should remain static if no operation is required.
The control port has 2 modes: SPI and IC, with the CS8406 acting as a slave device. SPI mode
is selected if there is a high to low transition on the AD0/CS pin, after the RST pin has been
brought high. IC mode is selected by connecting the AD0/CS pin through a resistor to VL or
GND, thereby permanently selecting the desired AD0 bit address state.
6.1.
SPI Mode
In SPI mode, CS is the CS8406 chip select signal, CCLK is the control port bit clock (input into
the CS8406 from the microcontroller), CDIN is the input data line from the microcontroller, CD-
OUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK
and out on the falling edge.
Figure 9 shows the operation of the control port in SPI mode. To write to a register, bring CS low.
The first seven bits on CDIN form the chip address and must be 0010000. The eighth bit is a
read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Ad-
dress Pointer (MAP), which is set to the address of the register that is to be updated. The next
eight bits are the data which will be placed into the register designated by the MAP. During writes,
the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 k
resistor, if desired.
There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR
is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP
will autoincrement after each byte is read or written, allowing block reads or writes of successive
registers.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle
which finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR)
may be set or not, as desired. To begin a read, bring CS low, send out the chip address and set
M A P
MSB
LSB
DATA
b y te 1
b y te n
R/W
R/W
A D D R E S S
C H IP
ADDRESS
C H I P
C D I N
C C L K
CS
C D O U T
MSB
LSB MSB
LSB
0010000
0010000
MAP = Memory Address Pointer, 8 bits, MSB first
High Impedance
Figure 9. Control Port Timing in SPI Mode
CS8406
20
DS580F1
the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the ad-
dressed register (CDOUT will leave the high impedance state). If the MAP auto increment bit is
set to 1, the data for successive registers will appear consecutively.
6.2.
IC Mode
In IC mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock,
SCL. There is no CS pin. Pins AD0, AD1, and AD2 form the three least significant bits of the chip
address and should be connected through a resistor to VL or GND as desired.
The signal timings for a read and write cycle are shown in Figure 10 and Figure 11. A Start con-
dition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising
transition while the clock is high. All other transitions of SDA occur while the clock is low. The first
byte sent to the CS8406 after a Start condition consists of a 7 bit chip address field and a R/W
bit (high for a read, low for a write). The upper 4 bits of the 7-bit address field are fixed at 0010.
To communicate with a CS8406, the chip address field, which is the first byte sent to the CS8406,
should match 0010 followed by the settings of the AD2, AD1, and AD0 pins. The eighth bit of the
address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer
(MAP) which selects the register to be read or written. If the operation is a read, the contents of
the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows
successive reads or writes of consecutive registers. Each byte is separated by an acknowledge
bit (ACK). The ACK bit is output from the CS8406 after each input byte is read, and is input to
the CS8406 from the microcontroller after each transmitted byte.
Since the read operation can not set the MAP, an aborted write operation is used as a preamble.
As shown in Figure 11, the write operation is aborted after the acknowledge for the MAP byte by
sending a stop condition. The following pseudocode illustrates an aborted write operation fol-
lowed by a read operation.
4 5 6 7
24 25
SCL
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
START
ACK
STOP
ACK
ACK
ACK
0 0 1 0 AD2 AD1 AD0 0
SDA
INCR
6 5 4 3 2 1 0
7 6 1 0
7 6 1 0
7 6 1 0
0 1 2 3
8 9
12
16 17 18 19
10 11
13 14 15
27 28
26
DATA +n
Figure 10. Control Port Timing, IC Slave Mode Write
SCL
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
START
ACK
STOP
ACK
ACK
ACK
SDA
CHIP ADDRESS (READ)
START
INCR
6 5 4 3 2 1 0
7 0
7 0
7 0
NO
16
8 9
12 13 14 15
4 5 6 7
0 1
20 21 22 23 24
26 27 28
2 3
10 11
17 18 19
25
ACK
DATA + n
STOP
0 0 1 0 AD2 AD1 AD0 0
0 0 1 0 AD2 AD1 AD0 1
Figure 11. Control Port Timing, IC Slave Mode Read
CS8406
DS580F1
21
Send start condition.
Send 0010xxx0 (chip address & write operation).
Receive acknowledge (ACK) bit.
Send MAP byte, auto increment off.
Receive ACK bit.
Send stop condition, aborting write.
Send start condition.
Send 0010xxx(chip address & read operation).
Receive ACK bit.
Receive byte, contents of selected register.
Send no acknowledge (NO ACK) bit.
Send stop condition.
Setting the auto increment bit in the MAP allows successive reads or writes of consecutive reg-
isters. Each byte is separated by an acknowledge bit.
6.3.
Memory Address Pointer (MAP)
6.3.1.
Memory Address Pointer (MAP) Register Detail
6.3.2.
INCR (Auto Map Increment Enable)
Default = `0'
0 - Disabled, the MAP will stay constant for successive writes
1 - Enabled, the MAP will auto increment after each byte is written, allowing block reads
or writes of successive registers
6.3.3.
MAP6-0 (Memory Address Pointer)
Default = `0000000'
7
6
5
4
3
2
1
0
INCR
MAP6
MAP5
MAP4
MAP3
MAP2
MAP1
MAP0
CS8406
22
DS580F1
7.
CONTROL PORT REGISTER SUMMARY
Notes:
Reserved registers must not be written to during normal operation. Some reserved registers are used
for test modes, which can completely alter the normal operation of the CS8406.
Addr
(HEX)
Function
7
6
5
4
3
2
1
0
00
Reserved
0
0
0
0
0
0
0
0
01
Control 1
0
VSET
0
MUTEAES
0
INT1
INT0
TCBLD
02
Control 2
0
0
0
0
0
MMT
MMCST
MMTLR
03
Data Flow Control
0
TXOFF
AESBP
0
0
0
0
0
04
Clock Source Control
0
RUN
CLK1
CLK0
0
0
0
0
05
Serial Input Format
SIMS
SISF
SIRES1
SIRES0
SIJUST
SIDEL
SISPOL SILRPOL
06
Reserved
0
0
0
0
0
0
0
0
07
Interrupt 1 Status
TSLIP
0
0
0
0
0
EFTC
0
08
Interrupt 2 Status
0
0
0
0
0
EFTU
0
0
09
Interrupt 1 Mask
TSLIPM
0
0
0
0
0
EFTCM
0
0A
Interrupt 1 Mode (MSB) TSLIP1
0
0
0
0
0
EFTC1
0
0B
Interrupt 1 Mode (LSB)
TSLIP0
0
0
0
0
0
EFTC0
0
0C
Interrupt 2 Mask
0
0
0
0
0
EFTUM
0
0
0D
Interrupt 2 Mode (MSB)
0
0
0
0
0
EFTU1
0
0
0E
Interrupt 2 Mode (LSB)
0
0
0
0
0
EFTU0
0
0
0F-11 Reserved
0
0
0
0
0
0
0
0
12
CS Data Buffer Control
0
0
BSEL
0
0
EFTCI
CAM
0
13
U Data Buffer Control
0
0
0
UD
UBM1
UBM0
0
EFTUI
1D-1F Reserved
0
0
0
0
0
0
0
0
20-37 C or U Data Buffer
7F
ID and Version
ID3
ID2
ID1
ID0
VER3
VER2
VER1
VER0
Table 1. Control Register Map Summary
CS8406
DS580F1
23
8.
CONTROL PORT REGISTER BIT DEFINITIONS
8.1
Control 1 (01h)
VSET - Transmitted Validity bit level
Default = `0'
0 - Indicates data is valid, linear PCM audio data
1 - Indicates data is invalid or not linear PCM audio data
MUTEAES - Mute control for the AES transmitter output
Default = `0'
0 - Not Muted
1 - Muted
INT1:0 - Interrupt output pin (INT) control
Default = `00'
00 - Active high; high output indicates interrupt condition has occurred
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.
11 - Reserved
TCBLD - Transmit Channel Status Block pin (TCBL) direction specifier
Default = `0'
0 - TCBL is an input
1 - TCBL is an output
7
6
5
4
3
2
1
0
0
VSET
0
MUTEAES
0
INT1
INT0
TCBLD
CS8406
24
DS580F1
8.2
Control 2 (02h)
MMT - Select AES3 transmitter mono or stereo operation
Default = `0'
0 - Normal stereo operation
1 - Output either left or right channel inputs into consecutive subframe outputs (mono
mode, left or right is determined by MMTLR bit)
MMTCS - Select A or B channel status data to transmit in mono mode
Default = `0'
0 - Use channel A CS data for the A subframe and use channel B CS data for the B subframe
1 - Use the same CS data for both the A and B subframe outputs. If MMTLR = 0, use the
left channel CS data. If MMTLR = 1, use the right channel CS data.
MMTLR - Channel Selection for AES Transmitter mono mode
Default = `0'
0 - Use left channel input data for consecutive subframe outputs
1- Use right channel input data for consecutive subframe outputs
8.3
Data Flow Control (03h)
The Data Flow Control register configures the flow of audio data. The output data should be muted prior to changing
bits in this register to avoid transients.
TXOFF - AES3 Transmitter Output Driver Control
Default = `0
0 - AES3 transmitter output pin drivers normal operation
1 - AES3 transmitter output pin drivers drive to 0 V.
AESBP - AES3 bypass mode selection
Default = `0'
0 - Normal operation
1 - Connect the AES3 transmitter driver input directly to the RXP pin, which becomes a normal TTL
threshold digital input.
7
6
5
4
3
2
1
0
0
0
0
0
0
MMT
MMTCS
MMTLR
7
6
5
4
3
2
1
0
0
TXOFF
AESBP
0
0
0
0
0
CS8406
DS580F1
25
8.4
Clock Source Control (04h)
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, var-
ious Receiver/Transmitter/Transceiver modes may be selected.
RUN - Controls the internal clocks, allowing the CS8406 to be placed in a "powered down" low
current consumption, state.
Default = `0'
0 - Internal clocks are stopped. Internal state machines are reset. The fully static
control port registers are operational, allowing registers to be read or changed. Reading and
writing the U and C data buffers is not possible. Power consumption is low.
1 - Normal part operation. This bit must be set to 1 to allow the CS8406 to begin operation.
All input clocks should be stable in frequency and phase when RUN is set to 1.
CLK1:0 - Output master clock (OMCK) input frequency to output sample rate (Fs) ratio selector.
If these bits are changed during normal operation, then always stop the CS8406 first (RUN = 0),
write the new value, then start the CS8406 (RUN = 1).
Default = `00'
00 - OMCK frequency is 256*Fs
01 - OMCK frequency is 384*Fs
10 - OMCK frequency is 512*Fs
11 - OMCK frequency is 128*Fs
8.5
Serial Audio Input Port Data Format (05h)
SIMS - Master/Slave Mode Selector
Default = `0'
0 - Serial audio input port is in slave mode
1 - Serial audio input port is in master mode
SISF - ISCLK frequency (for master mode)
Default = `0'
0 - 64*Fs
1 - 128*Fs
SIRES1:0 - Resolution of the input data, for right-justified formats
Default = `00'
00 - 24-bit resolution
01 - 20-bit resolution
10 - 16-bit resolution
11 - Reserved
7
6
5
4
3
2
1
0
0
RUN
CLK1
CLK0
0
0
0
0
7
6
5
4
3
2
1
0
SIMS
SISF
SIRES1
SIRES0
SIJUST
SIDEL
SISPOL
SILRPOL
CS8406
26
DS580F1
SIJUST - Justification of SDIN data relative to ILRCK
Default = `0'
0 - Left-justified
1 - Right-justified
SIDEL - Delay of SDIN data relative to ILRCK, for left-justified data formats
Default = `0'
0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge (left justified mode)
1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge (IS mode)
SISPOL - ISCLK clock polarity
Default = `0'
0 - SDIN sampled on rising edges of ISCLK
1 - SDIN sampled on falling edges of ISCLK
SILRPOL - ILRCK clock polarity
Default = `0'
0 - SDIN data is for the left channel when ILRCK is high
1 - SDIN data is for the right channel when ILRCK is high
8.6
Interrupt 1 Status (07h) (Read Only)
For all bits in this register, a `1' means the associated interrupt condition has occurred at least once since the register
was last read. A `0' means the associated interrupt condition has NOT occurred since the last reading of the register.
Reading the register resets all bits to `0', unless the interrupt mode is set to level and the interrupt source is still true.
Status bits that are masked off in the associated mask register will always be `0' in this register. This register defaults
to 00h.
TSLIP - AES3 transmitter source data slip interrupt
In data flows where OMCK, which clocks the AES3 transmitter, is asynchronous to the data source,
this bit will go high every time a data sample is dropped or repeated. When TCBL is an input, this bit
will go high on receipt of a new TCBL signal.
EFTC - E to F C-buffer transfer interrupt.
The source for this bit is true during the E to F buffer transfer in the C bit buffer management process.
7
6
5
4
3
2
1
0
TSLIP
0
0
0
0
0
EFTC
0
CS8406
DS580F1
27
8.7
Interrupt 2 Status (08h) (Read Only)
For all bits in this register, a `1' means the associated interrupt condition has occurred at least once since the register
was last read. A `0' means the associated interrupt condition has NOT occurred since the last reading of the register.
Reading the register resets all bits to `0', unless the interrupt mode is set to level and the interrupt source is still true.
Status bits that are masked off in the associated mask register will always be `0' in this register. This register defaults
to 00h.
EFTU - E to F U-buffer transfer interrupt. (Block Mode only)
The source of this bit is true during the E to F buffer transfer in the U bit buffer management process.
8.8
Interrupt 1 Mask (09h)
The bits of this register serve as a mask for the Interrupt 1 register. If a mask bit is set to 1, the error is unmasked,
meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked,
meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corre-
sponding bits in Interrupt 1 register. This register defaults to 00h.
8.9
Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh)
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to
set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin be-
comes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active
on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the in-
terrupt condition. Be aware that the active level (Active High or Low) only depends on the INT[1:0] bits. These reg-
isters default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
8.10
Interrupt 2 Mask (0Ch)
The bits of this register serve as a mask for the Interrupt 2 register. If a mask bit is set to 1, the error is unmasked,
meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked,
meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corre-
sponding bits in Interrupt 2 register. This register defaults to 00h.
7
6
5
4
3
2
1
0
0
0
0
0
0
EFTU
0
0
7
6
5
4
3
2
1
0
TSLIPM
0
0
0
0
0
EFTCM
0
7
6
5
4
3
2
1
0
TSLIP1
0
0
0
0
0
EFTC1
0
TSLIP0
0
0
0
0
0
EFTC0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
EFTUM
0
0
CS8406
28
DS580F1
8.11
Interrupt 2 Mode MSB (0Dh) and Interrupt Mode 2 LSB (0Eh)
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to
set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin be-
comes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active
on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the in-
terrupt condition. Be aware that the active level (Active High or Low) only depends on the INT[1:0] bits. These reg-
isters default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
8.12
Channel Status Data Buffer Control (12h)
BSEL - Selects the data buffer register addresses to contain User data or Channel Status data
Default = `0'
0 - Data buffer address space contains Channel Status data
1 - Data buffer address space contains User data
Note:
There are separate complete buffers for the Channel Status and User bits. This control bit determines which
buffer appears in the address space.
EFTCI - E to F C-data buffer transfer inhibit bit.
Default = `0'
0 - Allow C-data E to F buffer transfers
1 - Inhibit C-data E to F buffer transfers
CAM - C-data buffer control port access mode bit
Default = `0'
0 - One byte mode
1 - Two byte mode
7
6
5
4
3
2
1
0
0
0
0
0
0
EFTU1
0
0
0
0
0
0
0
EFTU0
0
0
7
6
5
4
3
2
1
0
0
0
BSEL
0
0
EFTCI
CAM
0
CS8406
DS580F1
29
8.13
User Data Buffer Control (13h)
UD - User bit data source specifier
Default = `0'
0 - U Pin is the source of transmitted U data
1 - U data buffer is the source of transmitted U data
UBM1:0 - Sets the operating mode of the AES3 User bit manager
Default = `00'
00 - Transmit all zeros mode
01 - Block mode
10 - Reserved
11 - Reserved
EFTUI - E to F U-data buffer transfer inhibit bit (valid in block mode only).
Default = `0'
0 - Allow U-data E to F buffer transfers
1 - Inhibit U-data E to F buffer transfers
8.14
Channel Status bit or User bit Data Buffer (20h - 37h)
Either the channel status data buffer E or the separate user bit data buffer E (provided UBM bits are set to block
mode) is accessible through these register addresses.
8.15
CS8406 I.D. and Version Register (7Fh) (Read Only)
ID[3:0] - ID code for the CS8406. Permanently set to 1110
VER[3:0] = 0001 (revision A)
VER[3:0] = 0010 (revision B)
7
6
5
4
3
2
1
0
0
0
0
UD
UBM1
UBM0
0
EFTUI
7
6
5
4
3
2
1
0
ID3
ID2
ID1
ID0
VER3
VER2
VER1
VER0
CS8406
30
DS580F1
9. PIN DESCRIPTION - SOFTWARE MODE
VD
6
Digital Power (
Input) - Digital core power supply. Typically +3.3 V or +5.0 V.
VL
23
Logic Power (
Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
GND
22
Ground
(
Input) - Ground for I/O and core logic.
RST
9
Reset (
Input) - When RST is low, the CS8406 enters a low power mode and all internal states are reset.
On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable
in frequency and phase. This is particularly true in hardware mode with multiple CS8406 devices, where
synchronization between devices is important.
H/S
24
Hardware/Software Control Mode Select (
Input) -Determines the method of controlling the operation
of the CS8406, and the method of accessing CS and U data. In software mode, device control and CS
and U data access is primarily through the control port, using a microcontroller. To select Software
mode, this pin should be permanently tied to GND.
TXN
TXP
25
26
Differential Line Drivers (
Output) - These pins transmit biphase encoded data. The drivers are pulled
low while the CS8406 is in the reset state.
OMCK
21
Master Clock (
Input) - The frequency can be set through the control port registers.
ISCLK
13
Serial Audio Bit Clock (
Input/Output) - Serial bit clock for audio data on the SDIN pin.
ILRCK
12
Serial Audio Input Left/Right Clock (
Input/Output) - Word rate clock for the audio data on the SDIN
pin.
SDIN
14
Serial Audio Data Port (
Input) - Audio data serial input pin.
SDA / CDOUT
SCL / CCLK
AD0 / CS
AD1 / CDIN
AD2
TXP
RXP
TXN
TEST
H/S
VD
VL
TEST
GND
TEST
OMCK
RST
U
TEST
INT
TEST
TEST
ILRCK
TEST
ISCLK
TEST
SDIN
TCBL
1
2
3
4
5
6
7
8
21
22
23
24
25
26
27
28
9
10
11
12
17
18
19
20
13
14
15
16
CS8406
DS580F1
31
SDA/CDOUT
1
Serial Control Data I/O (IC Mode) / Data Out (SPI) (
Input/Output) - In IC Mode, SDA is the control I/O
data line. SDA is open drain and requires an external pull-up resistor to VL. In SPI mode, CDOUT is the
output data from the control port interface on the CS8406
SCL/CCLK
28
Control Port Clock (
Input) - Serial control interface clock and is used to clock control data bits into and
out of the CS8406. In IC mode, SCL requires an external pull-up resistor to VL.
AD0/CS
2
Address Bit 0 (IC Mode) / Control Port Chip Select (SPI) (
Input) - A falling edge on this pin puts the
CS8406 into SPI control port mode. With no falling edge, the CS8406 defaults to IC mode. In IC mode,
AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on the CS8406
AD1/CDIN
27
Address Bit 1 (IC Mode) / Serial Control Data in (SPI) (
Input) - In IC mode, AD1 is a chip address
pin. In SPI mode, CDIN is the input data line for the control port interface.
AD2
3
Address Bit 2 (IC Mode)
(
Input) -
Determines the AD2 address bit for the control port in IC mode, and
should be connected to GND or VL. If SPI mode is used, the AD2 pin should be connected to either
GND or VL.
RXP
4
Auxiliary AES3 Receiver Port (
Input) - Input for an alternate, already AES3 coded, audio data
source.
INT
19
Interrupt (
Output) - Indicates key events during the operation of the CS8406. All bits affecting INT may
be unmasked through bits in the control registers. Indication of the condition(s) that initiated an interrupt
are readable in the control registers. The polarity of the INT output, as well as selection of a standard or
open drain output, is set through a control register. Once set true, the INT pin goes false only after the
interrupt status registers have been read and the interrupt status bits have returned to zero.
TCBL
15
Transmit Channel Status Block Start (
Input/Output) - When operated as output, TCBL is high during
the first sub-frame of a transmitted channel status block, and low at all other times. When operated as
input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be
the start of a channel status block.
U
20
User Data (
Input) - May optionally be used to input User data for transmission by the AES3 transmitter,
see
Figure 4
for timing information. If not driven, a 47 k
pull-down resistor is recommended for the U
pin. If the U pin is driven by a logic level output, then a 100
series resistor is recommended.
TEST
7
8
10
11
16
17
18
Test Pins - These pins are unused inputs. It is recommended that these pins be tied to a supply (VL or
GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left floating, how-
ever current consumption from VL will increase by 25
A per TEST pin that is left floating.
CS8406
32
DS580F1
10.HARDWARE MODE
The CS8406 has a hardware mode that allows the use of the device without a microcontroller.
Hardware mode is selected by connecting the H/S pin to VL. The flexibility of the CS8406 is nec-
essarily limited in hardware mode. Various pins change function as described in the hardware
mode pin description section.
The hardware mode data flow is shown in Figure 12. Audio data is input through the serial audio
input port and routed to the AES3 transmitter.
10.1 Channel Status, User and Validity Data
The transmitted channel status, user and validity data can be input in two methods, determined
by the state of the CEN pin. Mode A is selected when the CEN pin is low. In mode A, the user bit
data and the validity bit are input through the U and V pins, clocked by both edges of ILRCK. The
channel status data is derived from the state of the COPY/C, ORIG, EMPH, and AUDIO pins.
Table 2 shows how the COPY/C and ORIG pins map to channel status bits. In consumer mode,
the transmitted category code is set to General (00h).
Mode B is selected when the CEN pin is high. In mode B, the channel status, user data bits and
the validity bit are input serially through the COPY/C, U and V pins. Data is clocked into these
pins at both edges of ILRCK. Figure 8 shows the timing requirements.
AES3
Encoder
& Tx
Serial
Audio
Input
C, U, V Data Buffer
ILRCK
ISCLK
TXP
COPY/C ORIG EMPH AUDIO
VL
H/S
Output
Clock
Source
OMCK
Power supply pins are omitted from this diagram.
Please refer to the Typical Connection Diagram for hook-up details.
SDIN
SFMT1 SFMT0
TXN
CEN
U
V
APMS
TCBL
TCBLD
RST
Figure 12. Hardware Mode Data Flow
CS8406
DS580F1
33
The channel status block pin (TCBL) may be an input or an output, determined by the state of
the TCBLD pin.
10.2 Serial Audio Port
The serial audio input port data format is selected as shown in Table 3, and may be set to master
or slave by the state of the APMS input pin. The OMCK clock ratio is selected as shown in
Table 4. Table 5 describes the equivalent software mode, bit settings for each of the available for-
mats. Timing diagrams are shown in Figure 7.
COPY/C
ORIG
Function
0
0
PRO=0, COPY=0, L=0 copyright
0
1
PRO=0, COPY=0, L=1 copyright, pre-recorded
1
0
PRO=0, COPY=1, L=0 non-copyright
1
1
PRO=1
Table 2. Hardware Mode COPY/C and ORIG pin functions
SFMT1
SFMT0
Function
0
0
Serial Input Format IF1 - Left Justified
0
1
Serial Input Format IF2 - IS
1
0
Serial Input Format IF3 - Right Justified, 24-bit data
1
1
Serial Input Format IF4 - Right Justified, 16-bit data
Table 3. Hardware Mode Serial Audio Port Format Selection
HWCK1
HWCK0
Function
0
0
OMCK Frequency is 256*Fs
0
1
OMCK Frequency is 128*Fs
1
0
OMCK Frequency is 512*Fs
1
1
OMCK Frequency is 256*Fs
Table 4. Hardware Mode OMCK Clock Ratio Selection
SISF
SIRES1/0
SIJUST
SIDEL
SISPOL
SILRPOL
IF1 - Left Justified
0
00
0
0
0
0
IF2 - IS
0
00
0
1
0
1
IF3 - Right Justified, 24-bit data
0
00
1
0
0
0
IF4 - Right Justified, 16-bit data
0
10
1
0
0
0
Table 5. Equivalent Register Settings of Serial Audio Input Formats Available in Hardware Mode
CS8406
34
DS580F1
11.PIN DESCRIPTION - HARDWARE MODE
VD
6
Digital Power (
Input) - Digital core power supply. Typically +3.3 V or +5.0 V.
VL
23
Logic Power (
Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
GND
22
Ground
(
Input) - Ground for I/O and core logic.
RST
9
Reset (
Input) - When RST is low, the CS8406 enters a low power mode and all internal states are reset.
On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable
in frequency and phase. This is particularly true in hardware mode with multiple CS8406 devices, where
synchronization between devices is important.
H/S
24
Hardware/Software Control Mode Select (
Input) -Determines the method of controlling the operation
of the CS8406, and the method of accessing CS and U data. Hardware mode provides an alternate
mode of operation, and access to CS and U data is provided by dedicated pins. To select Hardware
mode, this pin should be permanently tied to VL.
TXN
TXP
25
26
Differential Line Drivers (
Output) - These pins transmit biphase encoded data. The drivers are pulled
low while the CS8406 is in the reset state.
OMCK
21
Master Clock (
Input) - The frequency can be set through the HWCK[1:0] pins.
ISCLK
13
Serial Audio Bit Clock (
Input/Output) - Serial bit clock for audio data on the SDIN pin.
ILRCK
12
Serial Audio Input Left/Right Clock (
Input/Output) - Word rate clock for the audio data on the SDIN
pin.
SDIN
14
Serial Audio Data Port (
Input) - Audio data serial input pin.
SFMT0
SFMT1
4
5
Serial Audio Data Format Select (
Input) - Selects the serial audio input port format. See Table 3 on
page 33.
COPY / C
ORIG
TEST
HWCK1
EMPH
TXP
SFMT0
TXN
SFMT1
H/S
VD
VL
TEST
GND
TEST
OMCK
RST
HWCK0
APMS
AUDIO
TCBLD
U
ILRCK
V
ISCLK
CEN
SDIN
TCBL
1
2
3
4
5
6
7
8
21
22
23
24
25
26
27
28
9
10
11
12
17
18
19
20
13
14
15
16
CS8406
DS580F1
35
APMS
10
Serial Audio Data Port Master/Slave Select (
Input) - APMS should be connected to VL to set serial
audio input port as a master or connected to GND to set the port as a slave.
HWCK0
HWCK1
20
27
OMCK Clock Ratio Select (
Input) - Selects the ratio of OMCK to the input sample rate (Fs). A pull-up to
VL or pull-down to GND is required to set the appropriate mode. See Table 4 on page 33.
TCBLD
11
Transmit Channel Status Block Direction (
Input) - Connect TCBLD to VL to set TCBL as an output.
Connect TCBLD to GND to set TCBL as an input.
TCBL
15
Transmit Channel Status Block Start (
Input/Output) - When operated as output, TCBL is high during
the first sub-frame of a transmitted channel status block, and low at all other times. When operated as
input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be
the start of a channel status block.
CEN
16
C Bit Enable (
Input) - Determines how the channel status data bits are input. When CEN is low, hard-
ware mode A is selected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected
channel status data. When CEN is high, hardware mode B is selected, where the COPY/C pin is used to
enter serial channel status data.
V
17
Validity Bit (
Input) - In hardware modes A and B, the V pin input determines the state of the validity bit
in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.
U
18
User Data Bit (
Input) - In hardware modes A and B, the U pin input determines the state of the user
data bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.
COPY/C
1
COPY Channel Status Bit/C Bit (Input) - In hardware mode A (CEN = 0), the COPY/C and ORIG pins
determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data stream,
see Table 2 on page 33. In hardware mode B, the COPY/C pin becomes the direct C bit input data pin,
which is sampled on both edges of LRCK.
EMPH
3
Pre-Emphasis Indicator (
Input) - In hardware mode A (CEN = 0), the EMPH pin low sets the 3 empha-
sis channel status bits to indicate 50/15
s pre-emphasis of the transmitted audio data. If EMPH is high,
then the three EMPH channel status bits are set to 000, indicating no pre-emphasis.
AUDIO
19
Audio Channel Status Bit (
Input) - In hardware mode A (CEN = 0), the AUDIO pin determines the state
of the audio/non audio Channel Status bit in the outgoing AES3 data stream.
ORIG
28
ORIG Channel Status Bit Control (
Input) - In hardware mode A (CEN = 0), the ORIG and COPY/C
pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data
stream, see Table 2 on page 33.
TEST
2
7
8
Test Pins - These pins are unused inputs. It is recommended that these pins be tied to a supply (VL or
GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left floating, how-
ever current consumption from VL will increase by 25
A per TEST pin that is left floating.
CS8406
36
DS580F1
12.APPLICATIONS
12.1 Reset, Power Down and Start-up
When RST is low, the CS8406 enters a low power mode and all internal states are reset, includ-
ing the control port and registers, and the outputs are disabled. In Software mode when RST is
high, the control port becomes operational and the desired settings should be loaded into the
control registers. Writing a 1 to the RUN bit will then cause the part to leave the low power state
and begin operation. In Hardware mode when RST is high, the part will automatically leave the
low power state and begin operation.
12.2 ID Code and Revision Code
The CS8406 has a register that contains a four-bit code to indicate that the addressed device is
a CS8406. This is useful when other CS84XX family members are resident in the same or similar
systems, allowing common software modules.
The CS8406 four-bit revision level code is also available. This allows the software driver for the
CS8406 to identify which revision of the device is in a particular system, and modify its behavior
accordingly. To allow for future revisions, it is strongly recommended that the revision code is
read into a variable area within the microcontroller, and used wherever appropriate as revision
details become known.
12.3 Power Supply, Grounding, and PCB layout
The CS8406 operates from a VD = +3.3 V or +5.0 V and VL = +3.3 V or +5.0 V supply. These
supplied may be set independently. Follow normal supply decoupling practices, see Figure 5 and
Figure 6. The VD and VL supplies should be decoupled with a 0.1
F capacitor to GND to mini-
mize AES3 transmitter induced transients.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount
decoupling capacitors are recommended. Decoupling capacitors should be mounted on the
same side of the board as the CS8406 to minimize inductance effects, and all decoupling capac-
itors should be as close to the CS8406 as possible.
12.4 Synchronization of Multiple CS8406s
The AES3 transmitters of multiple CS8406s can be synchronized if all devices share the same
master clock, TCBL, and RST signals. The TCBL pin is used to synchronize multiple CS8406
AES3 transmitters at the channel status block boundaries. One CS8406 must have its TCBL set
to master; the others must be set to slave TCBL. Alternatively, TCBL can be derived from exter-
nal logic, whereby all CS8406 devices should be set to slave TCBL.
CS8406
DS580F1
37
13. PACKAGE DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN
NOM
MAX
MIN
NOM
MAX
A 0.093
0.098
0.104
2.35
2.50
2.65
A1
0.004
0.008
0.012
0.10
0.20
0.30
b
0.013
0.017
0.020
0.33
0.42
0.51
C
0.009
0.011
0.013
0.23
0.28
0.32
D
0.697
0.705
0.713
17.70
17.90
18.10
E
0.291
0.295
0.299
7.40
7.50
7.60
e
0.040
0.050
0.060
1.02
1.27
1.52
H
0.394
0.407
0.419
10.00
10.34
10.65
L
0.016
0.026
0.050
0.40
0.65
1.27
0
4
8
0
4
8
JEDEC #: MS-013
Controlling Dimension is Millimeters
28L SOIC (300 MIL BODY) PACKAGE DRAWING
D
H
E
b
A1
A
c
L
SEATING
PLANE
1
e
CS8406
38
DS580F1
Notes: 1."D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2.Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not
reduce dimension "b" by more than 0.07 mm at least material condition.
3.These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
INCHES
MILLIMETERS
NOTE
DIM
MIN
NOM
MAX
MIN
NOM
MAX
A
--
--
0.47
--
--
1.20
A1
0.002
0.004
0.006
0.05
0.10
0.15
A2
0.03150
0.035
0.04
0.80
0.90
1.00
b
0.00748
0.0096
0.012
0.19
0.245
0.30
2,3
D
0.378 BSC
0.382 BSC
0.386 BSC
9.60 BSC
9.70 BSC
9.80 BSC
1
E
0.248
0.2519
0.256
6.30
6.40
6.50
E1
0.169
0.1732
0.177
4.30
4.40
4.50
1
e
--
0.026 BSC
--
--
0.65 BSC
--
L
0.020
0.024
0.029
0.50
0.60
0.75
0
4
8
0
4
8
JEDEC #: MO-153
Controlling Dimension is Millimeters.
28L TSSOP (4.4 mm BODY) PACKAGE DRAWING
E
N
1 2 3
e
b
2
A1
A2
A
D
SEATING
PLANE
E1
1
L
SIDE VIEW
END VIEW
TOP VIEW
CS8406
DS580F1
39
14.APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER
COMPONENTS
This section details the external components required to interface the AES3 transmitter to cables
and fiber-optic components.
14.1 AES3 Transmitter External Components
The output drivers on the CS8406 are designed to drive both the professional and consumer in-
terfaces. The AES3 and IEC60958-4 specifications call for a balanced output drive of 2-7 V peak-
to-peak into a 110
20% load with no cable attached. Using the circuit in Figure 13, the output
of the transformer is short-circuit protected, has the proper source impedance, and provides a
5 V peak-to-peak signal into a 110
load. Lastly, the two output pins should be attached to an
XLR connector with male pins and a female shell, and with pin 1 of the connector grounded.
In the case of consumer use, the IEC60958-3 specification calls for an unbalanced drive circuit
with an output impedance of 75
20% and a output drive level of 0.5 V peak-to-peak 20%
when measured across a 75
load using no cable. The circuit shown in Figure 14 only uses the
TXP pin and provides the proper output impedance and drive level using standard 1% resistors.
If VL is set to +3.3 V, change 374
to 243 and change 90.9 to 107 . The connector for a
consumer application would be an RCA phono socket. This circuit is also short circuit protected.
The TXP pin may be used to drive TTL or CMOS gates as shown in Figure 15. This circuit may
be used for optical connectors for digital audio since they usually have TTL or CMOS compatible
inputs. This circuit is also useful when driving multiple digital audio outputs since RS422 line driv-
ers have TTL compatible inputs.
14.2 Isolating Transformer Requirements
Please refer to the application note AN134:
AES and SPDIF Recommended Transformers for re-
sources on transformer selection.
374-R
TXP
90.9
TXP
TXN
RCA
Phono
CS8406
110-(R
TXP
+R
TXN
)
TXP
TXN
XLR
1
CS8406
Figure 13. Professional Output Circuit
Figure 14. Consumer Output Circuit (VL = 5.0 V)
TXP
TXN
TTL or
CMOS Gate
CS8406
Figure 15. TTL/CMOS Output Circuit
CS8406
40
DS580F1
15.APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT
The CS8406 has a comprehensive channel status (C) and user (U) data buffering scheme which
allows the user to manage the C and U data through the control port.
15.1 AES3 Channel Status(C) Bit Management
The CS8406 contains sufficient RAM to store a full block of C data for both A and B channels
(192x2 = 384 bits), and also 384 bits of U information. The user may read from or write to these
RAM buffers through the control port.
The CS8406 manages the flow of channel status data at the block level, meaning that entire
blocks of channel status information are buffered at the input, synchronized to the output time-
base, and then transmitted. The buffering scheme involves a cascade of 2 block-sized buffers,
named E and F, as shown in Figure 16. The MSB of each byte represents the first bit in the serial
C data stream. For example, the MSB of byte 0 (which is at control port address 20h) is the con-
sumer/professional bit for channel status block A.
The E buffer is accessible from the control port, allowing read and writing of the C data. The F
buffer is used as the source of C data for the AES3 transmitter. The F buffer accepts block trans-
fers from the E buffer.
15.1.1 Accessing the E buffer
The user can monitor the data being transferred by reading the E buffer, which is mapped into
the register space of the CS8406, through the control port. The user can modify the data to be
transmitted by writing to the E buffer.
The user can configure the interrupt enable register to cause interrupts to occur whenever "E to
F" buffer transfers occur. This allows determination of the allowable time periods to interact with
the E buffer.
Also provided is an "E to F" inhibit bit. The "E to F" buffer transfer is disabled whenever the user
sets this bit. This may be used whenever "long" control port interactions are occurring.
A flowchart for reading and writing to the E buffer is shown in Figure 17. For writing, the sequence
starts after a E to F transfer, which is based on the output timebase.
C on tro l P ort
To
A E S 3
Tra nsm itte r
E
24
w o rds
8 -bits
8 -b its
A
B
F
Tran sm it
D a ta
B u ffer
Figure 16. Channel Status Data Buffer Structure
CS8406
DS580F1
41
If the channel status block to transmit indicates PRO mode, then the CRCC byte is automatically
calculated by the CS8406, and does not have to be written into the last byte of the block by the
host microcontroller. This is also true if the channel status data is entered serially through the
COPY/C pin when the part is in hardware mode.
15.1.2 Serial Copy Management System
(SCMS)
In software mode, the CS8406 allows read/modify/write access to all the channel status bits. For
consumer mode SCMS compliance, the host microcontroller needs to manipulate the Category
Code, Copy bit and L bit appropriately.
In hardware mode, the SCMS protocol can be followed by either using the COPY and ORIG input
pins, or by using the C bit serial input pin. These options are documented in the hardware mode
section of this data sheet.
15.1.3 Channel Status Data E Buffer Access
The E buffer is organized as 24 x 16-bit words. For each word the MS Byte is the A channel data,
and the LS Byte is the B channel data (see Figure 16).
There are two methods of accessing this memory, known as one byte mode and two byte mode.
The desired mode is selected through a control register bit.
15.1.3.1 One Byte mode
In many applications, the channel status blocks for the A and B channels will be identical. In this
situation, if the user reads a byte from one of the channel's blocks, the corresponding byte for the
other channel will be the same. Similarly, if the user wrote a byte to one channel's block, it would
be necessary to write the same byte to the other block. One byte mode takes advantage of the
often identical nature of A and B channel status data.
When reading data in one byte mode, a single byte is returned, which can be from channel A or
B data, depending on a register control bit. If a write is being done, the CS8406 expects a single
E to F interrupt occurs
Optionally set E to F inhibit
If set, clear E to F inhibit
Return
Write E data
Wait for E to F transfer
Figure 17. Flowchart for Writing the E Buffer
CS8406
42
DS580F1
byte to be input to its control port. This byte will be written to both the A and B locations in the
addressed word.
One byte mode saves the user substantial control port access time, as it effectively accesses 2
bytes worth of information in 1 byte's worth of access time. If the control port's auto increment
addressing is used in combination with this mode, multi-byte accesses such as full-block reads
or writes can be done especially efficiently.
15.1.3.2 Two Byte mode
There are those applications in which the A and B channel status blocks will not be the same,
and the user is interested in accessing both blocks. In these situations, two byte mode should be
used to access the E buffer.
In this mode, a read will cause the CS8406 to output two bytes from its control port. The first byte
out will represent the A channel status data, and the 2nd byte will represent the B channel status
data. Writing is similar, in that two bytes must now be input to the CS8406's control port. The A
channel status data is first, B channel status data second.
15.2 AES3 User (U) Bit Management
The CS8406 U bit manager has two operating modes:
Mode 1. Transmit all zeros.
Mode 2. Block mode.
15.2.1 Mode 1: Transmit All Zeros
Mode 1 causes only zeros to be transmitted in the output U data, regardless of E buffer contents.
This mode is intended for the user who wants the output U channel to contain no data.
15.2.2 Mode 2: Block Mode
Mode 2 is very similar to the scheme used to control the C bits. Entire blocks of U data are buffered
using 2 block-sized RAMs to perform the buffering. The user has access to the first buffer, denoted
the E buffer, through the control port. It is the only mode in which the user can merge his own U data
into the transmitted AES3 data stream. The U buffer access only operates in two byte mode, since
there is no concept of A and B blocks for user data. The arrangement of the data is as followings:
Bit15[A7] Bit14[B7] Bit13[A6] Bit12 [B6]...Bit1 [A0] Bit0[B0]. The arrangement of the data in the each
byte is that the MSB is the first transmitted bit. The bit for the A subframe is followed by the bit for the
B subframe.
CS8406
DS580F1
43
16. REVISION HISTORY
Release
Date
Changes
PP1
August 2002
1st Preliminary Release
PP2
May 2003
2nd Preliminary Release
PP3
January 2004
-Corrected "OMCK Low and High Width for OMCK = 384*Fs" on page 7.
-Corrected "Rise Time of Both SDA and SCL Lines" on page 10.
-Corrected "Fall Time of Both SDA and SCL Lines" on page 10.
-Added Note 13 on page 10.
-Corrected Figure 6. "Recommended Connection Diagram for Hardware Mode" on
page 12
-Revised "Control Port Description" on page 19
F1
July 2004
Final Release
-Corrected "SDIN Setup Time Before ISCLK Active Edge" on page 7.
-Corrected Note 5 on page 7.
-Corrected Note 6 on page 7.
-Added Figure 8. "AES3 Transmitter Timing for C, U, and V Pin Input Data" on page 18
-Corrected H/S pin description on page 34.
Table 6. Revision History
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to
www.cirrus.com
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