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Электронный компонент: CS8421-CZZR

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Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 2005
(All Rights Reserved)
http://www.cirrus.com
CS8421
32-bit, 192 kHz Asynchronous Sample Rate Converter
Features
175 dB Dynamic Range
140 dB THD+N
No Programming Required
No External Master Clock Required
Supports Sample Rates up to 211 kHz
Input/Output Sample Rate Ratios from 7.5:1
to 1:8
Master Clock Support for 128 x f
s
, 256 x f
s
,
384 x f
s
, and 512 x f
s
(Master Mode)
16, 20, 24, or 32-bit Data I/O
32-bit Internal Signal Processing
Dither Automatically Applied and Scaled to
Output Resolution
Flexible 3-Wire Serial Digital Audio Input and
Output Ports
Master and Slave Modes for Both Input and
Output
Bypass Mode
Time Division Multiplexing (TDM) Mode
Attenuates Clock Jitter
Multiple Part Outputs are Phase Matched
Linear Phase FIR Filter
Automatic Soft Mute/Unmute
+2.5 V Digital Supply (VD)
+3.3 V or 5.0 V Digital Interface (VL)
Space Saving 20-pin TSSOP and QFN
Packages
I
Serial
Audio
Input
Time
Varying
Digital
Filters
BYPASS
Digital
PLL
Clock
Generator
ILRCK
ISCLK
SDIN
Sync Info
Data
Serial
Audio
Output
OLRCK
OSCLK
SDOUT
XTI
XTO
SRC_UNLOCK
2.5 V (VD)
GND
RST
Sync Info
Data
Data
Level Translators
TDM_IN
MS_SEL
SAIF
SAOF
Serial
Port
Mode
Decoder
L
eve
l
T
r
a
n
s
l
ato
r
s
L
eve
l
Tra
n
slato
r
s
MCLK_OUT
3.3 V or 5.0 V (VL)
JAN `05
DS641PP1
CS8421
2
DS641PP1
General Description
The CS8421 is a 32-bit, high performance, monolithic CMOS stereo asynchronous sample rate converter.
Digital audio inputs and outputs can be 32, 24, 20, or 16-bits. Input and output data can be completely
asynchronous, synchronous to an external data clock, or the part can operate without any external clock
by using an integrated oscillator.
Audio data is input and output through configurable 3-wire input/output ports. The CS8421 does not re-
quire any software control via a control port.
Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR),
digital mixing consoles, high quality D/A, effects processors, computer audio systems, and automotive au-
dio systems.
The part is available in space saving 20-pin TSSOP and QFN packages and supports sample rates up to
211 kHz.
ORDERING INFORMATION
Product
Description
Package Pb-Free Temp Range
Container
Order#
CS8421 32-bit Asynchronous Sample Rate Converter
TSSOP
YES
-10 to +70C
Rail
CS8421-CZZ
CS8421 32-bit Asynchronous Sample Rate Converter
TSSOP
YES
-10 to +70C Tape and Reel CS8421-CZZR
CS8421 32-bit Asynchronous Sample Rate Converter
QFN
YES
-10 to +70C
Rail
CS8421-CNZ
CS8421 32-bit Asynchronous Sample Rate Converter
QFN
YES
-10 to +70C Tape and Reel CS8421-CNZR
CS8421 32-bit Asynchronous Sample Rate Converter
TSSOP
YES
-40 to +85C
Rail
CS8421-DZZ
CS8421 32-bit Asynchronous Sample Rate Converter
TSSOP
YES
-40 to +85C Tape and Reel CS8421-DZZR
CDB8421 Evaluation Board for CS8421
-
-
-
-
CDB8421
CS8421
DS641PP1
3
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5
2. TYPICAL CONNECTION DIAGRAMS ................................................................................. 10
3. GENERAL DESCRIPTION ..................................................................................................... 12
4. THREE-WIRE SERIAL INPUT/OUTPUT AUDIO PORT ........................................................ 12
5. MODE SELECTION ................................................................................................................ 12
6. SAMPLE RATE CONVERTER (SRC) .................................................................................... 15
6.1 Clocking ........................................................................................................................... 15
6.2 Data Resolution and Dither ............................................................................................. 15
6.3 SRC Locking and Varispeed ........................................................................................... 15
6.4 Bypass Mode ................................................................................................................... 16
6.5 Muting .............................................................................................................................. 16
6.6 Group Delay and Phase Matching Between Multiple CS8421 Parts ............................... 16
6.7 Master Clock .................................................................................................................... 17
6.8 Time Division Multiplexing (TDM) Mode .......................................................................... 18
7. PIN DESCRIPTIONS ........................................................................................................ 20
7.1 TSSOP Pin Descriptions .............................................................................................. 21
7.2 QFN Pin Descriptions ..................................................................................................... 22
8. PERFORMANCE PLOTS .............................................................................................. 23
9. APPLICATIONS .................................................................................................................... 32
9.1 Reset, Power Down, and Start-up ................................................................................... 32
9.2 Power Supply, Grounding, and PCB layout ..................................................................... 32
10. PACKAGE DIMENSIONS ................................................................................................... 33
11. REVISION HISTORY ........................................................................................................... 35
LIST OF FIGURES
Figure 1. Non-TDM Slave Mode Timing.......................................................................................... 8
Figure 2. TDM Slave Mode Timing ................................................................................................. 8
Figure 3. Non-TDM Master Mode Timing........................................................................................ 9
Figure 4. TDM Master Mode Timing ............................................................................................... 9
Figure 5. Typical Connection Diagram, Master and Slave Modes................................................ 10
Figure 6. Typical Connection Diagram, No External Master Clock............................................... 11
Figure 7. Serial Audio Interface Format - IS ................................................................................ 14
Figure 8. Serial Audio Interface Format - Left Justified................................................................. 14
Figure 9. Serial Audio Interface Format - Right Justified .............................................................. 14
Figure 10. Typical Connection Diagram for Crystal Circuit ........................................................... 17
Figure 11. TDM Slave Mode Timing Diagram............................................................................... 18
Figure 12. TDM Master Mode Timing Diagram............................................................................. 18
Figure 13. TDM Mode Configuration (All CS8421 outputs are slave)........................................... 19
Figure 14. TDM Mode Configuration (First CS8421 output is master, all others are slave).......... 19
Figure 15a. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:48 kHz...................... 23
Figure 15b. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:192 kHz................. 23
Figure 16a. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:48 kHz................... 23
Figure 16b. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:44.1 kHz................... 23
Figure 17a. Wideband FFT Plot (1Fsi6k Points) 0 dBFS 1 kHz Tone, 48 kHz:96 kHz ................. 23
Figure 17b. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 96 kHz:48 kHz...................... 23
Figure 18a. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 192 kHz:48 kHz.................... 24
Figure 18b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:96 kHz................... 24
Figure 19a. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:48 kHz................... 24
Figure 19b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 44.1 kHz:192 kHz.............. 24
Figure 20a. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 44.1 kHz:48 kHz................ 24
Figure 20b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:44.1 kHz................ 24
CS8421
4
DS641PP1
Figure 21b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 96 kHz:48 kHz ................... 25
Figure 21b. IMD, 10 kHz and 11 kHz -7 dBFS, 96 kHz:48 kHz..................................................... 25
Figure 22a. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 192 kHz:48 kHz ................. 25
Figure 22b. IMD, 10 kHz and 11 kHz -7 dBFS, 48 kHz:44.1 kHz.................................................. 25
Figure 23a. IMD, 10 kHz and 11 kHz -7 dBFS, 44.1 kHz:48 kHz.................................................. 25
Figure 23b. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 44.1 kHz:48 kHz ................. 25
Figure 24a. Wideband FFT Plot (16k Points) 0 dBFS 80 kHz Tone, 192 kHz:192 kHz ................ 26
Figure 24b. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:96 kHz .................... 26
Figure 25a. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:48 kHz .................... 26
Figure 25b. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 96 kHz:48 kHz .................... 26
Figure 26a. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:44.1 kHz ................. 26
Figure 26b. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 192 kHz ...................... 26
Figure 27a. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 48 kHz ........................ 27
Figure 27b. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 96 kHz ........................ 27
Figure 28a. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 44.1 kHz ..................... 27
Figure 28b. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 192 kHz...... 27
Figure 29a. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 32 kHz ........................ 27
Figure 29b. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 32 kHz........ 27
Figure 30a. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 96 kHz........ 28
Figure 30b. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 44.1 kHz..... 28
Figure 31a. Frequency Response with 0 dBFS Input.................................................................... 28
Figure 31b. Passband Ripple, 192 kHz:48 kHz............................................................................. 28
Figure 32a. Dynamic Range........ vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 48 kHz28
Figure 32b. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:48 kHz ........................ 28
Figure 33a. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:44.1 kHz ..................... 29
Figure 33b. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:96 kHz ........................ 29
Figure 34a. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 96 kHz:48 kHz ........................ 29
Figure 34b. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:192 kHz ................... 29
Figure 35a. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:48 kHz ..................... 29
Figure 35b. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 192 kHz:44.1 kHz ................... 29
Figure 36a. THD+N vs. Input Amplitude, 1 kHz Tone, 48 kHz:44.1 kHz....................................... 30
Figure 36b. THD+N vs. Input Amplitude, 1 kHz Tone, 48 kHz:96 kHz.......................................... 30
Figure 37a. THD+N vs. Input Amplitude, 1 kHz Tone, 96 kHz:48 kHz.......................................... 30
Figure 37b. THD+N vs. Input Amplitude, 1 kHz Tone, 44.1 kHz:192 kHz..................................... 30
Figure 38a. THD+N vs. Input Amplitude, 1 kHz Tone, 44.1 kHz:48 kHz....................................... 30
Figure 38b. THD+N vs. Input Amplitude, 1 kHz Tone, 192 kHz:48 kHz........................................ 30
Figure 39a. THD+N vs. Frequency Input, 0 dBFS, 48 kHz:44.1 kHz ............................................ 31
Figure 39b. THD+N vs. Frequency Input, 0 dBFS, 48 kHz:96 kHz ............................................... 31
Figure 40a. THD+N vs. Frequency Input, 0 dBFS, 44.1 kHz:48 kHz ............................................ 31
Figure 40b. THD+N vs. Frequency Input, 0 dBFS, 96 kHz:48 kHz ............................................... 31
LIST OF TABLES
Table 1. Serial Audio Port Master/Slave and Clock Ratio Select Startup Options (MS_SEL) ...... 13
Table 2. Serial Audio Input Port Startup Options (SAIF) ............................................................... 13
Table 3. Serial Audio Output Port Startup Options (SAOF) .......................................................... 13
Table 4. TSSOP Pin Descriptions ................................................................................................. 21
Table 5. QFN Pin Descriptions...................................................................................................... 22
Table 6. Revision History .............................................................................................................. 35
CS8421
DS641PP1
5
1.
CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions.
Typical performance characteristics and specifications are derived from measurements taken at nominal
supply voltages and T
A
= 25C.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V)
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to 0 V. Operation beyond
these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.)
Notes: 1. Transient currents of up to 100 mA will not cause SCR latch-up.
2. Numbers separated by a colon indicate input and output sample rates. For example, 48 kHz:96 kHz
indicates that Fsi = 48 khz and Fso = 96 kHz.
Parameter
Symbol Min Nominal
Max
Units
Power Supply Voltage
VD
VL
2.38
3.14
2.5
3.3 or 5.0
2.62
5.25
V
V
Ambient Operating Temperature:
`-CZ'
`-CNZ'
`-DZ'
T
A
-10
-10
-40
-
-
-
+70
+70
+85
C
C
C
Parameter
Symbol
Min
Max
Units
Power Supply Voltage
VD
VL
-0.3
-0.3
3.5
6.0
V
V
Input Current, Any Pin Except Supplies
(Note 1)
I
in
-
10
mA
Input Voltage
V
in
-0.3
VL+0.4
V
Ambient Operating Temperature (power applied)
T
A
-55
+125
C
Storage Temperature
T
stg
-65
+150
C
CS8421
6
DS641PP1
PERFORMANCE SPECIFICATIONS
(XTI/XTO = 27 MHz; Input signal = 1.000 kHz, 0 dBFS,
Measurement Bandwidth = 20 to Fso/2 Hz, and Word Width = 32-Bits, unless otherwise stated.)
DIGITAL FILTER CHARACTERISTICS
Notes: 3. The equation for the group delay through the sample rate converter is (56.581 / Fsi) + (55.658 / Fso).
For example, if the input sample rate is 192 kHz and the output sample rate is 96 kHz, the group delay
through the sample rate converter is (56.581/192,000) + (55.658/96,000) =.875 milliseconds.
Parameter
Min Typ
Max
Units
Resolution
16
-
32
bits
Sample Rate with XTI = 27.000 MHz
Slave
Master
7.2
53
-
-
207
211
kHz
kHz
Sample Rate with other XTI clocks
Slave
Master
XTI/3750
XTI/512
-
-
XTI/130
XTI/128
kHz
kHz
Sample Rate with ring oscillator (XTI to GND or VL, XTO floating)
12
-
96
kHz
Sample Rate Ratio - Upsampling
-
-
1:8
Sample Rate Ratio - Downsampling
-
-
7.5:1
Interchannel Gain Mismatch
-
0.0
-
dB
Interchannel Phase Deviation
-
0.0
-
Degrees
Peak Idle Channel Noise Component (32-bit operation)
-
-
-192
dBFS
Dynamic Range (20 Hz to Fso/2, 1 kHz, -60 dBFS Input)
44.1 kHz:48 kHz
A-Weighted
Unweighted
-
-
180
177
-
-
dB
dB
44.1 kHz:192 kHz
A-Weighted
Unweighted
-
-
175
172
-
-
dB
dB
48 kHz:44.1 kHz
A-Weighted
Unweighted
-
-
180
177
-
-
dB
dB
48 kHz:96 kHz
A-Weighted
Unweighted
-
-
179
176
-
-
dB
dB
96 kHz:48 kHz
A-Weighted
Unweighted
-
-
176
173
-
-
dB
dB
192 kHz:32 kHz
A-Weighted
Unweighted
-
-
175
172
-
-
dB
dB
Total Harmonic Distortion + Noise
(20 Hz to Fso/2, 1 kHz, 0 dBFS
Input)
32 kHz:48 kHz
-
-161
-
dB
44.1 kHz:48 kHz
-
-171
-
dB
44.1 kHz:192 kHz
-
-130
-
dB
48 kHz:44.1 kHz
-
-160
-
dB
48 kHz:96 kHz
-
-148
-
dB
96 kHz:48 kHz
-
-168
-
dB
192 kHz:32 kHz
-
-173
-
dB
Parameter
Min Typ
Max
Units
Passband (Upsampling or Downsampling)
-
-
0.4535*Fso Hz
Passband Ripple
-
-
0.007
dB
Stopband
0.5465*Fso
-
-
Hz
Stopband Attenuation
125
-
-
dB
Group Delay
(Note 3)
ms
CS8421
DS641PP1
7
DC ELECTRICAL CHARACTERISTICS
(GND = 0 V; all voltages with respect to 0 V.)
Notes: 4. Power Down Mode is defined as RST = LOW with all clocks and data lines held static, except when a
crystal is attached across XTI-XTO, in which case the crystal will begin oscillating.
5. Normal operation is defined as RST = HI.
DIGITAL INPUT CHARACTERISTICS
DIGITAL INTERFACE SPECIFICATIONS
(GND = 0 V; all voltages with respect to 0 V.)
Parameters
Symbol
Min
Typ
Max
Units
Power-down Mode
(Note 4)
Supply Current in power down
VD
(Oscillator attached to XTI-XTO)
VL = 3.3 V
VL = 5.0 V
-
-
-
50
100
200
-
-
-
A
A
A
Supply Current in power down
VD
(Crystal attached to XTI-XTO)
VL = 3.3 V
VL = 5.0 V
-
-
-
99.9
1.34
3.54
-
-
-
A
mA
mA
Normal Operation
(Note 5)
Supply Current at 48 kHz Fsi and Fso
VD
(Oscillator attached to XTI-XTO) VL = 3.3 V
VL = 5.0 V
-
-
-
23.1
2.17
3.42
-
-
-
mA
mA
mA
Supply Current at 192 kHz Fsi and Fso
VD
(Oscillator attached to XTI-XTO) VL = 3.3 V
VL = 5.0 V
-
-
-
78.7
7.7
12.49
-
-
-
mA
mA
mA
Supply Current at 48 kHz Fsi and Fso
VD
(Crystal attached to XTI-XTO) VL = 3.3 V
VL = 5.0 V
-
23.1
2.92
6.02
-
mA
mA
mA
Supply Current at 192 kHz Fsi and Fso
VD
(Crystal attached to XTI-XTO) VL = 3.3 V
VL = 5.0 V
-
78.7
3.037
6.25
-
mA
mA
mA
Parameters
Symbol Min Typ
Max
Units
Input Leakage Current
I
in
-
-
10
A
Input Capacitance
I
in
-
8
-
pF
Input Hysteresis
-
250
-
mV
Parameters
Symbol Min
Max
Units
High-Level Output Voltage, except MCLK_OUT and SDOUT
(I
OH
=-4 mA)
V
OH
0.77xVL
-
V
Low-Level Output Voltage, except MCLK_OUT and SDOUT
(I
OL
=4 mA)
V
OL
-
.6
V
High-Level Output Voltage, MCLK_OUT
(I
OH
=-6 mA)
V
OH
0.77xVL
-
V
Low-Level Output Voltage, MCLK_OUT
(I
OL
=6 mA)
V
OL
-
.6
V
High-Level Output Voltage, SDOUT
(I
OH
=-8 mA)
V
OH
0.77xVL
-
V
Low-Level Output Voltage, SDOUT
(I
OL
=8 mA)
V
OL
-
.6
V
High-Level Input Voltage
V
IH
0.55xVL
VL+0.3
V
Low-Level Input Voltage
V
IL
-0.3
0.8
V
CS8421
8
DS641PP1
SWITCHING SPECIFICATIONS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C
L
= 20 pF)
Parameters
Symbol Min
Max
Units
RST pin Low Pulse Width
(Note 6)
1
-
ms
XTI Frequency (Note 7)
Crystal
Digital Clock Source
16.384
1.024
27.000
27.000
MHz
MHz
XTI Pulse Width High/Low
14.8
-
ns
MCLK_OUT Duty Cycle
45
55
%
Slave Mode
I/OSCLK Frequency
-
24.576
MHz
OLRCK High Time
(Note 8)
t
lrckh
326
-
ns
I/OSCLK High Time
t
sckh
9
-
ns
I/OSCLK Low Time
t
sckl
9
-
ns
I/OLRCK Edge to I/OSCLK Rising
t
lcks
6
-
ns
OLRCK Rising Edge to OSCLK Rising Edge (TDM)
t
fss
5
-
ns
I/OSCLK Rising Edge to I/OLRCK Edge
t
lckd
5
-
ns
OSCLK Rising Edge to OLRCK Falling Edge (TDM)
t
fsh
5
-
ns
OSCLK Falling Edge/OLRCK Edge to SDOUT Output Valid
t
dpd
-
18
ns
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
t
ds
3
-
ns
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
t
dh
5
-
ns
t
ds
OLRCK
(input)
t
dh
t
sckh
t
sckl
t
fsh
t
fss
OSCLK
(input)
TDM_IN
(input)
SDOUT
(output)
MSB
t
dpd
MSB-1
MSB
MSB-1
t
lrckh
t
ds
MSB
t
dh
t
dpd
MSB-1
I/OLRCK
(input)
I/OSCLK
(input)
SDIN
(input)
SDOUT
(output)
MSB
MSB-1
t
sckh
t
sckl
t
lcks
t
lckd
Figure 1. Non-TDM Slave Mode Timing
Figure 2. TDM Slave Mode Timing
CS8421
DS641PP1
9
Notes: 6. After powering up the CS8421, RST should be held low until the power supplies and clocks are settled.
7. The maximum possible sample rate is XTI/128.
8. OLRCK must remain high for at least 8 OSCLK periods in TDM mode.
9. Only the input or the output serial port can be set as master at a given time.

Master Mode
(Note 9)
I/OSCLK Frequency (non-TDM)
64*Fsi/o
MHz
OSCLK Frequency (TDM)
256*Fso
MHz
I/OLRCK Duty Cycle
45
55
%
I/OSCLK Duty Cycle
45
55
%
I/OSCLK Falling Edge to I/OLRCK Edge
t
lcks
-
5
ns
OSCLK Falling Edge to OLRCK Edge (TDM)
t
fss
-
5
ns
OSCLK Falling Edge to SDOUT Output Valid
t
dpd
-
7
ns
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
t
ds
3
-
ns
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
t
dh
5
-
ns
Parameters
Symbol Min
Max
Units
t
ds
OLRCK
(output)
t
dh
t
dpd
t
fss
OSCLK
(output)
TDM_IN
(input)
SDOUT
(output)
MSB
MSB-1
MSB
MSB-1
t
ds
MSB
t
dh
t
dpd
MSB-1
t
lcks
I/OLRCK
(output)
I/OSCLK
(output)
SDIN
(input)
SDOUT
(output)
MSB
MSB-1
Figure 3. Non-TDM Master Mode Timing
Figure 4. TDM Master Mode Timing
CS8421
10
DS641PP1
2.
TYPICAL CONNECTION DIAGRAMS
CS8421
VD
VL
Serial
Audio
Source
ILRCK
ISCLK
SDIN
BYPASS
+2.5 V
+3.3 V or +5.0 V
0.1
F
0.1
F
Serial
Audio
Input
Device
OLRCK
OSCLK
SDOUT
XTI
XTO
RST
SRC_UNLOCK
SAOF
TDM_IN
Hardware Control
Settings
Crystal /Clock
Source
GND
SAIF
MS_SEL
GND
MCLK_OUT
To external
hardware
47 k
*
**
Figure 5. Typical Connection Diagram, Master and Slave Modes
* The connection (VL or GND) and value of these three resistors determines the mode of operation for the
input and output serial ports as described in Table 1, "Serial Audio Port Master/Slave and Clock Ratio Se-
lect Startup Options (MS_SEL)", Table 2, "Serial Audio Input Port Startup Options (SAIF)", and Table 3,
"Serial Audio Output Port Startup Options (SAOF)", all on page 13.
** MCLK_OUT pin should be pulled high through a 47 k
resistor if an MCLK output is not needed.
CS8421
DS641PP1
11
CS8421
VD
VL
Serial
Audio
Source
ILRCK
ISCLK
SDIN
BYPASS
+2.5 V
+3.3 V or +5.0 V
0.1
F
0.1
F
Serial
Audio
Input
Device
OLRCK
OSCLK
SDOUT
XTI
RST
SRC_UNLOCK
SAOF
TDM_IN
Hardware Control
Settings
GND
SAIF
MS_SEL
GND
**
1 k
*
Figure 6. Typical Connection Diagram, No External Master Clock
* When no external master clock is supplied to the part, both input and output must be set to salve mode
for the part to operate properly. This is done by connecting the MS_SEL pin to ground through a resis-
tance of 0
to 1 k
1% as stated in Table 1, "Serial Audio Port Master/Slave and Clock Ratio Select
Startup Options (MS_SEL)," on page 13
** The connection (VL or GND) and value of these two resistors determines the mode of operation for the
input and output serial ports as described in Table 1, "Serial Audio Port Master/Slave and Clock Ratio
Select Startup Options (MS_SEL)", Table 2, "Serial Audio Input Port Startup Options (SAIF)", and
Table 3, "Serial Audio Output Port Startup Options (SAOF)", all on page 13.
CS8421
12
DS641PP1
3. GENERAL DESCRIPTION
The CS8421 is a 32-bit, high performance, monolithic CMOS stereo asynchronous sample rate converter.
The digital audio data is input and output through configurable 3-wire serial ports. The digital audio in-
put/output ports offer Left Justified, Right Justified, and IS serial audio formats. The CS8421 also sup-
ports a TDM mode which allows multiple channels of digital audio data on one serial line. A bypass mode
allows the data to be passed directly to the output port without sample rate conversion.
The CS8421 does not require a control port interface, helping to speed design time by not requiring the
user to develop software to configure the part. Pins that are sensed after reset allow the part to be con-
figured. See "Reset, Power Down, and Start-up" on page 32.
Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR),
digital mixing consoles, high quality D/A, effects processors and computer audio systems.
Figure 5 and Figure 6 show the supply and external connections to the CS8421.
4. THREE-WIRE SERIAL INPUT/OUTPUT AUDIO PORT
A 3-wire serial audio input/output port is provided. The interface format should be chosen to suit the at-
tached device through the MS_SEL, SAIF, and SAOF pins. Table 1, Table 2, and Table 3 show the pin
functions and their corresponding settings. The following parameters are adjustable:
Master or slave.
Master clock (MCLK) ratios of 128*Fsi/o, 256*Fsi/o, 384*Fsi/o, and 512*Fsi/o (Master mode).
Audio data resolution of 16, 20, 24, or 32-bits.
Left or right justification of the data relative to left/right clock (LRCK) as well as IS.
Figure 7, Figure 8, and Figure 9 show the input/output formats available.
In master mode, the left/right clock and the serial bit clock are outputs, derived from the XTI input pin mas-
ter clock.
In slave mode, the left/right clock and the serial bit clock are inputs and may be asynchronous to the XTI
master clock. The left/right clock should be continuous, but the duty cycle can be less than 50% if enough
serial clocks are present in each phase to clock all of the data bits.
ISCLK is always set to 64*Fsi when the input is set to master. In normal operation, OSCLK is set to
64*Fso. In TDM slave mode, OSCLK must operate at N*64*Fso, where N is the number of CS8421's con-
nected together. In TDM master mode, OSCLK is set to 256*Fso
5. MODE SELECTION
The CS8421 uses the resistors attached to the MS_SEL, SAIF, and SAOF pins to determine the modes
of operation. After reset the resistor value and condition (VL or GND) are sensed. This operation will take
approximately 4
s to complete. The SRC_UNLOCK pin will remain high and the SDOUT pin will be mut-
ed until the mode detection sequence has completed. After this, if all clocks are stable, SRC_UNLOCK
will be brought low when audio output is valid and normal operation will occur. Table 1, Table 2, and
Table 3 show the pin functions and their corresponding settings. If the 1.0 k
option is selected for
MS_SEL, SAIF, or SAOF, the resistor connected to that pin may be replaced by a direct connection to VL
or GND as appropriate.
The resistor attached to each mode selection pin should be placed physically close to the CS8421. The
end of the resistor not connected to the mode selection pins should be connected as close as possible to
VL and GND to minimize noise. Table 1, Table 2, and Table 3 show the pin functions and their corre-
sponding settings.
CS8421
DS641PP1
13
MS_SEL pin
Input M/S
Output M/S
1.0 k
1% to GND
Slave
Slave
1.96 k
1% to GND
Slave
Master (
128 x Fso
)
4.02 k
1% to GND
Slave
Master (
256 x Fso
)
8.06 k
1% to GND
Slave
Master (
384
x Fso)
16.2 k
1% to GND
Slave
Master (
512
x Fso)
1.0 k
1% to VL
Master (
128 x Fsi
)
Slave
1.96 k
1% to VL
Master (
256 x Fsi
)
Slave
4.02 k
1% to VL
Master (
384 x Fsi
)
Slave
8.06 k
1% to VL
Master (
512
x Fsi)
Slave
Table 1. Serial Audio Port Master/Slave and Clock Ratio Select Startup Options (MS_SEL)
SAIF pin
Input Port Configuration
1.0 k
1% to GND
IS up to 32-bit data
1.96 k
1% to GND
Left Justified up to 32-bit data
4.02 k
1% to GND
Right Justified 16-bit data
1.0 k
1% to VL
Right Justified 20-bit data
1.96 k
1% to VL
Right Justified 24-bit data
4.02 k
1% to VL
Right Justified 32-bit data
Table 2. Serial Audio Input Port Startup Options (SAIF)
SAOF pin
Output Port Configuration
1.0 k
1% to GND
IS 16-bit data
1.96 k
1% to GND
IS 20-bit data
4.02 k
1% to GND
IS 24-bit data
8.06 k
1% to GND
IS 32-bit data
16.2 k
1% to GND
Left Justified 16-bit data
32.4 k
1% to GND
Left Justified 20-bit data
63.4 k
1% to GND
Left Justified 24-bit data
127.0 k
1% to GND
Left Justified 32-bit data
1.0 k
1% to VL
Right Justified 16-bit data
1.96 k
1% to VL
Right Justified 20-bit data
4.02 k
1% to VL
Right Justified 24-bit data
8.06 k
1% to VL
Right Justified 32-bit data
16.2 k
1% to VL
TDM Mode 16-bit data
32.4 k
1% to VL
TDM Mode 20-bit data
63.4 k
1% to VL
TDM Mode 24-bit data
127.0 k
1% to VL
TDM Mode 32-bit data
Table 3. Serial Audio Output Port Startup Options (SAOF)
CS8421
14
DS641PP1
I/OLRCK
I/OSCLK
M S B
L S B
M S B
L S B
Channel A
SDIN
SDOUT
MSB
Channel B
Figure 7. Serial Audio Interface Format - IS
M S B
L S B
M S B
L S B
MSB
I/OLRCK
I/OSCLK
SDIN
SDOUT
Channel A
Channel B
Figure 8. Serial Audio Interface Format - Left Justified
I/OLRCK
I/OSCLK
Channel A
SDIN
Channel B
MSB
SDOUT
MSB
MSB
MSB
LSB
LSB
LSB
LSB
MSB Extended
MSB Extended
Figure 9. Serial Audio Interface Format - Right Justified
CS8421
DS641PP1
15
6. SAMPLE RATE CONVERTER (SRC)
Multirate digital signal processing techniques are used to conceptually upsample the incoming data to a
very high rate and then downsample to the outgoing rate. The internal data path is 32-bits wide even if a
lower bit depth is selected at the output. The filtering is designed so that a full input audio bandwidth of
20 kHz is preserved if the input sample and output sample rates are greater than or equal to 44.1 kHz.
When the output sample rate becomes less than the input sample rate, the input is automatically band
limited to avoid aliasing products in the output. Careful design ensures minimum ripple and distortion
products are added to the incoming signal. The SRC also determines the ratio between the incoming and
outgoing sample rates, and sets the filter corner frequencies appropriately. Any jitter in the incoming signal
has little impact on the dynamic performance of the rate converter and has no influence on the output
clock.
6.1
Clocking
In order to ensure proper operation of the CS8421, the clock or crystal attached to XTI must simultaneous-
ly satisfy the requirements of LRCK for both the input and output as follows:
If the input is set to master, Fsi
XTI/128 and Fso
XTI/130.
If the output is set to master, Fso
XTI/128 and Fsi
XTI/130.
If both input and output are set to slave, XTI
130*[minimum(Fsi,Fso)], XTI/Fsi < 3750, and XTI/Fso
< 3750.
6.2
Data Resolution and Dither
When using the serial audio input port in left justified and IS modes all input data is treated as 32-bits
wide. Any truncation that has been done prior to the CS8421 to less than 32-bits should have been done
using an appropriate dithering process. If the serial audio input port is in right justified mode, the input data
will be truncated to the bit depth set by SAIF pin setting. If the SAIF bit depth is set to 16, 20, or 24-bits,
and the input data is 32-bits wide, then truncation distortion will occur. Similarly, in any serial audio input
port mode, if an inadequate number of bit clocks are entered (i.e. 16 clocks instead of 20 clocks), then the
input words will be truncated, causing truncation distortion at low levels. In summary, there is no dithering
mechanism on the input side of the CS8421, and care must be taken to ensure that no truncation occurs.
Dithering is used internally where appropriate inside the SRC block.
The output side of the SRC can be set to 16, 20, 24, or 32-bits. Dithering is applied and is automatically
scaled to the selected output word length. This dither is not correlated between left and right channels.
6.3
SRC Locking and Varispeed
The SRC calculates the ratio between the input sample rate and the output sample rate, and uses this
information to set up various parameters inside the SRC block. The SRC takes some time to make this
calculation, approximately 4200/Fso (8.75 ms at Fso of 48 kHz).
If Fsi is changing, as in a varispeed application, the SRC will track the incoming sample rate. During this
tracking mode, the SRC will still rate convert the audio data, but at increased distortion levels. Once the
incoming sample rate is stable the SRC will return to normal levels of audio quality. The data buffer in the
SRC can overflow if the input sample rate changes at greater than 10%/sec.
The SRC_UNLOCK pin is used to indicate when the SRC is not locked. When RST is asserted, or if there
is a change in Fsi or Fso, SRC_UNLOCK will be set high. The SRC_UNLOCK pin will continue to be high
until the SRC has reacquired lock and settled, at which point it will transition low. When the
SRC_UNLOCK pin is set low, SDOUT is outputting valid audio data. This can be used to signal a DAC to
unmute its output.
CS8421
16
DS641PP1
6.4
Bypass Mode
When the BYPASS pin is set high, the input data bypasses the sample rate converter and is sent directly
to the serial audio output port. No dithering is performed on the output data. This mode is ideal for passing
non-audio data through without a sample rate conversion. ILRCK and OLRCK should be the same sample
rate and synchronous in this mode.
6.5
Muting
The SDOUT pin is set to all zero output (full mute) immediately after the RST pin is set high. When the
output from the SRC becomes valid, though the SRC may not have reached full performance, SDOUT is
unmuted over a period of approximately 4096 OLRCK cycles (soft unmuted). When the output becomes
invalid, depending on the condition, SDOUT is either immediately set to all zero output (hard muted) or
SDOUT is muted over a period of approximately 4096 OLRCK cycles until it reaches full mute (soft mut-
ed). The SRC will soft mute SDOUT if there is an illegal ratio between ILRCK and the XTI master clock.
Conditions that will cause the SRC to hard mute SDOUT include removing OLRCK, the RST pin being
set low, or illegal ratios between OLRCK and the XTI master clock. After all invalid states have been
cleared, the SRC will soft unmute SDOUT.
6.6
Group Delay and Phase Matching Between Multiple CS8421 Parts
The equation for the group delay through the sample rate converter is shown in "Digital Filter Character-
istics" on page 6. This phase delay is equal across multiple parts. Therefore, when multiple parts operate
at the same Fsi and Fso and use a common XTI/XTO clock, their output data is phase matched.
CS8421
DS641PP1
17
6.7
Master Clock
The CS8421 uses the clock signal supplied through XTI as its master clock (MCLK). MCLK can be sup-
plied from a digital clock source, a crystal oscillator, or a fundamental mode crystal. Figure 10 shows the
typical connection diagram for using a fundamental mode crystal. Please refer to the crystal manufactur-
er's specifications for the external capacitor recommendations. If XTO is not used, such as with a digital
clock source or crystal oscillator, XTO should be left unconnected or pulled low through a 47 k
resistor
to GND.
If either serial audio port is set as master, MCLK will be used to supply the sub-clocks to the master SCLK
and LRCK. In this case MCLK will be synchronous to the master serial audio port. If both serial audio ports
are set as slave, MCLK can be asynchronous to either or both ports. If the user needs to change the clock
source to XTI while the CS8421 is still powered on and running, a RESET must be issued once the XTI
clock source is present and valid to ensure proper operation.
When both serial ports are configured as slave and operating at sample rates less than 96 kHz, the
CS8421 has the ability to operate without a master clock input through XTI. This benefits the design by
not requiring extra external clock components (lowering production cost) and not requiring a master clock
to be routed to the CS8421, resulting in lowered noise contribution in the system. In this mode, an internal
oscillator provides the clock to run all of the internal logic. To enable the internal oscillator simply tie XTI
to GND or VL. In this mode, XTO should be left unconnected.
The CS8421 can also provide a buffered MCLK output through the MCLK_OUT pin. This pin can be used
to supply MCLK to other system components that operate synchronously to MCLK. If MCLK_OUT is not
needed, the output of the pin can be disabled by pulling the pin high through a 47 k
resistor to VL.
MCLK_OUT is also disabled when using the internal oscillator mode. The MCLK_OUT pin will be set low
when disabled by using the internal oscillator mode.
XTI
XTO
C
C
R
Figure 10. Typical Connection Diagram for Crystal Circuit
CS8421
18
DS641PP1
6.8
Time Division Multiplexing (TDM) Mode
TDM mode allows several CS8421 to be serially connected together allowing their corresponding SDOUT
data to be multiplexed onto one line for input into a DSP or other TDM capable multichannel device.
The CS8421 can operate in two TDM modes. The first mode consists of all of the CS8421's output ports
set to slave as shown in Figure 13. The second mode consists of one CS8421 output port set to master
and the remaining CS8421's output ports set to slave as shown in Figure 14.
The TDM_IN pin is used to input the data while the SDOUT pin is used to output the data. The first
CS8421 in the chain should have its TDM_IN set to GND. Data is transmitted from SDOUT most signifi-
cant bit first on the first OSCLK after an OLRCK transition and is valid on the rising edge of OSCLK.
In TDM slave mode, the number of channels that can by multiplexed to one serial data line depends on
the output sampling rate. For slave mode, OSCLK must operate at N*64*Fso, where N is the number of
CS8421's connected together. The maximum allowable OSCLK frequency is 24.576 MHz, so for Fso =
48 kHz, N = 8 (16 channels of serial audio data).
In TDM master mode, OSCLK operates at 256*Fso, which is equivalent to N = 4, so a maximum of 8 chan-
nels of digital audio can be multiplexed together. Note that for TDM master mode, MCLK must be at least
256*Fso, where Fso
96 kHz. OLRCK identifies the start of a new frame. Each time slot is 32-bits wide,
with the valid data sample left justified within the time slot. Valid data lengths are 16, 20, 24 or 32-bits.
Figure 11 and Figure 12 show the interface format for master and slave TDM modes.
Channel6
OLRCK
OSCLK
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
SDOUT/
TDM_IN
Channel1
Channel4
Channel2
Channel5
Channel3
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
Channel8
LSB
MSB
LSB
MSB
Channel7
32 clks
32 clks
Figure 11. TDM Slave Mode Timing Diagram
Channel6
OLRCK
OSCLK
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
SDOUT/
TDM_IN
Channel1
Channel4
Channel2
Channel5
Channel3
256 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
Channel8
LSB
MSB
LSB
MSB
Channel7
32 clks
32 clks
Figure 12. TDM Master Mode Timing Diagram
CS8421
DS641PP1
19
ILRCK
ISCLK
SDIN
OLRCK
OSCLK
SDOUT
TDM_IN
OLRCK
OSCLK
SDOUT
TDM_IN
OLRCK
OSCLK
SDOUT
TDM_IN
LRCK
SCLK
SDIN
ILRCK
ISCLK
SDIN
ILRCK
ISCLK
SDIN
Output
Clock
Source
LRCK
SCLK
OLRCK OSCLK SDOUT
PCM Source n
OLRCK OSCLK SDOUT
PCM Source 1
OLRCK OSCLK SDOUT
PCM Source 0
CS8421
Phase
Master /
Slave 0
CS8421
Slave 1
CS8421
Slave n
DSP
Slave
Figure 13. TDM Mode Configuration (All CS8421 outputs are slave)
ILRCK
ISCLK
SDIN
OLRCK
OSCLK
SDOUT
TDM_IN
CS8421
OLRCK
OSCLK
SDOUT
TDM_IN
OLRCK
OSCLK
SDOUT
TDM_IN
LRCK
SCLK
SDIN
ILRCK
ISCLK
SDIN
ILRCK
ISCLK
SDIN
OLRCK OSCLK SDOUT
PCM Source n
OLRCK OSCLK SDOUT
PCM Source 1
OLRCK OSCLK SDOUT
PCM Source 0
Clock
and
Phase
Master
CS8421
Slave 0
CS8421
Slave n
DSP
Slave
Figure 14. TDM Mode Configuration (First CS8421 output is master, all others are slave)
CS8421
20
DS641PP1
7. PIN DESCRIPTIONS
XTO
SRC_UNLOCK
XTI
SAIF
VD
SAOF
GND
VL
RST
GND
BYPASS
MS_SEL
ILRCK
OLRCK
ISCLK
OSCLK
SDIN
SDOUT
MCLK_OUT
TDM_IN
1
2
3
4
5
6
7
8
13
14
15
16
17
18
19
20
9
10
11
12
Top-Down View
20-pin TSSOP Package
7
6
5
4
3
2
1
8
9
10
11
12
13
14
15
16
17
18
19
20
Top-Down View
20-pin QFN Package
Thermal Pad
XTI
XTO
SR
C_
UN
LO
C
K
SAIF
SAOF
ISCLK
SDIN
MCLK_OUT
TDM_IN
SDOUT
VD
GND
RST
BYPASS
ILRCK
VL
GND
MS_SEL
OLRCK
OSCLK
CS8421
DS641PP1
21
7.1
TSSOP PIN DESCRIPTIONS
PIN
XTO
1
Crystal Out
(Output) - Crystal output for Master clock. See "Master Clock" on page 17.
XTI
2
Crystal/Oscillator In
(Input) - Crystal or digital clock input for Master clock. See "Master Clock" on
page 17.
VD
3
Digital Power
(Input) - Digital core power supply. Typically +2.5 V.
GND
4
Ground
(Input) - Ground for I/O and core logic.
RST
5
Reset
(Input) - When RST is low the CS8421 enters a low power mode and all internal states are
reset. On initial power up RST must be held low until the power supply is stable and all input clocks
are stable in frequency and phase.
BYPASS
6
Sample Rate Converter Bypass
(Input) - When BYPASS is high, the sample rate converter will be
bypassed and any data input through the serial audio input port will be directly output on the serial
audio output port. When Bypass is low the sample rate converter will operate normally.
ILRCK
7
Serial Audio Input Left/Right Clock
(Input/Output) - Word rate clock for the audio data on the
SDIN pin.
ISCLK
8
Serial Audio Bit Clock
(Input/Output) - Serial bit clock for audio data on the SDIN pin.
SDIN
9
Serial Audio Input Data Port
(Input) - Audio data serial input pin.
MCLK_OUT
10
Master Clock Output
(Output) - Buffered and level shifted output for Master clock. If MCLK_OUT
is not required, this pin should be pulled high through a 47 k
resistor to turn the output off. See
"Master Clock" on page 17.
TDM_IN
11
Serial Audio TDM Input
(Input) - Time Division Multiplexing serial audio data input. Grounded
when not used. See "Time Division Multiplexing (TDM) Mode" on page 18
SDOUT
12
Serial Audio Output Data Port
(Output) - Audio data serial output pin. Optionally this pin may be
pulled low through a 47 k
resistor, but should not be pulled high.
OSCLK
13
Serial Audio Bit Clock
(Input/Output) - Serial bit clock for audio data on the SDOUT pin.
OLRCK
14
Serial Audio Input Left/Right Clock
(Input/Output) - Word rate clock for the audio data on the
SDOUT pin.
MS_SEL
15
Master/Slave Select
(Input) - Used to select Master or Slave for the input and output serial audio
ports at startup and reset. See Table 1 on page 13 for format settings.
GND
16
Ground
(Input) - Ground for I/O and core logic.
VL
17
Logic Power
(Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
SAOF
18
Serial Audio Output Format Select
(Input) - Used to select the serial audio output format at star-
tup and reset. See Table 3 on page 13 for format settings.
SAIF
19
Serial Audio Input Format Select
(Input) - Used to select the serial audio input format at startup
and reset. See Table 2 on page 13 for format settings.
SRC_UNLOCK
20
SRC Unlock Indicator
(Output) - Indicates when the SRC is unlocked. See "SRC Locking and
Varispeed" on page 15.
Table 4. TSSOP Pin Descriptions
CS8421
22
DS641PP1
7.2
QFN PIN DESCRIPTIONS
PIN
VD
1
Digital Power
(Input) - Digital core power supply. Typically +2.5 V.
GND
2
Ground
(Input) - Ground for I/O and core logic.
RST
3
Reset
(Input) - When RST is low the CS8421 enters a low power mode and all internal states are
reset. On initial power up RST must be held low until the power supply is stable and all input clocks
are stable in frequency and phase.
BYPASS
4
Sample Rate Converter Bypass
(Input) - When BYPASS is high, the sample rate converter will be
bypassed and any data input through the serial audio input port will be directly output on the serial
audio output port. When Bypass is low the sample rate converter will operate normally.
ILRCK
5
Serial Audio Input Left/Right Clock
(Input/Output) - Word rate clock for the audio data on the
SDIN pin.
ISCLK
6
Serial Audio Bit Clock
(Input/Output) - Serial bit clock for audio data on the SDIN pin.
SDIN
7
Serial Audio Input Data Port
(Input) - Audio data serial input pin.
MCLK_OUT
8
Master Clock Output
(Output) - Buffered and level shifted output for Master clock. If MCLK_OUT
is not required, this pin should be pulled high through a 47 k
resistor to turn the output off. See
"Master Clock" on page 17.
TDM_IN
9
Serial Audio TDM Input
(Input) - Time Division Multiplexing serial audio data input. Grounded
when not used. See "Time Division Multiplexing (TDM) Mode" on page 18
SDOUT
10
Serial Audio Output Data Port
(Output) - Audio data serial output pin. Optionally this pin may be
pulled low through a 47 k
resistor, but should not be pulled high.
OSCLK
11
Serial Audio Bit Clock
(Input/Output) - Serial bit clock for audio data on the SDOUT pin.
OLRCK
12
Serial Audio Input Left/Right Clock
(Input/Output) - Word rate clock for the audio data on the
SDOUT pin.
MS_SEL
13
Master/Slave Select
(Input) - Used to select Master or Slave for the input and output serial audio
ports at startup and reset. See Table 1 on page 13 for format settings.
GND
14
Ground
(Input) - Ground for I/O and core logic.
VL
15
Logic Power
(Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
SAOF
16
Serial Audio Output Format Select
(Input) - Used to select the serial audio output format at star-
tup and reset. See Table 3 on page 13 for format settings.
SAIF
17
Serial Audio Input Format Select
(Input) - Used to select the serial audio input format at startup
and reset. See Table 2 on page 13 for format settings.
SRC_UNLOCK
18
SRC Unlock Indicator
(Output) - Indicates when the SRC is unlocked. See "SRC Locking and
Varispeed" on page 15.
XTO
19
Crystal Out
(Output) - Crystal output for Master clock. See "Master Clock" on page 17.
XTI
20
Crystal/Oscillator In
(Input) - Crystal or digital clock input for Master clock. See "Master Clock" on
page 17.
THERMAL PAD
-
Thermal Pad
- Thermal relief pad for optimized heat dissipation.
Table 5. QFN Pin Descriptions
CS8421
DS641PP1
23
8. PERFORMANCE PLOTS
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k
20k
10k
15k
Hz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
20k
80k
40k
60k
Hz
Figure 15a. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone,
48 kHz:48 kHz
Figure 15b. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone,
44.1 kHz:192 kHz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k
20k
10k
15k
Hz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
2.5k
20k
5k
7.5k
10k
12.5k
15k
17.5k
Hz
Figure 16a. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone,
44.1 kHz:48 kHz
Figure 16b. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone,
48 kHz:44.1 kHz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
10k
40k
20k
30k
Hz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k
20k
10k
15k
Hz
Figure 17a. Wideband FFT Plot (1Fsi6k Points) 0 dBFS 1 kHz
Tone, 48 kHz:96 kHz
Figure 17b. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone,
96 kHz:48 kHz
CS8421
24
DS641PP1
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k
20k
10k
15k
Hz
-200
-60
-180
-160
-140
-120
-100
-80
d
B
F
S
10k
40k
20k
30k
Hz
Figure 18a. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone,
192 kHz:48 kHz
Figure 18b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone,
48 kHz:96 kHz
-200
-60
-180
-160
-140
-120
-100
-80
d
B
F
S
5k
20k
10k
15k
Hz
-200
-60
-180
-160
-140
-120
-100
-80
d
B
F
S
20k
80k
40k
60k
Hz
Figure 19a. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz
Tone, 48 kHz:48 kHz
Figure 19b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone,
44.1 kHz:192 kHz
-200
-60
-180
-160
-140
-120
-100
-80
d
B
F
S
5k
20k
10k
15k
Hz
-200
-60
-180
-160
-140
-120
-100
-80
d
B
F
S
2.5k
20k
5k
7.5k
10k
12.5k
15k
17.5k
Hz
Figure 20a. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz
Tone, 44.1 kHz:48 kHz
Figure 20b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone,
48 kHz:44.1 kHz
CS8421
DS641PP1
25
-200
-60
-180
-160
-140
-120
-100
-80
d
B
F
S
5k
20k
10k
15k
Hz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k
20k
10k
15k
Hz
Figure 21b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz
Tone, 96 kHz:48 kHz
Figure 21b. IMD, 10 kHz and 11 kHz -7 dBFS, 96 kHz:48 kHz
-200
-60
-180
-160
-140
-120
-100
-80
d
B
F
S
5k
20k
10k
15k
Hz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
2.5k
20k
5k
7.5k
10k
12.5k
15k
17.5k
Hz
Figure 22a. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz
Tone, 192 kHz:48 kHz
Figure 22b. IMD, 10 kHz and 11 kHz -7 dBFS, 48 kHz:44.1 kHz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k
20k
10k
15k
Hz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k
20k
10k
15k
Hz
Figure 23a. IMD, 10 kHz and 11 kHz -7 dBFS, 44.1 kHz:48 kHz
Figure 23b. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone,
44.1 kHz:48 kHz
CS8421
26
DS641PP1
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
20k
80k
40k
60k
Hz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
10k
40k
20k
30k
Hz
Figure 24a. Wideband FFT Plot (16k Points) 0 dBFS 80 kHz Tone,
192 kHz:192 kHz
Figure 24b. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone,
48 kHz:96 kHz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k
20k
10k
15k
Hz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
5k
20k
10k
15k
Hz
Figure 25a. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone,
48 kHz:48 kHz
Figure 25b. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone,
96 kHz:48 kHz
-200
+0
-180
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
2.5k
20k
5k
7.5k
10k
12.5k
15k
17.5k
Hz
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k
175k
75k
100k
125k
150k
Hz
Figure 26a. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone,
48 kHz:44.1 kHz
Figure 26b. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone,
Fsi = 192 kHz
CS8421
DS641PP1
27
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k
175k
75k
100k
125k
150k
Hz
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k
175k
75k
100k
125k
150k
Hz
Figure 27a. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone,
Fsi = 48 kHz
Figure 27b. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone,
Fsi = 96 kHz
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k
175k
75k
100k
125k
150k
Hz
-145
-135
-144
-143
-142
-141
-140
-139
-138
-137
-136
d
B
F
S
50k
175k
75k
100k
125k
150k
Hz
Figure 28a. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone,
Fsi = 44.1 kHz
Figure 28b. Dynamic Range vs. Output Sample Rate, -60 dBFS
1 kHz Tone, Fsi = 192 kHz
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k
175k
75k
100k
125k
150k
Hz
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k
175k
75k
100k
125k
150k
Hz
Figure 29a. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone,
Fsi = 32 kHz
Figure 29b. Dynamic Range vs. Output Sample Rate, -60 dBFS
1 kHz Tone, Fsi = 32 kHz
CS8421
28
DS641PP1
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k
175k
75k
100k
125k
150k
Hz
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k
175k
75k
100k
125k
150k
Hz
Figure 30a. Dynamic Range vs. Output Sample Rate, -60 dBFS
1 kHz Tone, Fsi = 96 kHz
Figure 30b. Dynamic Range vs. Output Sample Rate, -60 dBFS
1 kHz Tone, Fsi = 44.1 kHz
-140
+0
-120
-100
-80
-60
-40
-20
d
B
F
S
0
60k
10k
20k
30k
40k
50k
Hz
192 kHz:32 kHz
192 kHz:48 kHz
192 kHz:96 kHz
-0.2
+0
-0.18
-0.16
-0.14
-0.12
-0.1
-0.08
-0.06
-0.04
-0.02
d
B
F
S
0
25k
5k
10k
15k
20k
Hz
Figure 31a. Frequency Response with 0 dBFS Input
Figure 31b. Passband Ripple, 192 kHz:48 kHz
-150
-120
-147.5
-145
-142.5
-140
-137.5
-135
-132.5
-130
-127.5
-125
-122.5
d
B
F
S
50k
175k
75k
100k
125k
150k
Hz
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
-140
+0
-120
-100
-80
-60
-40
-20
dBFS
Figure 32a. Dynamic Range vs. Output Sample Rate, -60 dBFS
1 kHz Tone, Fsi = 48 kHz
Figure 32b. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone,
48 kHz:48 kHz
CS8421
DS641PP1
29
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
-140
+0
-120
-100
-80
-60
-40
-20
dBFS
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
-140
+0
-120
-100
-80
-60
-40
-20
dBFS
Figure 33a. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone,
48 kHz:44.1 kHz
Figure 33b. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone,
48 kHz:96 kHz
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
-140
+0
-120
-100
-80
-60
-40
-20
dBFS
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
-140
+0
-120
-100
-80
-60
-40
-20
dBFS
Figure 34a. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone,
96 kHz:48 kHz
Figure 34b. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone,
44.1 kHz:192 kHz
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
-140
+0
-120
-100
-80
-60
-40
-20
dBFS
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
-140
+0
-120
-100
-80
-60
-40
-20
dBFS
Figure 35a. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone,
44.1 kHz:48 kHz
Figure 35b. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone,
192 kHz:44.1 kHz
CS8421
30
DS641PP1
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
-140
+0
-120
-100
-80
-60
-40
-20
dBFS
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
-140
+0
-120
-100
-80
-60
-40
-20
dBFS
Figure 36a. THD+N vs. Input Amplitude, 1 kHz Tone,
48 kHz:44.1 kHz
Figure 36b. THD+N vs. Input Amplitude, 1 kHz Tone,
48 kHz:96 kHz
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
-140
+0
-120
-100
-80
-60
-40
-20
dBFS
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
-140
+0
-120
-100
-80
-60
-40
-20
dBFS
Figure 37a. THD+N vs. Input Amplitude, 1 kHz Tone,
96 kHz:48 kHz
Figure 37b. THD+N vs. Input Amplitude, 1 kHz Tone,
44.1 kHz:192 kHz
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
-140
+0
-120
-100
-80
-60
-40
-20
dBFS
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
-140
+0
-120
-100
-80
-60
-40
-20
dBFS
Figure 38a. THD+N vs. Input Amplitude, 1 kHz Tone,
44.1 kHz:48 kHz
Figure 38b. THD+N vs. Input Amplitude, 1 kHz Tone,
192 kHz:48 kHz
CS8421
DS641PP1
31

-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
0
20k
2.5k
5k
7.5k
10k
12.5k
15k
17.5k
Hz
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
-140
+0
-120
-100
-80
-60
-40
-20
dBFS
Figure 39a. THD+N vs. Frequency Input, 0 dBFS, 48 kHz:44.1 kHz
Figure 39b. THD+N vs. Frequency Input, 0 dBFS, 48 kHz:96 kHz
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
0
20k
2.5k
5k
7.5k
10k
12.5k
15k
17.5k
Hz
-180
-110
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
d
B
F
S
0
20k
2.5k
5k
7.5k
10k
12.5k
15k
17.5k
Hz
Figure 40a. THD+N vs. Frequency Input, 0 dBFS, 44.1 kHz:48 kHz
Figure 40b. THD+N vs. Frequency Input, 0 dBFS, 96 kHz:48 kHz
All performance plots represent typical performance. Measurements for all performance plots were taken
under the following conditions, unless otherwise stated:
VD = 2.5 V, VL = 3.3 V
Serial Audio Input port set to slave
Serial Audio Output port set to slave
Input and output clocks and data are asynchronous
XTI/XTO = 27 MHz
Input signal = 1.000 kHz, 0 dBFS
Measurement Bandwidth = 20 to (Fso/2) Hz
Word Width = 24 Bits
CS8421
32
DS641PP1
9. APPLICATIONS
9.1
Reset, Power Down, and Start-up
When RST is low the CS8421 enters a low power mode, all internal states are reset, and the outputs are
disabled. After RST transitions from low to high the part senses the resistor value on the configuration
pins (MS_SEL, SAIF, and SAOF) and sets the appropriate mode of operation. After the mode has been
set (approximately 4
s) the part is set to normal operation and all outputs are functional.
9.2
Power Supply, Grounding, and PCB layout
The CS8421 operates from a VD = +2.5 V and VL = +3.3 V or +5.0 V supply. These supplies may be set
independently. Follow normal supply decoupling practices, see Figure 5.
Extensive use of power and ground planes, ground plane fill in unused areas, and surface mount decou-
pling capacitors are recommended. Decoupling capacitors should be mounted on the same side of the
board as the CS8421 to minimize inductance effects and all decoupling capacitors should be as close to
the CS8421 as possible. The pin of the configuration resistors not connected to MS_SEL, SAIF, and
SAOF should be connected as close as possible to VL or GND.
CS8421
DS641PP1
33
10. PACKAGE DIMENSIONS
Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not
reduce dimension "b" by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
THERMAL CHARACTERISTICS
INCHES
MILLIMETERS
NOTE
DIM
MIN
NOM
MAX
MIN
NOM
MAX
A
--
--
0.043
--
--
1.10
A1
0.002
0.004
0.006
0.05
--
0.15
A2
0.03346
0.0354
0.037
0.85
0.90
0.95
b
0.00748
0.0096
0.012
0.19
0.245
0.30
2,3
D
0.252
0.256
0.259
6.40
6.50
6.60
1
E
0.248
0.2519
0.256
6.30
6.40
6.50
E1
0.169
0.1732
0.177
4.30
4.40
4.50
1
e
--
--
0.026
--
--
0.65
L
0.020
0.024
0.028
0.50
0.60
0.70
0
4
8
0
4
8
JEDEC #: MO-153
Controlling Dimension is Millimeters.
Parameter
Symbol
Min
Typ
Max
Units
Junction to Ambient Thermal Impedance
2 Layer Board
4 Layer Board
JA
-
-
48
38
-
-
C/Watt
C/Watt
20L TSSOP (4.4 mm BODY) PACKAGE DRAWING
E
N
1 2 3
e
b
2
A1
A2
A
D
SEATING
PLANE
E1
1
L
SIDE VIEW
END VIEW
TOP VIEW
CS8421
34
DS641PP1
20-PIN QFN (5
5 MM BODY) PACKAGE DRAWING
Notes: 1. Dimensioning and tolerance per ASME Y 14.5M-1995.
2. Dimensioning lead width applies to the plated terminal and is measured between 0.23mm and 0.33mm
from the terminal tip.
THERMAL CHARACTERISTICS
INCHES
MILLIMETERS
NOTE
DIM
MIN
NOM
MAX
MIN
NOM
MAX
A
--
--
0.0394
--
--
1.00
1
A1
0.0000
--
0.0020
0.00
--
0.05
1
b
0.0091
0.0110
0.0130
0.23
0.28
0.33
1,2
D
0.1969 BSC
5.00 BSC
1
D2
0.1201
0.1220
0.1240
3.05
3.10
3.15
1
E
0.1969 BSC
5.00 BSC
1
E2
0.1202
0.1221
0.1241
3.05
3.10
3.15
1
e
0.0256 BSC
0.65 BSC
1
L
0.0197
0.0236
0.0276
0.50
0.60
0.70
1
JEDEC #: MO-220
Controlling Dimension is Millimeters.
Side View
A
A1
D2
L
b
e
Pin #1 Corner
Bottom View
Top View
Pin #1 Corner
D
E
E2
Parameter
Symbol
Min
Typ
Max
Units
Junction to Ambient Thermal Impedance
2 Layer Board
4 Layer Board
JA
-
-
131
38
-
-
C/Watt
C/Watt
CS8421
DS641PP1
35
11. REVISION HISTORY
Release
Date
Changes
A1
July 2004
Initial Advance Release
PP1
January 2005
-Updated "Features" on page 1.
-Updated "Sample Rate with other XTI clocks" on page 6.
-Updated "DC Electrical Characteristics" on page 7.
-Updated "Digital Input Characteristics" on page 7.
-Updated "Digital Interface Specifications" on page 7
-Updated Figure 5. "Typical Connection Diagram, Master and Slave
Modes" on page 10.
-Added Figure 6. "Typical Connection Diagram, No External Master
Clock" on page 11.
-Corrected reference to bypass mode to output only data on page 12.
-Added section 6.1, "Clocking" on page 15.
-Updated "Master Clock" on page 17.
-Updated "Time Division Multiplexing (TDM) Mode" on page 18.
-Added Thermal Pad label "Pin Descriptions" on page 20.
-Added Thermal Pad pin description to "QFN Pin Descriptions" on
page 22.
-Updated "Performance Plots" beginning on page 23.
Table 6. Revision History
CS8421
36
DS641PP1
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to
www.cirrus.com
IIMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its sub-
sidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and
is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before
placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order
acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this informa-
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE-
VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED
IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA-
TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.
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or service marks of their respective owners.