Copyright
Cirrus Logic, Inc. 1999
(All Rights Reserved)
CS8900A
Product Data Sheet
&U\VWDO /$1
TM ISA Ethernet
Controller
FEATURES
s
Single-Chip IEEE 802.3 Ethernet Controller with
Direct ISA-Bus Interface
s
Maximum Current Consumption = 55 mA (5V Supply)
s
3 V Operation
s
Industrial Temperature Range
s
Comprehensive Suite of Software Drivers Available
s
Efficient PacketPageTM Architecture Operates in
I/O and Memory Space, and as DMA Slave
s
Full Duplex Operation
s
On-Chip RAM Buffers Transmit and Receive Frames
s
10BASE-T Port with Analog Filters, Provides:
-- Automatic Polarity Detection and Correction
s
AUI Port for 10BASE2, 10BASE5 and 10BASE-F
s
Programmable Transmit Features:
-- Automatic Re-transmission on Collision
-- Automatic Padding and CRC Generation
s
Programmable Receive Features:
-- Stream TransferTM for Reduced CPU Overhead
-- Auto-Switch Between DMA and On-Chip Memory
-- Early Interrupts for Frame Pre-Processing
-- Automatic Rejection of Erroneous Packets
s
EEPROM Support for Jumperless Configuration
s
Boot PROM Support for Diskless Systems
s
Boundary Scan and Loopback Test
s
LED Drivers for Link Status and LAN Activity
s
Standby and Suspend Sleep Modes
DESCRIPTION
The CS8900A is a low-cost Ethernet LAN Controller op-
timized for Industry Standard Architecture (ISA)
Personal Computers. Its highly-integrated design elimi-
nates the need for costly external components required
by other Ethernet controllers. The CS8900A includes
on-chip RAM, 10BASE-T transmit and receive filters,
and a direct ISA-Bus interface with 24 mA Drivers.
In addition to high integration, the CS8900A offers a
broad range of performance features and configuration-
options. Its unique PacketPage architecture
automatically adapts to changing network traffic pat-
terns and available system resources. The result is
increased system efficiency.
The CS8900A is available in a 100-pin TQFP package-
ideally suited for small form-factor, cost-sensitive
Ethernet applications. With the CS8900A, system engi-
neers can design a complete Ethernet circuit that
occupies less than 1.5 square inches (10 sq. cm) of
board space.
ORDERING INFORMATION
CS8900A-CQ 0 to 70 C 5V TQFP-100
CS8900A-IQ -40 to 85 C 5V TQFP-100
CS8900A-CQ3 0 to 70 C
3.3V TQFP-100
CS8900A-IQ3 -40 to 85 C 3.3V TQFP-100
CRD8900A-1
Evaluation Kit
EEPROM
RJ-45
10BASE-T
Attachment
Unit
Interface
(AUI)
20 MHz
XTAL
RAM
ISA
Bus
Logic
Memory
Manager
802.3
MAC
Engine
EEPROM
Control
Encoder/
Decoder
&
PLL
10BASE-T
RX Filters &
Receiver
10BASE-T
TX Filters &
Transmitter
AUI
Transmitter
AUI
Collision
AUI
Receiver
Clock
Power
Manager
Boundary
Scan
Test Logic
LED
Control
CS8900A ISA Ethernet Controller
I
S
A
DS271PP3
MAR `99
CIRRUS LOGIC PRODUCT DATA SHEET
2
DS271PP3
CS8900A
Crystal LANTM ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
TABLE OF CONTENTS
1.0 INTRODUCTION ......................................................................................................................................... 8
1.1 General Description............................................................................................................................... 8
1.1.1 Direct ISA-Bus Interface .............................................................................................................. 8
1.1.2 Integrated Memory....................................................................................................................... 8
1.1.3 802.3 Ethernet MAC Engine ........................................................................................................ 8
1.1.4 EEPROM Interface ...................................................................................................................... 8
1.1.5 Complete Analog Front End ........................................................................................................ 8
1.2 System Applications .............................................................................................................................. 8
1.2.1 Motherboard LANs....................................................................................................................... 8
1.2.2 Ethernet Adapter Cards ............................................................................................................... 9
1.3 Key Features and Benefits .................................................................................................................. 10
1.3.1 Very Low Cost ........................................................................................................................... 10
1.3.2 High Performance ...................................................................................................................... 10
1.3.3 Low Power and Low Noise ........................................................................................................ 10
1.3.4 Complete Support ...................................................................................................................... 10
2.0 PIN DESCRIPTION ................................................................................................................................ 12
3.0 FUNCTIONAL DESCRIPTION .................................................................................................................. 17
3.1 Overview ............................................................................................................................................. 17
3.1.1 Configuration ............................................................................................................................. 17
3.1.2 Packet Transmission.................................................................................................................. 17
3.1.3 Packet Reception....................................................................................................................... 17
3.2 ISA Bus Interface ................................................................................................................................ 18
3.2.1 Memory Mode Operation ........................................................................................................... 18
3.2.2 I/O Mode Operation ................................................................................................................... 18
3.2.3 Interrupt Request Signals .......................................................................................................... 18
3.2.4 DMA Signals .............................................................................................................................. 18
3.3 Reset and Initialization ........................................................................................................................ 19
3.3.1 Reset ......................................................................................................................................... 19
3.3.1.1 External Reset, or ISA Reset ........................................................................................... 19
3.3.1.2 Power-Up Reset ............................................................................................................... 19
3.3.1.3 Power-Down Reset .......................................................................................................... 19
3.3.1.4 EEPROM Reset ............................................................................................................... 19
3.3.1.5 Software Initiated Reset ................................................................................................... 19
3.3.1.6 Hardware (HW) Standby or Suspend ............................................................................... 19
3.3.1.7 Sof tware (SW) Suspend .................................................................................................. 19
3.3.2 Allowing Time for Reset Operation ............................................................................................ 19
3.3.3 Bus Reset Considerations ......................................................................................................... 19
3.3.4 Initialization ................................................................................................................................ 20
3.4 Configurations with EEPROM ............................................................................................................. 21
3.4.1 EEPROM Interface .................................................................................................................... 21
3.4.2 EEPROM Memory Organization ................................................................................................ 21
3.4.3 Reset Configuration Block ......................................................................................................... 21
3.4.3.1 Reset Configuration Block Structure ................................................................................ 21
3.4.3.2 Reset Configuration Block Header ................................................................................... 21
3.4.3.3 Determining the EEPROM Type ...................................................................................... 21
3.4.3.4 Checking EEPROM for presence of Reset Configuration Block ...................................... 21
3.4.3.5 Determining Number of Bytes in the Reset Configuration Block ...................................... 22
3.4.4 Groups of Configuration Data .................................................................................................... 22
3.4.4.1 Group Header................................................................................................................... 23
3.4.5 Reset Configuration Block Checksum ....................................................................................... 23
3.4.6 EEPROM Example .................................................................................................................... 23
3.4.7 EEPROM Read-out ................................................................................................................... 23
DS271PP3
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CS8900A
Crystal LANTM ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
3.4.7.1 Determining EEPROM Size ............................................................................................. 23
3.4.7.2 Loading Configuration Data ............................................................................................. 24
3.4.8 EEPROM Read-out Completion ................................................................................................ 24
3.5 Programming the EEPROM ................................................................................................................ 24
3.5.1 EEPROM Commands................................................................................................................ 24
3.5.2 EEPROM Command Execution................................................................................................. 24
3.5.3 Enabling Access to the EEPROM ............................................................................................. 25
3.5.4 Writing and Erasing the EEPROM............................................................................................. 25
3.6 Boot PROM Operation ........................................................................................................................ 25
3.6.1 Accessing the Boot PROM ........................................................................................................ 25
3.6.2 Configuring the CS8900A for Boot PROM Operation................................................................ 25
3.7 Low-Power Modes .............................................................................................................................. 26
3.7.1 Hardware Standby ..................................................................................................................... 26
3.7.2 Hardware Suspend .................................................................................................................... 26
3.7.3 Software Suspend ..................................................................................................................... 27
3.8 LED Outputs........................................................................................................................................ 28
3.8.0.1 LANLED ........................................................................................................................... 28
3.8.0.2 LINKLED or HC0.............................................................................................................. 28
3.8.0.3 BSTATUS or HC1 ............................................................................................................ 28
3.8.1 LED Connection ........................................................................................................................ 28
3.9 Media Access Control ......................................................................................................................... 28
3.9.1 Overview.................................................................................................................................... 28
3.9.2 Frame Encapsulation and Decapsulation .................................................................................. 29
3.9.2.1 Transmission.................................................................................................................... 29
3.9.2.2 Reception ......................................................................................................................... 29
3.9.2.3 Enforcing Minimum Frame Size ....................................................................................... 29
3.9.3 Transmit Error Detection and Handling ..................................................................................... 30
3.9.3.1 Loss of Carrier.................................................................................................................. 30
3.9.3.2 SQE Error......................................................................................................................... 30
3.9.3.3 Out-of-Window (Late) Collision ........................................................................................ 30
3.9.3.4 Jabber Error ..................................................................................................................... 30
3.9.3.5 Transmit Collision............................................................................................................. 30
3.9.3.6 Transmit Underrun ........................................................................................................... 30
3.9.4 Receive Error Detection and Handling ...................................................................................... 31
3.9.4.1 CRC Error ........................................................................................................................ 31
3.9.4.2 Runt Frame ...................................................................................................................... 31
3.9.4.3 Extra Data ........................................................................................................................ 31
3.9.4.4 Dribble Bits and Alignment Error...................................................................................... 31
3.9.5 Media Access Management ...................................................................................................... 31
3.9.5.1 Collision Avoidance.......................................................................................................... 31
3.9.5.2 Two-Part Deferral............................................................................................................. 31
3.9.5.3 Simple Deferral ................................................................................................................ 32
3.9.5.4 Collision Resolution.......................................................................................................... 32
3.9.5.5 Normal Collisions ............................................................................................................. 32
3.9.5.6 Late Collisions.................................................................................................................. 33
3.9.5.7 Backoff ............................................................................................................................. 33
3.9.5.8 Standard Backoff.............................................................................................................. 33
3.9.5.9 Modified Backoff............................................................................................................... 33
3.9.5.10 SQE Test........................................................................................................................ 33
3.10 Encoder/Decoder (ENDEC) .............................................................................................................. 34
3.10.1 Encoder ................................................................................................................................... 34
3.10.2 Carrier Detection ..................................................................................................................... 34
3.10.3 Clock and Data Recovery ........................................................................................................ 34
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DS271PP3
CS8900A
Crystal LANTM ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
3.10.4 Interface Selection ................................................................................................................... 35
3.10.4.1 10BASE-T Only .............................................................................................................. 35
3.10.4.2 AUI Only ......................................................................................................................... 35
3.10.4.3 Auto-Select ..................................................................................................................... 35
3.11 10BASE-T Transceiver...................................................................................................................... 35
3.11.1 10BASE-T Filters ..................................................................................................................... 35
3.11.2 Transmitter............................................................................................................................... 36
3.11.3 Receiver................................................................................................................................... 36
3.11.3.1 Squelch Circuit ............................................................................................................... 36
3.11.3.2 Extended Range............................................................................................................. 36
3.11.4 Link Pulse Detection ................................................................................................................ 36
3.11.5 Receive Polarity Detection and Correction .............................................................................. 37
3.11.6 Collision Detection ................................................................................................................... 37
3.12 Attachment Unit Interface (AUI) ........................................................................................................ 37
3.12.1 AUI Transmitter........................................................................................................................ 37
3.12.2 AUI Receiver............................................................................................................................ 38
3.12.3 Collision Detection ................................................................................................................... 38
3.13 External Clock Oscillator ................................................................................................................... 38
4.0 PACKETPAGE ARCHITECTURE ............................................................................................................ 39
4.1 PacketPage Overview ......................................................................................................................... 39
4.1.1 Integrated Memory..................................................................................................................... 39
4.1.2 Bus Interface Registers ............................................................................................................. 39
4.1.3 Status and Control Registers ..................................................................................................... 39
4.1.4 Initiate Transmit Registers ......................................................................................................... 39
4.1.5 Address Filter Registers............................................................................................................. 39
4.1.6 Receive and Transmit Frame Locations .................................................................................... 39
4.2 PacketPage Memory Map ................................................................................................................... 40
4.3 Bus Interface Registers ....................................................................................................................... 42
4.3.1 Product Identification Code ....................................................................................................... 42
4.3.2 I/O Base Address ...................................................................................................................... 42
4.3.3 Interrupt Number ....................................................................................................................... 43
4.3.4 DMA Channel Number .............................................................................................................. 43
4.3.5 DMA Start of Frame .................................................................................................................. 44
4.3.6 DMA Frame Count ................................................................................................................... 44
4.3.7 RxDMA Byte Count .................................................................................................................. 44
4.3.8 Memory Base Address .............................................................................................................. 44
4.3.9 Boot PROM Base Address ....................................................................................................... 45
4.3.10 Boot PROM Address Mask ..................................................................................................... 45
4.3.11 EEPROM Command ............................................................................................................... 46
4.3.12 EEPROM Data ........................................................................................................................ 46
4.3.13 Receive Frame Byte Counter .................................................................................................. 46
4.4 Status and Control Registers .............................................................................................................. 47
4.4.1 Configuration and Control Registers.......................................................................................... 47
4.4.2 Status and Event Registers ....................................................................................................... 47
4.4.3 Status and Control Bit Definitions .............................................................................................. 47
4.4.3.1 Act-Once Bits ................................................................................................................... 48
4.4.3.2 Temporal Bits ................................................................................................................... 48
4.4.3.3 Interrupt Enable Bits and Events...................................................................................... 48
4.4.3.4 Accept Bits ....................................................................................................................... 48
4.4.4 Status and Control Register Summary ...................................................................................... 49
4.4.5 Register 0: Interrupt Status Queue .......................................................................................... 52
4.4.6 Register 3: Receiver Configuration .......................................................................................... 53
4.4.7 Register 4: Receiver Event ...................................................................................................... 54
DS271PP3
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CS8900A
Crystal LANTM ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
4.4.8 Register 5: Receiver Control ................................................................................................... 55
4.4.9 Register 7: Transmit Configuration .......................................................................................... 56
4.4.10 Register 8: Transmitter Event ................................................................................................ 57
4.4.11 Register 9: Transmit Command Status ................................................................................. 58
4.4.12 Register B: Buffer Configuration ............................................................................................ 59
4.4.13 Register C: Buffer Event ........................................................................................................ 60
4.4.14 Register 10: Receiver Miss Counter ...................................................................................... 61
4.4.15 Register 10: Transmit Collision Counter ................................................................................ 62
4.4.16 Register 13: Line Control ....................................................................................................... 63
4.4.17 Register 14: Line Status ........................................................................................................ 64
4.4.18 Register 15: Self Control ....................................................................................................... 65
4.4.19 Register 16: Self Status ......................................................................................................... 66
4.4.20 Register 17: Bus Control ....................................................................................................... 67
4.4.21 Register 18: Bus Status ......................................................................................................... 68
4.4.22 Register 19: Test Control ....................................................................................................... 69
4.4.23 Register 1C: AUI Time Domain Reflectometer ...................................................................... 70
4.5 Initiate Transmit Registers .................................................................................................................. 71
4.5.1 Transmit Command Request - TxCMD .................................................................................... 71
4.5.2 Transmit Length ........................................................................................................................ 71
4.6 Address Filter Registers...................................................................................................................... 72
4.6.1 Logical Address Filter (hash table) ........................................................................................... 72
4.6.2 Individual Address (IEEE address) ........................................................................................... 72
4.7 Receive and Transmit Frame Locations ............................................................................................. 73
4.7.1 Receive PacketPage Locations ................................................................................................. 73
4.7.2 Transmit Locations .................................................................................................................... 73
4.8 Eight and Sixteen Bit Transfers........................................................................................................... 73
4.8.1 Transferring Odd-Byte-Aligned Data ......................................................................................... 74
4.8.2 Random Access to CS8900A Memory ...................................................................................... 74
4.9 Memory Mode Operation .................................................................................................................... 74
4.9.1 Accesses in Memory Mode ....................................................................................................... 74
4.9.2 Configuring the CS8900A for Memory Mode............................................................................. 74
4.9.3 Basic Memory Mode Transmit ................................................................................................... 75
4.9.4 Basic Memory Mode Receive .................................................................................................... 75
4.9.5 Polling the CS8900A in Memory Mode...................................................................................... 76
4.10 I/O Space Operation ......................................................................................................................... 76
4.10.1 Receive/Transmit Data Ports 0 and 1...................................................................................... 76
4.10.2 TxCMD Port ............................................................................................................................. 76
4.10.3 TxLength Port .......................................................................................................................... 76
4.10.4 Interrupt Status Queue Port..................................................................................................... 76
4.10.5 PacketPage Pointer Port ......................................................................................................... 76
4.10.6 PacketPage Data Ports 0 and 1 .............................................................................................. 77
4.10.7 I/O Mode Operation ................................................................................................................. 77
4.10.8 Basic I/O Mode Transmit ......................................................................................................... 77
4.10.9 Basic I/O Mode Receive .......................................................................................................... 77
4.10.10 Accessing Internal Registers ................................................................................................. 78
4.10.11 Polling the CS8900A in I/O Mode .......................................................................................... 78
5.0 OPERATION ............................................................................................................................................. 79
5.1 Managing Interrupts and Servicing the Interrupt Status Queue .......................................................... 79
5.2 Basic Receive Operation..................................................................................................................... 79
5.2.0.1 Overview .......................................................................................................................... 79
5.2.1 Terminology: Packet, Frame, and Transfer ............................................................................... 81
5.2.1.1 Packet .............................................................................................................................. 81
5.2.1.2 Frame............................................................................................................................... 81
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