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Электронный компонент: CS8952T-CQ

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Copyright
Cirrus Logic, Inc. 2001
(All Rights Reserved)
TX_EN
TX_ER/TXD4
TXD[3:0]
TX_CLK
MDC
MII_IRQ
MDIO
CRS
COL
RX_ER/RXD4
RX_DV
RXD[3:0]
RX_CLK
RX_EN
TX+/-
RX+/-
10/100
MUX
4B/5B
Decoder
Descrambler
Manchester
Encoder
Scrambler
MLT-3
Encoder
10BaseT
Filter
Slew Rate
Control
MUX
10/100
4B/5B
Encoder
Adaptive Eq. &
Baseline Wander
Compensation
10BaseT
Filter
LED
Drivers
100BaseT
Slicer
10BaseT
Slicer
MLT-3
Decoder
Manchester
Decoder
Auto
Negotiation
Timing
Recovery
MII
Control/Status
Registers
Link
Management
CS8952T 10BaseT/100Base-X
Transceiver
M
edi
a
I
ndependent
I
n
t
e
r
f
ace
(MII)
LED1
LED2
LED3
LED4
LED5
CS8952T
Advanced Product Databook
CrystalLANTM 100BASE-X
and 10BASE-T Transceiver
FEATURES
! Single-Chip IEEE 802.3 Physical Interface IC for
100BASE-TX and 10BASE-T
! Adaptive Equalizer provides Extended Length Opera-
tion with Superior Noise Immunity and NEXT Margin
! Extremely Low Transmit Jitter (<400 ps)
! Low Common Mode Noise on TX Driver for Reduced
EMI Problems
! Integrated RX and TX Filters for 10BASE-T
! Compensation for Back-to-Back "Killer Packets"
! Digital Interfaces Supported
-- Media Independent Interface (MII) for 100BASE-X and
10BASE-T
-- Repeater 5-bit code-group interface (100BASE-X)
-- 10BASE-T Serial Interface
! Register Set Compatible with DP83840A
! IEEE 802.3 Auto-Negotiation with Next Page Support
! Six LED drivers (LNK, COL, FDX, TX, RX, and SPD)
! Low power (135 mA Typical) CMOS design operates
on a single 5 V supply
DESCRIPTION
The CS8952T uses CMOS technology to deliver a high-per-
formance, low-cost 100BASE-X/10BASE-T Physical Layer
(PHY) line interface. It makes use of an adaptive equalizer op-
timized for noise and near end crosstalk (NEXT) immunity to
extend receiver operation to cable lengths exceeding 160 m.
In addition, the transmit circuitry has been designed to pro-
vide extremely low transmit jitter (<400 ps) for improved link
partner performance. Transmit driver common mode noise
has been minimized to reduce EMI for simplified FCC
certification.
The CS8952T incorporates a standard Media Independent In-
terface (MII) for easy connection to a variety of 10 and
100 Mb/s Media Access Controllers (MACs).
ORDERING INFORMATION
CS8952T-CQ 0 to 70 C
100-pin TQFP
CS8952T-IQ
-40 to 85 C 100-pin TQFP
CDB8952
Evaluation Board
DS206TPP2
OCT `01
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
2
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
TABLE OF CONTENTS
INTRODUCTION .......................................................................................................................... 4
High Performance Analog ....................................................................................................... 4
Low Power Consumption ........................................................................................................ 4
Application Flexibility ............................................................................................................... 4
Typical Connection Diagram ................................................................................................... 4
PIN DESCRIPTIONS ...................................................................................................................... 6
FUNCTIONAL DESCRIPTION ..................................................................................................... 17
Digital System Interface ......................................................................................................... 17
Major Operating Modes .......................................................................................................... 17
100BASE-TX Nibble Mode ........................................................................................... 17
100BASE-X Symbol Modes ......................................................................................... 20
10BASE-T MII Application ............................................................................................ 21
- 10BASE-T Serial Application ..................................................................................... 22
- Auto-Negotiation .................................................................................................................. 22
- Auto-Negotiation Configuration .................................................................................. 23
- Auto-Negotiation Operation ........................................................................................ 23
Reset Operation ..................................................................................................................... 24
LED Indicators ........................................................................................................................ 24
MEDIA INDEPENDENT INTERFACE .......................................................................................... 25
- MII Frame Structure ............................................................................................................. 25
- MII Receive Data ................................................................................................................. 26
MII Transmit Data ................................................................................................................... 26
MII Management Interface ..................................................................................................... 27
MII Management Frame Structure ......................................................................................... 27
CONFIGURATION ....................................................................................................................... 29
Configuration At Power-up/Reset Time .................................................................................. 29
Configuration Via Control Pins ............................................................................................... 29
Configuration via the MII ........................................................................................................ 29
CS8952T REGISTERS ................................................................................................................. 30
Basic Mode Control Register - Address 00h .......................................................................... 31
Basic Mode Status Register - Address 01h ........................................................................... 33
PHY Identifier Register, Part 1 - Address 02h ........................................................................ 35
PHY Identifier Register, Part 2 - Address 03h ........................................................................ 36
Auto-Negotiation Advertisement Register - Address 04h ....................................................... 37
Auto-Negotiation Link Partner Ability Register - Address 05h ................................................ 38
Auto-Negotiation Expansion Register - Address 06h ............................................................. 39
Auto-Negotiation Next-Page Transmit Register - Address 07h .............................................. 40
Interrupt Mask Register - Address 10h .................................................................................. 41
Interrupt Status Register - Address 11h ................................................................................. 44
Disconnect Count Register - Address 12h ............................................................................. 47
False Carrier Count Register - Address 13h .......................................................................... 48
Scrambler Key Initialization Register - Address 14h .............................................................. 49
Receive Error Count Register - Address 15h ......................................................................... 50
Descrambler Key Initialization Register - Address 16h .......................................................... 51
PCS Sub-Layer Configuration Register - Address 17h .......................................................... 52
Loopback, Bypass, and Receiver Error Mask Register - Address 18h .................................. 55
Self Status Register - Address 19h ........................................................................................ 58
10BASE-T Status Register - Address 1Bh ............................................................................. 60
10BASE-T Configuration Register - Address 1Ch ................................................................. 61
DESIGN CONSIDERATIONS ...................................................................................................... 63
Twisted Pair Interface ............................................................................................................ 63
Internal Voltage Reference .................................................................................................... 63
DS206TPP2
3
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Clocking Schemes ................................................................................................................. 63
Recommended Magnetics ..................................................................................................... 64
Power Supply and Decoupling ...............................................................................................64
General Layout Recommendations ........................................................................................ 64
SPECIFICATIONS AND CHARACTERISTICS ........................................................................... 67
ABSOLUTE MAXIMUM RATINGS.......................................................................................... 67
RECOMMENDED OPERATING CONDITIONS .....................................................................67
QUARTZ CRYSTAL REQUIREMENTS..................................................................................67
DC CHARACTERISTICS ........................................................................................................ 68
DC CHARACTERISTICS (CONT.) .........................................................................................69
SWITCHING CHARACTERISTICS.........................................................................................70
MECHANICAL SPECIFICATIONS .............................................................................................. 82
Package Dimensions ............................................................................................................. 82
Recommended PCB Footprint ...............................................................................................83
REVISION HISTORY ...................................................................................................................84
4
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
INTRODUCTION
The CS8952T is a complete physical-layer trans-
ceiver for 100BASE-TX and 10BASE-T applica-
tions. It provides a Physical Coding Sub-layer for
communication with an external MAC (Media Ac-
cess Controller), a complete Physical Medium At-
tachment layer, and a 100BASE-TX and 10BASE-
T Physical Medium Dependent layer.
High Performance Analog
The highly integrated mixed-signal design of the
CS8952T eliminates the need for external analog
circuitry such as transmit or receive filters. The
CS8952T builds upon Cirrus Logic's experience in
pioneering the high-volume manufacturing of
10BASE-T integrated circuits with "true" internal
filters. The CS8952T, CS8920, CS8904, and
CS8900 include fifth-order, continuous-time But-
terworth 10BASE-T transmit and receive filters, al-
lowing those products to meet 10BASE-T wave
shape, emission, and frequency content require-
ments without external filters.
Low Power Consumption
The CS8952T is implemented in low power
CMOS, consuming only 135 mA typically. Three
low-power modes are provided to make the
CS8952T ideal for power sensitive applications.
Application Flexibility
The CS8952T's digital interface and operating
modes can be tailored to efficiently support a wide
variety of applications. For example, the Media In-
dependent Interface (MII) supports 100BASE-TX
and 10BASE-T NIC cards, switches and routers.
Additionally, the low-latency "repeater" interface
mode minimizes data delay through the CS8952T,
facilitating system compliance with overall net-
work delay budgets. To support 10BASE-T appli-
cations, the CS8952T provides a 10BASE-T serial
port (Seven-wire ENDEC interface).
Typical Connection Diagram
Figure 1 illustrates a typical MII to CS8952T appli-
cation with twisted-pair interfaces. Refer to the De-
sign
Considerations
section
for
detailed
information on power supply requirements and de-
coupling, crystal and magnetics requirements, and
twisted-pair transceiver connections.
DS206TPP2
5
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
VSS
RES
VSS
4.99K
XTAL_I
XTAL_O
MDIO
33
MDC
TXD[3:0]
TX_ER/TXD[4]
TX_EN
TX_CLK
RX_CLK
RXD[3]/PHYAD[3]
RX_ER/RXD[4]/PHYAD[4]
RX_DV/MII_DRV
COL/PHYAD0
CRS/PHYAD[2]
4
MII
I
nte
r
fac
e
SPEED10
SPEED100
LED1
LED2
LED3
LED4
LED5
VDD
VDD_MII
VDD_MII
VDD
10F
0.1F
RSVD
VSS
TEST0
TEST1
AN0
AN1
NC
NC
CS8952
RX_EN
PWRDN
REPEATER
BP4B5B
BPALIGN
LPBK
ISODEF
10BT_SER
RESET
MII_IRQ
C
o
n
t
r
o
l
I
nt
er
f
a
c
e
LPSTRT
TCM
TXSLEW0
TXSLEW1
NC
NC
1.5K
VDD_MII
RXD[2]
RXD[1]/PHYAD[1]
RXD[0]
VDD_MII
4.7K
680
VDD_MII
+
3
3
11
11
10F
0.1F
+
25MHz
49.9
0.1F
TX+
TX-
RX+
RX-
1
2
3
4
5
6
7
8
RJ-45
SHLD
SHLD
7
Transformer
5
1%
49.9
1%
0.1F
75
75
0.01F
2KV
51
51
51
51
51
51
680
680
680
680
680
680
4.7K
4.7K
33
33
33
33
33
33
33
33
33
NC
1%
19
7
10V
10V
Figure 1. Typical Connection Diagram
6
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
PIN DESCRIPTIONS
Pin Diagram
VSS
VDD
VSS
NC
NC
NC
NC
NC
NC
VSS
VDD
VSS
VSS
RX_EN
RESET
REPEATER
CLK25
VSS
VDD
VSS
VDD_MII
VSS
10BT_SER
TEST0
TEST1
RSVD
RSVD
LED5
LED4
LED3
LED2
LED1
SPD10
SPD100
VDD_MII
VSS
PWRDN
ISODEF
VSS
TXSLEW1
TXSLEW0
TCM
AN1
AN0
BP4B5B
VSS
VDD
VSS
BPALIGN
LPBK
M
II_
IR
Q
MD
I
O
MD
C
RX
D2
RX
D1/
P
HY
A
D
1
RX
D0
RX
_DV
/
M
I
I
_
DRV
V
DD_M
I
I
VSS
RX
_CLK
RX
_E
R/
RX
D4/
P
HY
A
D
4
TX
_
E
R
/
TX
D
4
VSS
VD
D
VSS
T
X
_CLK
TX
_
E
N
TX
D
0
TX
D
1
TX
D
2
TX
D
3
C
O
L
/
PH
YAD
0
CRS
/
P
HY
A
D
2
L
PST
R
T
VD
D
R
SVD
R
SVD
XT
AL
_
O
XT
AL
_
I
VSS
VD
D
VSS
RX
-
RX
+
VSS
VD
D
VD
D
VSS
RE
S
VSS
R
SVD
VSS
VD
D
TX
-
TX
+
VD
D
VSS
R
SVD
R
SVD
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
RX
D3/
P
HY
A
D
3
CS8952
100-pin
TQFP
(14 mm x 14 mm)
DS206TPP2
7
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
MII Interface Pins
COL/PHYAD0 - Collision Detect/PHY Address 0. Input/Tri-State Output, Pin 48.
Asserted active-high to indicate a collision on the medium during half-duplex operation. In
full-duplex operation, COL is undefined and should be ignored. When configured for 10 Mb/s
operation, COL is also used to indicate a Signal Quality Error (SQE) condition.
At power-up or at reset, the logic value on this pin is latched into bit 0 of the PHY Address
field of the Self Status Register (address 19h). This pin includes a weak internal pull-down
(~ 20 K
), or the value may be set by an external 4.7 K
pull-up or pull-down resistor.
NOTE: Silicon revisions A and B included a weak internal pull-up rather than a pull-down.
CRS/PHYAD2 - Carrier Sense/PHY Address 2. Input/Tri-State Output, Pin 49.
The operation of CRS is controlled by the REPEATER pin as follows:
At power-up or at reset, the logic value of this pin is latched into bit 2 of the PHY Address
Field of the Self Status Register (address 19h). This pin includes a weak internal pull-down
(> 20 K
), or the value may be set by an external 4.7 K
pull-up or pull-down resistor.
MDC - Management Data Clock. Input, Pin 28.
Input clock used to transfer serial data on MDIO. The maximum clock rate is 16.67 MHz. This
clock may be asynchronous to RX_CLK and TX_CLK.
MDIO - Management Data Input/Output. Bi-Directional, Pin 27.
Bi-directional signal used to transfer management data between the CS8952T and the Ethernet
controller.
In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin
should be pulled high during power-up or reset, and the MDIO pin should have an external
1.5 K
pull-up resistor.
MII_IRQ - MII Interrupt. Open Drain Output, Pin 26.
Asserted low to indicate the status corresponding to one of the unmasked interrupt status bits in
the Interrupt Status Register (address 11h) has changed. It will remain low until the ISR is read,
clearing all status bits.
This open drain pin requires a 4.7 k
pull-up resistor.
REPEATER pin
DUPLEX mode
CRS Indicates
high
don't care
receive activity only
low
full duplex
receive activity only
low
half duplex
receive or transmit activity
8
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
RX_CLK - Receive Clock. Tri-State Output, Pin 36
Continuous clock output used as a reference clock for sampling RXD[3:0], RX_ER, and
RX_DV. RX_CLK will have the following nominal frequency:
In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin
should be pulled high during power-up or reset, and the RX_CLK pin should have an external
33
series resistor. For systems not required to drive external connectors and cables as
described in the IEEE802.3u specification, the external series resistor may not be necessary.
RX_DV/MII_DRV - Receive Data Valid/MII Drive Strength. Input/Tri-State Output, Pin 33.
Asserted high to indicate valid data nibbles are present on RXD[3:0].
At power-up or at reset, this pin is used as an input to determine the drive strength of the MII
output drivers. When the pin is low, all MII output drivers will be standard 4 mA CMOS
drivers. When high, additional drive strength will be added to the MII output drivers. This pin
includes a weak internal pull-down (> 20 K
), or the value may be set by an external 4.7 K
pull-up or pull-down resistor.
In order to conform with Annex 22B of the IEEE 802.3u specification, this pin should be
pulled high during power-up or reset and should have an external 33
series resistor. For
systems not required to drive external connectors and cables as described in the IEEE802.3u
specification, it may be possible to reduce overall power consumption by pulling the pin low at
power-up or reset, and the external series resistor may not be necessary.
RX_EN - Receive Enable. Input, Pin 14.
When high, signals RXD[3:0], RX_CLK, RX_DV, and RX_ER are enabled. When low, these
signals are tri-stated. RX_EN allows the received data signals of multiple PHY transceivers to
share the same MII bus.
This pin includes a weak internal pull-up (> 150 K
), or the value may be set by an external
10 K
pull-up or pull-down resistor.
RX_ER/PHYAD4/RXD4 - Receive Error/PHY Address 4/Receive Data 4. Input/Tri-State Output,
Pin 37.
During normal MII operation, this pin is defined as RX_ER (Receive Error). When RX_DV is
high, RX_ER asserted high indicates that an error has been detected in the current receive
frame. When RX_DV is low and RXD[3:0] = "1110", RX_ER high indicates a False Carrier
condition.
Speed
10BT_SER pin
Nominal frequency
100 Mb/s
n/a
25 MHz
10 Mb/s
low (parallel)
2.5 MHz
10 Mb/s
high (serial)
10 MHz
DS206TPP2
9
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
If either BPALIGN or BP4B5B is asserted, then this pin is re-defined as RXD4 (Receive
Data 4), the most-significant bit of the received five-bit code-group. If the 4B5B encoder is
being bypassed, receive data is present when RX_DV is asserted. If alignment is being
bypassed, data reception is continuous.
At power-up or at reset, the logic value on this pin is latched into bit 4 of the PHY Address
field of the Self Status Register (address 19h). This pin includes a weak internal pull-down
(> 20 K
), or the value may be set by an external 4.7 K
pull-up or pull-down resistor.
In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin
should be pulled high during power-up or reset, and the RX_ER pin should have an external
33
series resistor. For systems not required to drive external connectors and cables as
described in the IEEE802.3u specification, the external series resistor may not be necessary.
RXD3/PHYAD3 - Receive Data 3/PHY Address 3. Input/Tri-State Output, Pin 29.
RXD2 - Receive Data 2. Tri-State Output, Pin 30.
RXD1/PHYAD1 - Receive Data 1/PHY Address 1. Input/Tri-State Output, Pin 31.
RXD0 - Receive Data 0. Tri-State Output, Pin 32.
Receive data output. Receive data is present when RX_DV is asserted. RXD0 is the least-
significant bit. For MII modes, nibble-wide data (synchronous to RX_CLK) is transferred on
pins RXD[3:0]. In 10 Mb/s serial mode, pin RXD0 is used as the serial output pin, and
RXD[3:1] are ignored. When either BP4B5B or BPALIGN is selected, pin RXD4 contains the
most-significant bit of the five-bit code-group.
At power-up or at reset, the value on RXD1/PHYAD1 is latched into bit 1 of the PHY Address
field of the Self Status Register (address 19h). This pin includes a weak internal pull-down
(> 20 K
), or the value may be set by an external 4.7 K
pull-up or pull-down resistor.
At power-up or at reset, the logic value on RXD3/PHYAD3 is latched into bit 3 of the PHY
Address field of the Self Status Register (address 19h). This pin includes a weak internal pull-
down (> 20 K
), or the value may be set by an external 4.7 K
pull-up or pull-down resistor.
In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin
should be pulled high during power-up or reset, and the RXD[3:0] pins should have external
33
series resistors. For systems not required to drive external connectors and cables as
described in the IEEE802.3u specification, the external series resistors may not be necessary.
TX_CLK - Transmit Clock. Input/Tri-State Output, Pin 42.
Continuous clock signal used by the CS8952T as a reference clock to sample TXD[3:0],
TX_ER, and TX_EN. TX_CLK can be referenced either internally (Output Mode) or externally
(Input Mode) based upon the value of the TCM pin at power-up or at reset.
TCM pin
TX_CLK mode
CLK25 status
high
TX_CLK is input
CLK25 pin is an output
floating
TX_CLK is input
CLK25 is disabled
low
TX_CLK is output
CLK25 is disabled
10
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
When the TCM pin is high on power-up or reset, the CLK25 pin may be used as a source for
the TX_CLK pin. When the TCM pin is floating on power-up or reset, TX_CLK must be
supplied externally. TX_CLK should have the following nominal frequency:
TX_EN - Transmit Enable. Input, Pin 43.
Asserted high to indicate valid data nibbles are present on TXD[3:0]. When BPALIGN is
selected, TX_EN must be pulled up to VDD_MII.
TX_ER/TXD4 - Transmit Error Encoding/Transmit Data 4. Input, Pin 38.
When high, TX_ER indicates to the CS8952T that a transmit error has occurred. If TX_ER is
asserted simultaneously with TX_EN in 100 Mb/s mode, the CS8952T will ignore the data on
the TXD[3:0] pins and transmit one or more 100 Mb/s HALT symbols in its place. In 10 Mb/s
mode, TX_ER has no effect on the transmitted data.
If BP4B5B or BPALIGN are set, TX_ER/TXD4 is used to transmit the most-significant bit of
the five-bit code group.
TXD[3:0] - Transmit Data. Input, Pins 47, 46, 45, and 44.
Transmit data input pins. For MII modes, nibble-wide data (synchronous to TX_CLK) must be
presented on pins TXD[3:0] when TX_EN is asserted high. TXD0 is the least significant bit. In
10 Mb/s serial mode, pin TXD0 is used as the serial input pin, and TXD[3:1] are ignored.
When either BP4B5B or BPALIGN is selected, pin TXD4 contains the most significant bit of
the five-bit code-group.
Control and Status Pins
10BT_SER - 10 Mb/s Serial Mode Select. Input, Pin 23.
When asserted high during power-up or reset and 10 Mb/s operation is selected, serial data will
be transferred on pins RXD0 and TXD0. When low during power-up or reset and 10 Mb/s
operation is selected, data is transferred a nibble at a time on RXD[3:0] and TXD[3:0]. This
pin is ignored during 100 Mb/s operation.
10 Mb/s serial mode may also be entered under software control through bit 9 of the 10BASE-
T Status Register (address 1Bh).
At power-up or at reset, the value on this pin is latched into bit 9 of the 10BASE-T Status
Register (address 1Bh). This pin includes a weak internal pull-down (> 20 K
), or the value
may be set by an external 4.7 K
pull-up or pull-down resistor.
Speed
10BT_SER pin
Nominal frequency
100 Mb/s
low (nibble)
25 MHz
10 Mb/s
low (nibble)
2.5 MHz
10 Mb/s
high (serial)
10 MHz
DS206TPP2
11
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
AN[1:0] - Auto-Negotiate Control. Input, Pins 58 and 57.
These three-level input pins are sampled during power-up or reset. They control the forced or
advertised auto-negotiation operating modes. If either of these pins is left unconnected, internal
logic pulls its signal to a mid-range value, designated as 'M' in the following table. Either pin
may also be connected to a 5 to 25 MHz TTL-level clock source, designated as 'C' in the
following table. A minimum of 8 rising edges of the clock are required while RESET is
asserted for the AN[1:0] input logic to interpret the input as 'C'.
Auto-Negotiation may also be enabled and the advertised capabilities modified under software
control through bit 8 of the Basic Mode Control Register (address 00h), and bits 5, 6, 7, 8, and
10 of the Auto-Negotiation Advertisement Register (address 04h).
These pins are pulled to `M' through weak internal resistors (> 150 K
). Other values may be
set by tying them directly to VDD_MII, VSS, or a clock source, or through external 10 K
pull-up or pull-down resistors.
BP4B5B - Bypass 4B5B Coders. Input, Pin 56.
When driven high during power-up or reset, the transmit 4B5B encoder and receiver 5B4B
decoder are bypassed. Five-bit code groups are output and input on pins RXD[4:0] and
TXD[4:0].
The 4B5B Coders may also be bypassed under software control through bit 14 of the
Loopback, Bypass, and Receiver Error Mask Register (address 18h).
AN1 pin
AN0 pin
Forced/Auto
Speed
Full/Half Duplex
0
M
Forced
10 Mb/s
Half
1
M
Forced
10 Mb/s
Full
M
0
Forced
100 Mb/s
Half
M
1
Forced
100 Mb/s
Full
C
M
Forced
100 Mb/s
Full (Note 1)
1.
The Auto-Negotiation Advertisement Register will be modified to advertise 100 Mb/s
Full/Half.
M
C
Forced
100 Mb/s
Full (Note 2)
2.
The Auto-Negotiation Advertisement Register will be modified to advertise
100/10 Mb/s Full.
C
C
Forced
100 Mb/s
Half (Note 3)
3.
The Auto-Negotiation Advertisement Register will be modified to advertise
100/10 Mb/s Half.
M
M
Auto-Neg
100/10 Mb/s
Full/Half
0
0
Auto-Neg
10 Mb/s
Half
0
1
Auto-Neg
10 Mb/s
Full
1
0
Auto-Neg
100 Mb/s
Half
1
1
Auto-Neg
100 Mb/s
Full
C
1
Auto-Neg
100/10 Mb/s
Full
C
0
Auto-Neg
100/10 Mb/s
Half
1
C
Auto-Neg
100 Mb/s
Full/Half
0
C
Auto-Neg
10 Mb/s
Full/Half
12
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
At power-up or at reset, the value on this pin is latched into bit 14 of the Loopback, Bypass
and Receiver Error Mask Register (address 18h). This pin includes a weak internal pull-down
(> 20 K
), or the value may be set by an external 4.7 K
pull-up or pull-down resistor.
BPALIGN - Bypass Symbol Alignment. Input, Pin 52.
When driven high during power-up or reset, the following blocks are bypassed: 4B5B encoder,
5B4B decoder, scrambler and descrambler. Five-bit code groups are output and input on pins
RXD[4:0] and TXD[4:0]. The receiver will output five-bit data with no attempt to identify
code-group boundaries; therefore, the data in one RXD[4:0] word may contain data from two
code groups.
Symbol alignment may also be bypassed under software control through bit 12 of the
Loopback, Bypass, and Receiver Error Mask Register (address 18h).
At power-up or at reset, the value on this pin is latched into bit 12 of the Loopback, Bypass
and Receiver Error Mask Register (address 18h). This pin includes a weak internal pull-down
(> 20 K
), or the value may be set by an external 4.7 K
pull-up or pull-down resistor.
ISODEF - Isolate Default. Input, Pin 63.
When asserted high during power-up or reset, the MII will power-up electrically isolated except
for the MDIO and MDC pins. When low, the part will exit reset fully electrically connected to
the MII.
The MII may also be isolated under software control through bit 10 of the Basic Mode Control
Register (address 00h).
At power-up or at reset, the value on this pin is latched into bit 10 of the Basic Mode Control
Register (address 00h). This pin includes a weak internal pull-down (> 20 K
), or the value
may be set by an external 4.7 K
pull-up or pull-down resistor.
LED1 - Transmit Active LED. Open Drain Output, Pin 69.
This active-low output indicates transmit activity. It contains a pulse stretcher to insure that the
transmit events are visible when the pin is used to drive an LED. The definition of this pin may
be modified to indicate Disconnect Detection (bit 5 of the Self Status Register (address 19h))
by setting bit 2 of the PCS Sub-layer Configuration Register (address 17h).
This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input
pin.
LED2 - Receive Activity LED. Open Drain Output, Pin 70.
This active-low output indicates receive activity. It contains a pulse stretcher to insure that the
receive events are visible when the pin is used to drive an LED.
This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input
pin.
DS206TPP2
13
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
LED3 - Link Good LED. Open Drain Output, Pin 71.
This active-low output indicates the CS8952T has detected a valid link.
This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input
pin.
LED4 - Polarity/Full Duplex LED. Open Drain Output, Pin 72.
This active-low output indicates:
1) for 100 Mb/s operation, the CS8952T is in full-duplex operation,
2) for 10 Mb/s operation, either good polarity exists or full duplex is selected (see bit 1 in the
PCS Sub-layer Configuration Register (address 17h)).
This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input
pin.
LED5 - Collision/Descrambler Lock LED. Open Drain Output, Pin 73.
This active-low output is asserted when either the CS8952T detects a collision (bit 11 of the
PCS Sub-Layer Configuration Register (address 17h) is clear), or the 100BASE-TX
descrambler is synchronized (bit 11 of the PCS Sub-Layer Configuration Register (address 17h)
is set).
It contains a pulse stretcher to insure that the collision events are visible when the pin
is used to drive an LED.
This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input
pin.
LPBK - Loopback Enable. Input, Pin 51.
When this pin is asserted high and the CS8952T is operating in 100 Mb/s mode, the CS8952T
will perform a local loopback inside the PMD block. The loopback includes all CS8952T
100 Mb/s functionality except the MLT-3 coders and the analog line interface blocks.
When asserted high and the CS8952T is operating in 10 Mb/s mode, the CS8952T will perform
a local ENDEC loopback.
LPSTRT - Low Power Start. Input, Pin 50.
When this active-low input is asserted during power-up or reset, the CS8952T will exit reset in
a low power configuration, where the only circuitry enabled is that necessary to maintain the
media impedance. The CS8952T will remain in a low power state until RESET pin is asserted
or the MDC pin toggles.
This pin includes a weak internal pull-down (> 20 K
), or the value may be set by an external
4.7 K
pull-up or pull-down resistor.
14
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
PWRDN - Power Down. Input, Pin 64.
When this pin is asserted high, the CS8952T powers down all circuitry except that circuitry
needed to maintain the network line impedance. This is the lowest power mode possible. The
CS8952T will remain in low power mode until the PWRDN pin is deasserted.
A slightly higher power power-down mode may also be entered under software control through
bit 11 of the Basic Mode Control Register (address 00h).
REPEATER - REPEATER Mode Select. Input, Pin 16.
This pin controls the operation of the CRS (Carrier Sense) pin as shown below:
At power-up or at reset, the value on this pin is latched into bit 12 of the PCS Sub-Layer
Configuration Register (address 17h). This pin includes a weak internal pull-down (> 20 K
),
or the value may be set by an external 4.7 K
pull-up or pull-down resistor.
SPD10 - 10 Mb/s Speed Indication. Output, Pin 68.
This pin is asserted high when the CS8952T is configured for 10 Mb/s operation. This pin can
be used to drive a low-current LED to indicate 10 Mb/s operation.
SPD100 - 100 Mb/s Speed Indication. Output, Pin 67.
This pin is asserted high when the CS8952T is configured for 100 Mb/s operation. This pin can
be used to drive a low-current LED to indicate 100 Mb/s operation.
TCM - Transmit Clock Mode Initialization. Input, Pin 59.
The logic value on this three-level pin during power-up or reset determines whether TX_CLK
is used as an input or an output, and whether an external 25 MHz clock reference is provided
on the CLK25 output pin.
TEST[1:0] - Factory Test. Input, Pins 24 and 25.
These pins are for factory test only. They include weak internal pull-downs (> 20 K
), and
should be tied directly to VSS for normal operation.
REPEATER pin
DUPLEX mode
CRS Indicates
high
don't care
receive activity only
low
full duplex
receive activity only
low
half duplex
receive or transmit activity
TCM pin
TX_CLK mode
CLK25 status
high
TX_CLK is input
CLK25 pin is an output
floating
TX_CLK is input
CLK25 is disabled
low
TX_CLK is output
CLK25 is disabled
DS206TPP2
15
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
TXSLEW[1:0] - Transmit Slew Rate Control. Input, Pins 61 and 60.
These three-level pins allow adjustment to the rise and fall times of the 100BASE-TX
transmitter output waveform. The rise and fall times are symmetric.
Media Interface Pins
RX+, RX- - 10/100 Receive. Differential Input Pair, Pins 91 and 92.
Differential input pair receives 10 or 100 Mb/s data from the receive port of the transformer
primary.
TX+, TX- - 10/100 Transmit. Differential Output Pair, Pins 80 and 81.
Differential output pair drives 10 or 100 Mb/s data to the transmit port of the transformer
primary.
General Pins
CLK25 - 25 MHz Clock. Tristate Output, Pin 17.
A 25 MHz Clock is output on this pin when the CS8952T is configured to use an external
reference transmit clock in TX_CLK IN MASTER mode. See the pin description for the
Transmit Clock Mode Initialization pin (TCM) for more information on TX_CLK operating
modes.
CLK25 may also be enabled regardless of the TCM pin state by clearing bit 7 of the PCS Sub-
layer Configuration Register (address 17h).
RES - Reference Resistor. Input, Pin 86.
This input should be connected to ground with a 4.99 k
+/-1% series resistor. The resistor is
needed for the biasing of internal analog circuits.
TXSLEW0 pin
TXSLEW1 mode
Rise/Fall time
low
low
0.5 ns
low
floating
1.0 ns
low
high
1.5 ns
floating
low
2.0 ns
floating
floating
2.5 ns
floating
high
3.0 ns
high
low
3.5 ns
high
floating
4.0 ns
high
high
4.5 ns
16
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
RESET - Reset. Input, Pin 15.
This active high input initializes the CS8952T, and causes the CS8952T to latch the input
signal on the following pins: COL/PHYAD0, CRS/PHYAD2, RX_ER/PHYAD4/RXD4,
10BT_SER, BP4B5B, BPALIGN, BPSCR, ISODEF, REPEATER, RXD1/PHYAD1, and
RXD3/PHYAD3.
XTAL_I - Crystal Input, Pin 96.
XTAL_O - Crystal Output, Pin 97.
A 25 MHz crystal should be connected across pins XTAL_I and XTAL_O. If a crystal is not
used, a 25 MHz CMOS level clock may be connected to XTAL_I and XTAL_O left open.
NOTE: The XTAL_I pin capacitive load may be as high as 35pF. Any external clock source connected to this pin
must be capable of driving larger capacitive loads.
RSVD - Reserved. Pins 74, 75, 76, 77, 84, 98, and 99.
These seven pins are reserved and should be tied to VSS.
VDD_MII - I/O Pad Power. Pins 21, 34, and 66.
These pins provide power to all CS8952T digital I/O pads. Typically VDD_MII will be either
+5V or +3.3V.
VDD - Core Power. Pins 2, 11, 19, 40, 54, 79, 82, 88, 89, 94, and 100.
These pins provide power to the CS8952T core. Typically, VDD should be +5V.
VSS - Pins 1, 3, 10, 12, 13, 18, 20, 22, 35, 39, 41, 53, 55, 62, 65, 78, 83, 85, 87, 90, 93, and 95.
These pins provide a ground reference for the CS8952T.
DS206TPP2
17
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
FUNCTIONAL DESCRIPTION
Digital System Interface
The primary digital interface to the CS8952T is an
enhanced IEEE 802.3 Media Independent Interface
(MII). The MII supports parallel data transfer, ac-
cess to the CS8952T Control and Status registers,
and several status and control pins.
For 100BASE-X applications, the digital data in-
terface can be either 4-bit parallel (nibbles) or 5-bit
parallel (symbols). For 10BASE-T applications,
the digital data format can be either 4-bit parallel
(nibbles) or one-bit serial.
While the CS8952T can be fully controlled through
configuration registers via the MII Management
Interface, most fundamental functions can be set at
power-up and reset time through external pins.
Major Operating Modes
The following sections describe the four major op-
erating modes of the CS8952T:
-
100BASE-TX Nibble Mode
-
100BASE-X Symbol Modes
-
10BASE-T Nibble Mode
-
10BASE-T Serial Mode
The digital interface mode (nibble, symbol, or seri-
al) is selected through input pins 10BT_SER,
BPALIGN and BP4B5B as shown in Table 1.
Table 1. Operating Mode Selection
The choice of operating speed and duplex mode is
made using the auto-negotiation input pins (AN0,
AN1) and/or the auto-negotiation MII registers.
Both speed and duplex modes can either be forced
or negotiated with the link partner as shown in
Table 5 on page 23.
100BASE-TX Nibble Mode
In 100BASE-TX nibble mode, the CS8952T pro-
vides an IEEE 802.3-compliant MII interface. Data
is transferred across the MII in four-bit nibbles.
TX_CLK and RX_CLK are nominally 25 MHz.
Symbol Encoding and Decoding
Four-bit nibble transmit data is encoded into five-
bit symbols for transmission onto the media as
shown in Tables 2 and 3. While this encoding caus-
es the symbol rate transmitted across the wire (125
symbols/second) to be greater than the actual data
rate of the system (100 symbols/second), it is nec-
essary to allow data and control symbols to be sent
consecutively along the same media transparent to
the MAC layer.
Operating Mode
10BT_SER
BPALIGN
BP4B5B
100BASE-TX Nibble
10BASE-T Nibble
0
0
0
100BASE-TX Symbol
0
0
1
0
1
Don't Care
10BASE-T Serial
1
Don't Care
Don't Care
18
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Table 2. 4B5B Symbol Encoding/Decoding
DATA and CONTROL Codes (RX_ER = 0 or TX_ER = 0)
Name
5-bit Symbol
4-bit Nibble
Comments
DATA (Note 1)
0
11110
0000
1
01001
0001
2
10100
0010
3
10101
0011
4
01010
0100
5
01011
0101
6
01110
0110
7
01111
0111
8
10010
1000
9
10011
1001
A
10110
1010
B
10111
1011
C
11010
1100
D
11011
1101
E
11100
1110
F
11101
1111
CONTROL (Note 2)
I
11111
0101
IDLE (Note 3)
J
11000
0101
First Start of Stream Symbol
K
10001
0101
Second Start of Stream Symbol
T
01101
0000
First End of Stream Symbol
R
00111
0000
Second End of Stream Symbol
1.
DATA code groups are indicated by RX_DV = 1
2.
CONTROL code groups are inserted automatically during transmission in response to
TX_EN. They are not generated through any combination of TXD[3:0] or TX_ER.
3.
IDLE is indicated by RX_DV = 0.
DS206TPP2
19
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Table 3. 4B5B Code Violation Decoding
Carrier Sense Operation
The CRS pin (Carrier Sense) is asserted when ei-
ther the transmitter is active or the receiver detects
at least two non-contiguous ZEROS within any 10
bits in the received data stream. Once asserted, it
will remain asserted until the transmitter has gone
idle or the receiver detects 10 consecutive ONES.
CRS is not synchronous to RX_CLK. It may tran-
sition at any time.
Link Integrity Monitor
The link integrity monitor determines whether the
underlying receive channel is providing reliable
data.
When auto-negotiation is disabled, the link is con-
sidered to be stable when the receiver has detected
valid signal levels for at least 1 ms. If the signal
levels fall below the minimum for more than
350 us, the Link Status bit in the Basic Mode Status
Register (address 01h) is cleared, the Link Status
Change bit in the Interrupt Status Register (address
11h) is set, and the Disconnect Count Register (ad-
dress 12h) is incremented.
When auto-negotiation is enabled, the link will be
further qualified by the detection 100BASE-X
mode and 12 consecutive IDLE code groups.
Collision Detection
For half duplex, a collision is detected when the re-
ceiver and transmitter are active simultaneously.
Collisions are reported by asserting the COL pin.
Code Violations (RX_ER = 1 or TX_ER = 1)
Name
5-bit Symbol
Normal Mode 4-bit
Nibble
Error Report
Mode 4-bit
Nibble
Comments
CONTROL (Note 1)
1.
CONTROL code groups become violations when found in the data portion of the frame.
I
11111
0000
0000
This portion of the table relates received
5-bit symbols to received 4-bit nibbles
only. The control code groups may not
be transmitted in the data portion of the
frame.
J
11000
0000
0000
K
10001
0000
0000
T
01101
0000
0000
R
00111
0000
0000
CODE VIOLATIONS
H
00100
0000
0000
V0
00000
0110 or 0101 (Note 2)
2.
Invalid code groups are mapped to 5h unless the Code Error Report select bit in the Loopback,
Bypass, and Receiver Error Mask Register (address 18h) is set, in which case invalid code groups are
mapped to 6h.
0001
V1
00001
0110 or 0101 (Note 2)
0111
V2
00010
0110 or 0101 (Note 2)
1000
V3
00011
0110 or 0101 (Note 2)
1001
V4
00101
0110 or 0101 (Note 2)
1010
V5
00110
0110 or 0101 (Note 2)
1011
V6
01000
0110 or 0101 (Note 2)
1100
V7
01100
0110 or 0101 (Note 2)
1101
V8
10000
0110 or 0101 (Note 2)
1110
V9
11001
0110 or 0101 (Note 2)
1111
20
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
COL is not synchronous to RX_CLK. It may tran-
sition at any time.
False Carrier Detection
A false carrier condition is detected when the re-
ceiver has asserted CRS but a valid /J/K code group
sequence is not received.
When this condition is detected, the CS8952T will
assert RX_ER and place 1110 on the RXD[3:0]
pins until either the receiver detects at least two
consecutive IDLE code groups. In addition, the
False Carrier Count Register (address 13h) will be
incremented.
100 Mb/s Loopback
The CS8952T includes two 100 Mb/s loopback
modes.
Local loopback redirects the TXD[3:0] input data
to RXD[3:0] data outputs through the 4B5B coders
and scramblers. Local loopback is selected by as-
serting pin LPBK, by setting the LPBK bit (bit 14)
in the Basic Mode Control Register (address 00h)
or by setting bits 8 and 11 in the Loopback, Bypass,
and Receiver Error Mask Register (address 18h) as
shown in Table 4.
Remote loopback redirects the analog line interface
inputs to the analog line driver outputs. Remote
loopback is selected by setting bit 9 in the Loop-
back, Bypass, and Receiver Error Mask Register
(address 18h) as shown in Table 4.
Table 4. Loopback Mode Selection
When changing between local and non-loopback
modes, the data on RXD[3:0] will be undefined for
approximately 330 s.
100BASE-X Symbol Modes
The CS8952T provides two low latency modes for
100BASE-X repeater applications. These are se-
lected by asserting either pin BPALIGN or
BP4B5B. Both pins have the effect of bypassing
the 4B5B encoder and decoder. Bypassing the cod-
ers decreases latency, and uses a 5-bit wide parallel
code group interface on pins RXD[4:0] and
TXD[4:0] instead of the 4-bit wide MII nibble in-
terface on pins RXD[3:0] and TXD[3:0]. In repeat-
er mode, pin RX_ER is redefined as the fifth
receive data bit (RXD4), and pin TX_ER is rede-
fined as the fifth transmit data bit (TXD4).
BPALIGN can also be selected by setting bit 12 in
Loopback, Bypass, and Receiver Error Mask Reg-
ister (address 18h). BP4B5B can be selected by set-
ting bit 14 of the same register.
Pin BPALIGN causes more of the CS8952T to be
bypassed than the BP4B5B pin. BPALIGN also
bypasses the scrambler/descrambler (see Figure 1).
Asserting the REPEATER pin or setting bit 12 in
the PCS Sublayer Configuration Register (address
17h) redefines the function of the CRS (carrier
sense) pin to be asserted only on receive activity.
The REPEATER pin is also used to enable the Car-
rier Integrity Monitor feature by default.
For repeater applications, the RX_EN pin can be
used to gate the receive data pins (RXD[4:0],
RX_CLK, RX_DV, COL, and CRS) onto a shared,
external repeater system bus.
Carrier Integrity Monitor
The Carrier Integrity Monitor function allows a re-
peater to protect the attached network from some
transient fault conditions that would disrupt net-
work communications. The CS8952T contains a
self-interrupt capability to prevent a segment's
Remote
Loopback
(bit 9)
PMD
Loopback
(bit 8)
Function
0
0
No Loopback
0
1
Local Loopback (toward MII)
1
0
Remote Loopback (toward
line)
1
1
Operation is undefined
DS206TPP2
21
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
spurious carrier activity from propagating through
the repeater to other attached segments.
The false carrier detection logic described earlier is
used to increment a false carrier counter. When two
consecutive false carrier events are detected, the
CS8952T will deassert the Link OK bit in the Self
Status Register (address 19h), set the Link Status
Change bit in the Interrupt Status Register (address
11h), increment the Disconnect Count Register
(address 12h), stop propagating received data to the
MII, and ignore any transmit data from the MII.
The receiver will continue to monitor the received
data stream for valid IDLE symbols. Once dis-
abled, the receiver and transmitter will remain dis-
abled until the Link Integrity Monitor has
determined the link has again stabilized.
The Carrier Integrity Monitor may be disabled
through the CIM Disable bit in the PCS Sub-Layer
Configuration Register (address 17h). It is enabled
by default when the REPEATER pin is asserted on
reset or power-up.
10BASE-T MII Application
The digital interface used in this mode is the same
as that used in the 100BASE-X nibble modes ex-
cept that TX_CLK and RX_CLK are nominally
2.5 MHz.
The CS8952T includes a full-featured 10BASE-T
interface, as described in the following sections.
Duplex operation
The CS8952T supports both 10BASE-T full and
half duplex operation as determined by pins
AN[1:0] and/or the corresponding MII register bits.
(See Table 5 on page 23).
Carrier Detection
The carrier detect circuit informs the MAC that
valid receive data is present by asserting the Carrier
Sense signal (CRS) as soon it detects a valid bit
pattern (1010b or 0101b for 10BASE-T). During
normal packet reception, CRS remains asserted
while the frame is being received, and is de-assert-
ed within 2.3 bit times after the last low-to-high
transition of the End-of-Frame (EOF) sequence.
Whenever the receiver is idle (no receive activity),
CRS is de-asserted.
Collision Detection
If half duplex operation is selected, the CS8952T
detects a 10BASE-T collision whenever the receiv-
er and transmitter are active simultaneously. When
a collision is present, the collision is reported on
pin COL.
Collision detection is undefined for full-duplex op-
eration.
Jabber
The jabber timer monitors the transmitter and dis-
ables the transmission if the transmitter is active for
greater than approximately 105 ms. The transmit-
ter stays disabled until approximately 406 ms after
the internal transmit request is no longer enabled.
Link Test Pulses
To prevent disruption of network operation due to
a faulty link segment, the CS8952T continually
monitors the 10BASE-T receive pair (RXD+ and
RXD-) for packets and link pulses. After each
packet or link pulse is received, an internal Link-
Loss timer is started. As long as a packet or link
pulse is received before the Link-Loss timer finish-
es (between 50 and 100 ms), the CS8952T main-
tains normal operation. If no receive activity is
detected, the CS8952T disables packet transmis-
sion to prevent "blind" transmissions onto the net-
work (link pulses are still sent while packet
transmission is disabled). To reactivate transmis-
sion, the receiver must detect a single packet (the
packet itself is ignored), or two normal link pulses
separated by more than 6 ms and no more than
50 ms.
In the absence of transmit packets, the transmitter
generates
link
pulses
in
accordance
with
22
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Section 14.2.1.1 of the Ethernet standard. Trans-
mitted link pulses are positive pulses, one bit time
wide, typically generated at a rate of one every
16 ms. The 16 ms timer also starts whenever the
transmitter completes an End-of-Frame (EOF) se-
quence. Thus, a link pulse will be generated 16 ms
after an EOF unless there is another transmitted
packet.
Link Polarity Detection
The CS8952T automatically checks the polarity of
the receive half of the twisted pair cable. To detect
a reversed pair, the receiver examines received link
pulses and the End-of-Frame (EOF) sequence of
incoming packets. If it detects at least one reversed
link pulse and at least four frames in a row with
negative polarity after the EOF, the receive pair is
considered reversed.
If the polarity is reversed and the Polarity Disable
bit of the 10BASE-T Configuration Register (ad-
dress 1Ch) is clear, the CS8952T automatically
corrects a reversal.
SQE (Heartbeat) Test Function
When SQE is enabled, the CS8952T will assert the
COL pin for approximately 10 bit times within 1
s
after the transmission of each packet.
The SQE function is disabled by default when the
REPEATER pin is deasserted on reset or power-
up. It may be enabled through the SQE Enable bit
in the 10BASE-T Configuration Register (address
1Ch).
Receiver Squelch
The 10BASE-T squelch circuit determines when
valid data is present on the RXD+/RXD- pair. In-
coming signals passing through the receive filter
are tested by the squelch circuit. Any signal with
amplitude less than the squelch threshold (either
positive or negative, depending on polarity) is re-
jected.
10BASE-T Loopback
When Loopback is selected, the TXD[3:0] pins are
looped back into the RXD[3:0] pins through the
Manchester Encoder and Decoder. Selection is
made via:
-
setting bit 14 in the Basic Mode Control
Register (address 00h) or
-
setting bits 8 and 11 in the Loopback, By-
pass, and Receiver Error Mask Register
(address 18h) or
-
asserting the LPBK pin.
10BASE-T Serial Application
This mode is selected when pin 10BT_SER is as-
serted during power-up or reset, and operates simi-
lar to the 10BASE_T MII mode except that data is
transferred serially on pins RXD0 and TXD0 using
a 10 MHz RX_CLK and TX_CLK. Receive data is
framed by CRS rather than RX_DV.
Auto-Negotiation
The CS8952T supports auto-negotiation, which is
the mechanism that allows the two devices on ei-
ther end of an Ethernet link segment to share infor-
mation and automatically configure both devices
for maximum performance. When configured for
auto-negotiation, the CS8952T will detect and au-
tomatically operate full-duplex at 100 Mb/s if the
device on the other end of the link segment also
supports full-duplex, 100 Mb/s operation, and
auto-negotiation. The CS8952T auto-negotiation
capability is fully compliant with the relevant por-
tions of section 28 of the IEEE 802.3u standard.
The CS8952T can auto-negotiate both operating
speed (10 versus 100 Mb/s), duplex mode (half du-
plex versus full duplex), and flow control (pause
frames), or alternatively can be set not to negotiate.
DS206TPP2
23
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Auto-Negotiation Configuration
At power-up and reset times, the auto-negotiation
mode is selected via the auto-negotiation input pins
(AN[1:0]). These three-level input pins are sam-
pled during power-up or reset. If either of these
pins is left unconnected, internal logic pulls its sig-
nal to a mid-range value, designated as 'M' in the
following table. Either pin may also be connected
to a 5 to 25 MHz TTL-level clock source, designat-
ed as `C' in the following table. A minimum of 8
rising edges of the clock are required while RESET
is asserted for the AN[1:0] input logic to interpret
the input as `C'.
Auto-Negotiation may also be enabled and the ad-
vertised capabilities modified under software con-
trol through bit 8 of the Basic Mode Control
Register (address 00h), and bits 5, 6, 7, 8, and 10 of
the Auto-Negotiation Advertisement Register (ad-
dress 04h).
Auto-Negotiation Operation
Auto-Negotiation encapsulates information within
a burst of closely spaced Link Integrity Test Pulses,
referred to as a Fast Link Pulse (FLP) Burst. The
FLP Burst consists of a series of Link Integrity
Pulses which form an alternating clock / data se-
quence. Extraction of the data bits from the FLP
Burst yields a Link Code Word which identifies the
capability of the remote device.
In order to support legacy 10 and 100 Mb/s devic-
es, the CS8952T also supports parallel detection. In
parallel detection, the CS8952T monitors activity
on the media to determine the capability of the link
partner even without auto-negotiation having oc-
curred.
AN1 pin
AN0 pin
Forced/Auto
Speed
Full/Half Duplex
0
M
Forced
10 Mb/s
Half
1
M
Forced
10 Mb/s
Full
M
0
Forced
100 Mb/s
Half
M
1
Forced
100 Mb/s
Full
C
M
Forced
100 Mb/s
Full (Note 1)
M
C
Forced
100 Mb/s
Full (Note 2)
C
C
Forced
100 Mb/s
Half (Note 3)
M
M
Auto-Neg
100/10 Mb/s
Full/Half
0
0
Auto-Neg
10 Mb/s
Half
0
1
Auto-Neg
10 Mb/s
Full
1
0
Auto-Neg
100 Mb/s
Half
1
1
Auto-Neg
100 Mb/s
Full
C
1
Auto-Neg
100/10 Mb/s
Full
C
0
Auto-Neg
100/10 Mb/s
Half
1
C
Auto-Neg
100 Mb/s
Full/Half
0
C
Auto-Neg
10 Mb/s
Full/Half
Table 5. Auto-negotiation Mode Selection
1.
The Auto-Negotiation Advertisement Register will be modified to advertise 100 Mb/s
Full/Half.
2.
The Auto-Negotiation Advertisement Register will be modified to advertise
100/10 Mb/s Full.
3.
The Auto-Negotiation Advertisement Register will be modified to advertise
100/10 Mb/s Half.
24
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Reset Operation
Reset occurs in response to six different conditions:
1) There is a chip-wide reset whenever the RE-
SET pin is high for at least 200 ns. During a
chip-wide reset, all circuitry and registers in the
CS8952T are reset.
2) When power is applied, the CS8952T main-
tains reset until the voltage at the VDD supply
pins
reaches
approximately
3.6 V.
The
CS8952T comes out of reset once VDD is
greater than approximately 3.6 V and the crys-
tal oscillator has stabilized.
3) There is a chip-wide reset whenever the RE-
SET bit (bit 15 of the Basic Mode Control Reg-
ister (address 00h)) is set.
4) Digital circuitry is reset whenever bit 0 of the
PCS Sub-Layer Configuration Register (ad-
dress 17h) is set. Analog circuitry is unaffected.
5) Analog circuitry is reset and recalibrated when-
ever the CS8952T enters or exits the power-
down state, as requested by pin PWRDN.
6) Analog circuitry is reset and recalibrated when-
ever the CS8952T changes between 10 Mb/s
and 100 Mb/s modes.
After a reset, the CS8952T latches the signals on
various input pins in order to initialize key registers
and goes through a self configuration. This in-
cludes calibrating on-chip analog circuitry. Time
required for the reset calibration is typically 40 ms.
External circuitry may access registers internal to
the CS8952T during this time. Reset and calibra-
tion complete is indicated when bit 15 of the Basic
Mode Control Register (address 00h) is clear.
LED Indicators
The LEDx, SPD100, and SPD10 output pins pro-
vide status information that can be used to drive
LEDs or can be used as inputs to external control
circuitry. Indication options include: receive activ-
ity, transmit activity, collision, carrier sense, polar-
ity OK, descrambler synchronization status, auto-
negotiation status, speed (10 vs. 100), and duplex
mode.
DS206TPP2
25
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
MEDIA INDEPENDENT INTERFACE
The Media Independent Interface (MII) provides a
simple interconnect to an external Media Access
Controller (MAC). This connection may be chip to
chip, motherboard to daughterboard, or a connec-
tion between two assemblies attached by a limited
length of shielded cable and an appropriate connec-
tor.
The CS8952T's MII interface is enhanced beyond
IEEE requirements by register extensions and the
addition of pins for MII_IRQ, RX_EN, and ISO-
DEF signals. The MII_IRQ pin provides an inter-
rupt signal to the controller when a change of state
has occurred in the CS8952T, eliminating the need
for the system to poll the CS8952T for state chang-
es. The RX_EN signal allows the receiver outputs
to be electrically isolated. The ISODEF pin con-
trols the value of register bit ISOLATE in the Basic
Mode Control Register (address 00h) which in turn
electrically isolates the CS8952T's MII data path.
The MII interface uses the following pins:
STATUS Pins
-
COL - Collision indication, valid only for
half duplex modes.
-
CRS - Carrier Sense indication
SERIAL MANAGEMENT Pins
-
MDIO - a bi-directional serial data path
-
MDC - clock for MDIO (16.7 MHz max)
-
MII_IRQ - Interrupt indicating change in
the Interrupt Status Register (address 11h)
RECEIVE DATA Pins
-
RXD[3:0] - Parallel data output path
-
RX_CLK - Recovered clock output
-
RX_DV - Indicates when receive data is
present and valid
-
RX_ER - Indicates presence of error in re-
ceived data
-
RX_EN - Can be used to tri-state receiver
output pins
TRANSMIT DATA Pins
-
TXD[3:0] - Parallel data input path
-
TX_CLK - Transmit clock
-
TX_EN - Indicates when transmit data is
present and valid
-
TX_ER - Request to transmit a 100BASE-
T HALT symbol, ignored for 10BASE-T
operation.
The interface uses TTL signal levels, which are
compatible with devices operating at a nominal
supply voltage of either 5.0 or 3.3 volts. It is capa-
ble of supporting either 10 Mb/s or 100 Mb/s data
rates transparently. That is, all signaling remains
identical at either data rate; only the nominal clock
frequency is changed.
MII Frame Structure
Data frames transmitted through the MII have the
following format:
Each frame is preceded by an inter-frame gap. The
inter-frame gap is an unspecified time during
which no data activity occurs on the media as indi-
cated by the de-assertion of CRS for the receive
path and TX_EN for the transmit path.
The Preamble consists of seven bytes of 10101010.
The Start of Frame Delimiter consists of a single
byte of 10101011.
Data may be any number of bytes.
The End of Frame Delimiter is conveyed by the de-
assertion of RX_DV and TX_EN for receive and
transmit paths, respectively.
Preamble
(7 Bytes)
Start of
Frame
Delimiter
(1 Byte)
Data
End of
Frame
Delimiter
26
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Transmission and/or reception of each byte of data
is done one nibble at a time in the following order:
MII Receive Data
The presence of recovered data on the RXD[3:0]
bus is indicated by the assertion of RX_DV.
RX_DV will remain asserted from the beginning of
the preamble (or Start of Frame Delimiter if pream-
ble is not used) to the End of Frame Delimiter.
Once RX_DV is asserted, valid data will be driven
onto RXD[3:0] synchronously with respect to
RX_CLK.
Receive errors are indicated during frame reception
by the assertion of RX_ER. It indicates that an er-
ror was detected somewhere in the frame currently
being transferred across the MII. RX_ER will tran-
sition synchronously with respect to the RX_CLK,
and will be held high for one cycle for each error
received. It is up to the MAC to ensure that a CRC
error is detected in that frame by the Logical Link
Control. Figure 2 illustrates reception without er-
rors, and Figure 3 illustrates reception with errors.
MII Transmit Data
TX_EN is used by the MAC to signal to the
CS8952T that valid nibbles of data are being pre-
sented across the MII via TXD[3:0]. TX_EN must
be asserted synchronously with the first nibble of
preamble, and must remain asserted as long as val-
id data is being presented to the MII.
TX_EN must be de-asserted within one TX_CLK
cycle after the last nibble of data (CRC) has been
presented to the CS8952T. When TX_EN is not as-
serted, data on TXD[3:0] is ignored.
MII
LSB
MSB
D0
D1
D2
D3
Nibble
Stream
D0
MAC's Serial Bit Stream
First Bit
First
Second
Nibble
Nibble
D1 D2 D3 D4 D5 D6 D7
LSB
MSB
RX_CLK
RX_DV
RXD[3:0]
RX_ER
Preamble
SFD
SFD
Data
Data
Data
Data
Data
CRC
Figure 2. Reception without errors
RX_CLK
RX_DV
RXD[3:0]
RX_ER
Preamble
SFD
SFD
Data
Data
Data
Error
XX
XX
XX
Figure 3. Reception with errors
DS206TPP2
27
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Transmit errors should be signaled by the MAC by
asserting TX_ER for one or more TX_CLK cycles.
TX_ER must be synchronous with TX_CLK. This
will cause the CS8952T to replace the nibble with
a HALT symbol in the frame being transmitted.
This invalid data will be detected by the receiving
PHY and flagged as a bad frame. Figure 4 illus-
trates transmission without errors, and Figure 5 il-
lustrates transmission with errors.
MII Management Interface
The CS8952T provides an enhanced IEEE 802.3
MII Management Interface. The interface consists
of three signals: a bi-directional serial data line
(MDIO), a data clock (MDC), and an optional in-
terrupt signal (MII_IRQ). The Management Inter-
face can be used to access status and control
registers internal to the CS8952T. The CS8952T
implements an extended set of 16-bit MII registers.
Eight of the registers are defined by the IEEE 802.3
specification, while the remaining registers provide
enhanced monitoring and control capabilities.
As many as 31 devices may share a single Manage-
ment Interface. A unique five-bit PHY address is
associated with each device, with all devices re-
sponding to PHY address 00000. The CS8952T de-
termines its PHY address at power-up or reset
through the PHYAD[4:0] pins.
MII Management Frame Structure
Frames transmitted through the MII Management
Interface have the format shown in Table 6 on
page 28.
When the management interface is idle, the MDIO
signal will be tri-stated, and the MAC is required to
keep MDIO pulled to a logic ONE.
At the beginning of each transaction, the MAC will
typically send a sequence of 32 contiguous logic
ONE bits on MDIO with 32 corresponding clock
cycles on MDC to provide the CS8952T with a pat-
tern that it can use to establish synchronization.
Optionally, the CS8952T may be configured to op-
TX_CLK
TX_EN
TXD[3:0]
TX_ER
Preamble
Data
Data
Data
Data
Data
Data
Data
CRC
Figure 4. Transmission without errors
TX_CLK
TX_EN
TXD[3:0]
TX_ER
Preamble
Data
Data
Data
XX
Data
Figure 5. Transmission with errors
28
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
erate without the preamble through bit 9 of the PCS
Sub-Layer Configuration Register (address 17h).
Table 6. MII Management Interface Frame Format
The Start of Frame is indicated by a 01 bit pattern.
A read transaction is indicated by an Opcode of 10
and a write by 01.
The PHY Address is five bits, with the most signif-
icant bit sent first. If the PHY address included in
the frame is not 00000 or does not match the PHY-
AD field of the Self Status Register (address 19h),
the rest of the frame is ignored.
The register address is five bits, with the most sig-
nificant bit sent first, and indicates the CS8952T
register to be written to/read from.
The Turnaround time is a two bit time spacing be-
tween when the MAC drives the last register ad-
dress bit onto MDIO and the data field of a
management frame in order to avoid contention
during a read transaction. For a read transaction,
the MAC should tri-state the MDIO pin beginning
on the first bit time, and the CS8952T will begin
driving the MDIO signal to a logic ZERO during
the second bit time. During write transactions,
since the MDIO direction does not need to be re-
versed, the MAC will drive the MDIO to a logic
ONE for the first bit time and a logic ZERO for the
second.
The data field is always 16 bits in length, with the
most significant bit sent first.
Preamble
(32 bits)
Start of
Frame
(2 bits)
Opcode
(2 bits)
PHY
Address
(5 bits)
Register
Address
(5 bits)
Turnaround
(2 bits)
Data
(16 bits)
Idle
DS206TPP2
29
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
CONFIGURATION
The CS8952T can be configured in a variety of
ways. All control and status information can be ac-
cessed via the MII Serial Management Interface.
Additionally, many configuration options can be
set at power-up or reset times via individual control
lines. Some configuration capabilities are available
at any time via individual control lines.
Configuration At Power-up/Reset Time
At power-up and reset time, the following pins are
used to configure the CS8952T.
Table 7. Reset Configuration Pins
Configuration Via Control Pins
The following pins are for dedicated control signals
and can be used at any time to configure the
CS8952T.
Table 8. Dedicated Control Pins
Configuration via the MII
The CS8952T supports configuration by software
control through the use of 16-bit configuration and
status registers accessed via the MDIO/MDC pins
(MII Management Interface). The first seven regis-
ters are defined by the IEEE 802.3 specification.
Additional registers extend the register set to pro-
vide enhanced monitoring and control capabilities.
Pin Name
Function
10BT_SER
Select 10BASE-T serial mode
AN[1:0]
Select auto-negotiation mode
BP4B5B
Bypass 4B5B coders
BPALIGN
Bypass 4B5B coders and scramblers
ISODEF
Electrically isolate MII after reset
LPSTRT
Start in low power mode
PHYAD[4:0]
Set MII PHY address
REPEATER
Control definition of CRS pin, enable
carrier integrity monitor and SQE func-
tion
MII_DRV
Set MII driver strength
TCM
Set TX_CLK mode
TXSLEW[1:0] Set 100BASE-TX transmitter output
slew rate
Pin Name
Function
LPBK
Enter loopback mode
PWRDN
Enter power-down mode
RESET
Reset
30
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
CS8952T REGISTERS
The CS8952T register set is comprised of the 16-
bit status and control registers described below. A
detailed description each register follows.
Table 9. CS8952T Register Set
Register Address
Description
Type
0h
Basic Mode Control Register
Read/Write
1h
Basic Mode Status Register
Read-Only
2h
PHY Identifier #1
Read-Only
3h
PHY Identifier #2
Read-Only
4h
Auto-Negotiation Advertisement Register
Read/Write
5h
Auto-Negotiation Link Partner Ability Register
Read-Only
6h
Auto-Negotiation Expansion Register
Read-Only
7h
Auto-Negotiation Next Page Transmit Register
Read/Write
8h through Fh
Reserved by IEEE 802.3 Working Group
-
10h
Interrupt Mask Register
Read/Write
11h
Interrupt Status Register
Read-Only
12h
Disconnect Count Register
Read-Only
13h
False Carrier Count Register
Read-Only
14h
Scrambler Key Initialization Register
Read/Write
15h
Receive Error Count Register
Read-Only
16h
Descrambler Key Initialization Register
Read/Write
17h
PCS Sub-Layer Configuration Register
Read/Write
18h
Loopback, Bypass and Receiver Error Mask Register
Read/Write
19h
Self-Status Register
Read/Write
1Ah
Reserved
-
1Bh
10BASE-T Status Register
Read-Only
1Ch
10BASE-T Configuration Register
Read/Write
1Dh through 1Fh
Reserved
-
DS206TPP2
31
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Basic Mode Control Register - Address 00h
15
14
13
12
11
10
9
8
Software
Reset
Loopback
Speed
Selection
Auto-Neg
Enable
Power Down
Isolate
Restart
Auto-Neg
Duplex Mode
7
6
5
4
3
2
1
0
Collision Test
Reserved
BIT
NAME
TYPE
RESET
DESCRIPTION
15
Software Reset
Read/Set
0
Setting this bit performs a chip-wide reset. All status
and control registers are set to their default states,
and the analog circuitry is re-calibrated. This bit is an
Act-Once bit which is cleared once the reset and re-
calibration have completed.
This bit will also be set automatically while the analog
circuitry is reset and re-calibrated during mode
changes.
14
Loopback
Read/Write 0
When set, the CS8952T is placed in a loop back
mode. Any data sent on the transmit data path is
returned on the receive data path. Loopback mode is
entered regardless of whether 10 Mb/s or 100 Mb/s
operation has been configured.
This bit will be set upon the assertion of the LPBK
pin, and will be automatically cleared upon its deas-
sertion.
13
Speed Selection
Read/Write If auto-negotiation
is enabled via the
AN[1:0] pins, reset
to 1; otherwise,
reset to 0
When bit 12 is clear, setting this bit configures the
CS8952T for 100 Mb/s operation. Clearing this bit
sets the configuration at 10 Mb/s. When bit 12 is set,
this bit is ignored.
12
Auto-Neg Enable
Read/Write If auto-negotiation
is enabled via the
AN[1:0] pins, reset
to 1; otherwise,
reset to 0
Setting this bit enables the auto-negotiation process.
When this bit is set, bits 13 and 8 have no affect on
the link configuration. The link configuration is deter-
mined by the auto-negotiation process. Clearing this
bit disables auto-negotiation.
11
Power Down
Read/Write 0
When this bit is set, the CS8952T enters a low power
consumption state. Clearing this bit allows normal
operation.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
10
Isolate
Read/Write If PHYAD = 00000,
reset to 1; other-
wise reset to the
value on the ISO-
DEF pin
Setting this bit causes the MII data path to be electri-
cally isolated by tri-stating all data outputs (i.e.
TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL,
and CRS). In addition the CS8952T will not respond
to the TXD[3:0], TX_EN, and TX_ER inputs. It will,
however, respond to MDIO and MDC. Clearing this
bit allows normal operation.
32
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Basic Mode Control Register - Address 00h (Cont.)
BIT
NAME
TYPE
RESET
DESCRIPTION
9
Restart Auto-Neg
Read/Set
0
Setting this bit causes auto-negotiation to be
restarted. It is an Act-Once bit which is cleared once
auto-negotiation has begun. Clearing this bit has no
effect on the auto-negotiation process.
8
Duplex Mode
R/W
If auto-negotiation
is enabled via the
AN[1:0] pins, reset
to 0; otherwise,
reset to 1
When bit 12 is clear, this bit controls the Full-
Duplex/Half-Duplex operation of the part. When set,
the part is configured for Full-Duplex operation, and
when clear the part is configured for Half Duplex
operation. The setting of this bit is superseded by
auto-negotiation, and thus has no effect if bit 12 is
set.
7
Collision Test
R/W
0
When set, the COL pin will be asserted within 10 bit
times in response to the assertion of TX_EN. Upon
the deassertion of TX_EN, COL will be deasserted
within 4 bit times. When Collision Test is clear, COL
functions normally.
6:0
Reserved
Read Only
000 0000
DS206TPP2
33
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Basic Mode Status Register - Address 01h
15
14
13
12
11
10
9
8
100BASE-T4
100BASE-TX/
Full Duplex
100BASE-TX/
Half Duplex
10BASE-T/
Full Duplex
10BASE-T/
Half Duplex
Reserved
7
6
5
4
3
2
1
0
Reserved
MF Preamble
Suppression
Auto-Neg
Complete
Remote Fault
Auto-Neg
Ability
Link Status
Jabber Detect
Extended
Capability
BIT
NAME
TYPE
RESET
DESCRIPTION
15
100BASE-T4
Read Only
0
The CS8952T does not support 100BASE-T4 opera-
tion, so this bit will always read 0.
14
100BASE-TX/Full
Duplex
Read Only
1
When this bit is set, it indicates that the CS8952T is
capable of 100BASE-TX Full-Duplex operation. This
bit reflects the status of the 100BASE-TX/Full-Duplex
bit in the Auto-Negotiation Advertisement Register
(address 04h).
13
100BASE-TX/Half
Duplex
Read Only
1
When this bit is set, it indicates that the CS8952T is
capable of 100BASE-TX Half-Duplex operation. This
bit reflects the status of the 100BASE-TX/Half Duplex
bit in the Auto-Negotiation Advertisement Register
(address 04h).
12
10BASE-T/Full
Duplex
Read Only
1
When this bit is set, it indicates that the CS8952T is
capable of 10BASE-T Full-Duplex operation. This bit
reflects the status of the 10BASE-T/Full Duplex bit in
the Auto-Negotiation Advertisement Register
(address 04h).
11
10BASE-T/Half
Duplex
Read Only
1
When this bit is set, it indicates that the CS8952T is
capable of 10BASE-T Half-Duplex operation. This bit
reflects the status of the 10BASE-T/Half Duplex bit in
the Auto-Negotiation Advertisement Register
(address 04h).
10:7
Reserved
Read Only
0000
6
MF Preamble Sup-
pression
Read Only
1
When set, this bit indicates that the CS8952T is capa-
ble of accepting management frames regardless of
whether they are preceded by the preamble pattern.
When clear, it indicates that the management frame
must be preceded by the preamble pattern to be con-
sidered valid. This bit reflects the status of the MR
Preamble Enable bit in the PCS Sub-Layer Configu-
ration Register (address 17h).
5
Auto-Neg Complete Read Only
0
This bit is set to a 1 when the auto-negotiation pro-
cess has completed. This is an indication that data is
valid in the Auto-Negotiation Advertisement Register
(address 04h), the Auto-Negotiation Link Partner
Ability Register (address 05h), and the Auto-Negotia-
tion Expansion Register (address 06h).
4
Remote Fault
Read Only
0
When auto-negotiation is enabled, this bit is set if the
Remote Fault bit is set in the Auto-Negotiation Link
Partner Ability Register (address 05h). When auto-
negotiation is disabled, this bit will be set when a Far-
End Fault Indication for 100BASE-TX is detected.
34
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Basic Mode Status Register - Address 01h (Cont.)
BIT
NAME
TYPE
RESET
DESCRIPTION
3
Auto-Neg Ability
Read Only
1
This bit indicates that the CS8952T has auto-negotia-
tion capability. It will always read back a value of 1.
2
Link Status
Read Only
0
When set, this bit indicates that a valid link has been
established. Upon a link failure, this bit is cleared and
latched. It will remain cleared until this register is
read.
1
Jabber Detect
Read Only
0
In 10BASE-T mode, if the last transmission is longer
than 105 ms, then the packet output is terminated by
the jabber logic and this bit is set. If JabberiE (Inter-
rupt Mask Register (address 10h), bit 3) is set, an MII
Interrupt will be generated.
This bit is implemented with a latching function so
that the occurrence of a jabber condition causes it to
become set until it is cleared by a read to this register,
a read to the Interrupt Status Register (address 11h),
or a reset.
No jabber detect function has been defined for
100BASE-TX.
0
Extended Capability Read Only
1
This bit indicates that an extended register set may
be accessed (registers beyond address 01h). This bit
always reads back a value of 1.
DS206TPP2
35
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
PHY Identifier Register, Part 1 - Address 02h
15
14
13
12
11
10
9
8
Organizationally Unique Identifier: Bits[3:10]
7
6
5
4
3
2
1
0
Organizationally Unique Identifier: Bits[11:18]
BIT
NAME
TYPE
RESET
DESCRIPTION
15:0
Organizationally
Unique Identifier
(bits 3:18)
Read/Write 001Ah
This identifier is assigned to PHY manufacturers by
the IEEE. Its intention is to provide sufficient informa-
tion to support 10/100 Management as defined in
Clause 30.1.2 of the IEEE 802.3 specification.
This register contains bits [3:18] of the OUI. Bit 3 of
the OUI is located in bit 15 of the PHY Identifier, bit 4
of the OUI is in bit 14, and so on.
Note: This field is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
36
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
PHY Identifier Register, Part 2 - Address 03h
15
14
13
12
11
10
9
8
Organizationally Unique Identifier - Bits[19:24]
Part Number
7
6
5
4
3
2
1
0
Part Number
Revision Number
BIT
NAME
TYPE
RESET
DESCRIPTION
15:10 Organizationally
Unique Identifier
(bits 19:24)
Read/Write 00 1000
This identifier is assigned to PHY manufacturers by
the IEEE. Its intention is to provide sufficient informa-
tion to support 10/100 Management as defined in
Clause 30.1.2 of the IEEE 802.3 specification.
This register contains bits [19:24] of the OUI. Bit 19 of
the OUI is located in bit 15 of this register, bit 20 of
the OUI is in bit 14, and so on.
Note: This field is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
9:4
Part Number
Read/Write 10 0000
These bits indicate the CS8952T part number. It has
been set to a value of 100000.
Note: This field is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
3:0
Revision Number
Read/Write Revision x
These bits indicate the CS8952T part revision.
Rev. A
0000
Rev. B
0001
etc.
Note: This field is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
DS206TPP2
37
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Auto-Negotiation Advertisement Register - Address 04h
15
14
13
12
11
10
9
8
Next Page
Acknowledge
Remote Fault
Technology Ability Field
7
6
5
4
3
2
1
0
Technology Ability Field
Protocol Selector Field
BIT
NAME
TYPE
RESET
DESCRIPTION
15
Next Page
Read/Write 0
When set, this bit enables the ability to exchange
Next-Pages with the link partner. This bit should be
cleared if it is not desired to engage in Next Page
exchange.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
14
Acknowledge
Read Only
0
When set, this bit indicates consistent reception of
the link partner's data.
13
Remote Fault
Read/Write 0
This bit may be used to indicate a fault condition to
the link partner. Setting this bit will signal to the link
partner that a fault condition has occurred.
12:5
Technology Ability
Field
Read/Write Reset value is
dependent on the
status of the
AN[1:0] pins (See
Table 5).
This field determines the advertised capabilities of
the CS8952T as shown below. When the bit is set,
the corresponding technology will be advertised dur-
ing auto-negotiation.
BIT
Capability
12
Reserved
11
Reserved
10
PAUSE operation for full duplex links.
9
100BASE-T4 (Note: this technology is not sup-
ported and can not be set.)
8
100BASE-TX Full Duplex
7
100BASE-TX Half Duplex
6
10BASE-T Full Duplex
5
10BASE-T Half Duplex
4:0
Protocol Selector
Field
Read/Write 0 0001
This field is used to identify the type of message
being sent by auto-negotiation. This field defaults to a
value of "00001" for IEEE 802.3 messages.
38
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Auto-Negotiation Link Partner Ability Register - Address 05h
15
14
13
12
11
10
9
8
Next Page
Acknowledge
Remote Fault
Technology Ability Field
7
6
5
4
3
2
1
0
Technology Ability Field
Protocol Selector Field
BIT
NAME
TYPE
RESET
DESCRIPTION
15
Next Page
Read Only
0
When set, this bit indicates that the link partner is
capable of participating in the Next Page exchange.
14
Acknowledge
Read Only
0
When set, this bit indicates that the link partner has
received consistent data from the CS8952T.
13
Remote Fault
Read Only
0
This bit indicates that a fault condition occurred on
the far end. When this bit is set and auto-negotiation
is enabled, the Remote Fault bit in the Basic Mode
Status Register (address 01h) will also be set.
12:5
Technology Ability
Field
Read Only
0000 0000
This field indicates the advertised capabilities of the
link partner as shown below. When the bit is set, the
corresponding technology has been advertised dur-
ing auto-negotiation.
BIT
Capability
12
Reserved
11
Reserved
10
PAUSE operation for full duplex links.
9
100BASE-T4
8
100BASE-TX Full Duplex
7
100BASE-TX Half Duplex
6
10BASE-T Full Duplex
5
10BASE-T Half Duplex
4:0
Protocol Selector
Field
Read Only
0 0000
This field is used to identify the type of message
being received during auto-negotiation.
DS206TPP2
39
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Auto-Negotiation Expansion Register - Address 06h
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
Parallel
Detection
Fault
Link Partner
Next Page
Able
Next Page
Able
Page
Received
Link Partner
Auto-Neg Able
BIT
NAME
TYPE
RESET
DESCRIPTION
15:5
Reserved
Read Only
000 0000 0000
4
Parallel Detection
Fault
Read Only
0
When set, this bit indicates an error condition in
which both the 10BASE-T and 100BASE-TX links
came up valid, or that one of the technologies estab-
lished a link but was unable to maintain the link. This
bit is self-clearing.
3
Link Partner Next
Page Able
Read Only
0
When set, this bit indicates that the link partner is
capable of Next Page exchange.
2
Next Page Able
Read Only
1
This bit is a status bit which indicates to the Manage-
ment Layer that the CS8952T supports Next Page
capability.
1
Page Received
Read Only
0
When set, this bit indicates that a valid word of auto-
negotiation data has been received and its integrity
verified. The first page of data will consist of the Base
Page, and all successive pages will consist of Next
Page data. This bit is self-clearing.
0
Link Partner Auto-
Neg Able
Read Only
0
When set, this bit indicates that the link partner has
auto-negotiation capability.
40
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Auto-Negotiation Next-Page Transmit Register - Address 07h
15
14
13
12
11
10
9
8
Next Page
Acknowledge
Message
Page
Acknowledge
2
Toggle
Message/Unformatted Code Field
7
6
5
4
3
2
1
0
Message/Unformatted Code Field
BIT
NAME
TYPE
RESET
DESCRIPTION
15
Next Page
Read/Write 0
When set, this bit indicates that more Next Pages fol-
low. When clear, the current page is the last page of
data to be sent.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
14
Acknowledge
Read Only
0
This bit is used for Link Code Word verification. When
set, it indicates that consistent data has been suc-
cessfully read from the link partner.
13
Message Page
Read/Write 1
When set, this bit indicates that the data in the Mes-
sage/Unformatted Code Field is one of the pre-
defined message pages. When low, the data is unfor-
matted data.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
12
Acknowledge 2
Read/Write 0
When set, this bit indicates to the link partner that the
CS8952T can comply with the last received mes-
sage.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
11
Toggle
Read Only
0
This bit is used to maintain synchronization with the
link partner during Next Page exchange.
10:0
Message/Unformat-
ted Code Field
Read/Write 000 0000 0001
This field contains the 11 bit data for the Message or
Unformatted Page. It defaults to the Null Message.
Note: This field is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
DS206TPP2
41
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Interrupt Mask Register - Address 10h
This register indicates which events will cause an interrupt event on the MII_IRQ pin. Each bit acts as an enable to the interrupt.
Thus, when set, the event will cause the MII_IRQ pin to be asserted. When clear, the event will not affect the MII_IRQ pin, but
the status will still be reported via the Interrupt Status Register (address 11h).
15
14
13
12
11
10
9
8
CIM Link
Unstable
Link Status
Change
Descrambler
Lock Change
Premature
End Error
DCR
Rollover
FCCR
Rollover
RECR
Rollover
Remote
Loopback
Fault
7
6
5
4
3
2
1
0
Reset
Complete
Jabber
Detect
Auto-Neg
Complete
Parallel
Detection
Fault
Parallel
Fail
Remote
Fault
Page
Received
Reserved
BIT
NAME
TYPE
RESET
DESCRIPTION
15
CIM Link Unstable
Read/Write 0
When set, an interrupt will be generated if an unsta-
ble link condition is detected by the Carrier Integrity
Monitor function.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
14
Link Status Change Read/Write 1
When set, an interrupt will be generated each time
the CS8952T detects a change in the link status.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
13
Descrambler Lock
Change
Read/Write 0
When set, an interrupt will be generated each time
the 100BASE-TX receive descrambler loses or
regains synchronization with the far-end.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
12
Premature End
Error
Read/Write 0
When set, an interrupt will be generated when two
consecutive IDLES are detected in a 100BASE-TX
frame without the End-of-Stream-Delimiter sequence.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
42
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Interrupt Mask Register - Address 10h (Cont.)
BIT
NAME
TYPE
RESET
DESCRIPTION
11
DCR Rollover
Read/Write 0
When set, an interrupt will be generated if the MSB in
the DCR counter becomes set.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
10
FCCR Rollover
Read/Write 0
When set, an interrupt will be generated if the MSB in
the FCCR counter becomes set.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
9
RECR Rollover
Read/Write 0
When set, an interrupt will be generated if the MSB in
the RECR counter becomes set.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
8
Remote Loopback
Fault
Read/Write 0
When set, an interrupt will be generated if the elastic
buffer in the PMA is under-run or over-run during
Remote Loopback. This should not occur for normal
length 802.3 frames.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
7
Reset Complete
Read/Write 1
When set, an interrupt will be generated once the dig-
ital and analog sections have been reset, and a cali-
bration cycle has been performed.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
6
Jabber Detect
Read/Write 0
When set, an interrupt will be generated when a Jab-
ber condition is detected by the 10BASE-T MAU.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
DS206TPP2
43
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Interrupt Mask Register - Address 10h (Cont.)
BIT
NAME
TYPE
RESET
DESCRIPTION
5
Auto-Neg Complete Read/Write 0
When set, an interrupt will be generated once auto-
negotiation has completed successfully.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
4
Parallel Detection
Fault
Read/Write 0
When set, an interrupt will be generated if auto-nego-
tiation determines that unstable legacy link signaling
was received.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
3
Parallel Fail
Read/Write 0
When set, an interrupt will be generated when paral-
lel detection has occurred for a technology that is not
currently advertised by the local device.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
2
Remote Fault
Read/Write 0
When set, an interrupt will be generated if a remote
fault condition is detected either by auto-negotiation
or by the Far-End Fault Detect state machine.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
1
Page Received
Read/Write 0
When set, an interrupt is generated each time a page
is received during auto-negotiation.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
0
Reserved
Read Only
0
44
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Interrupt Status Register - Address 11h
This register indicates which event(s) caused an interrupt event on the MII_IRQ pin. All bits are self-clearing, and will thus be
cleared upon readout.
15
14
13
12
11
10
9
8
CIM Link
Unstable
Link Status
Change
Descrambler
Lock Change
Premature
End Error
DCR
Rollover
FCCR
Rollover
RECR
Rollover
Remote
Loopback
Fault
7
6
5
4
3
2
1
0
Reset
Complete
Jabber
Detect
Auto-Neg
Complete
Parallel
Detection
Fault
Parallel
Fail
Remote
Fault
Page
Received
Reserved
BIT
NAME
TYPE
RESET
DESCRIPTION
15
CIM Link Unstable
Read Only
0
When set, this bit indicates that an unstable link con-
dition was detected by the Carrier Integrity Monitor
function.
14
Link Status Change Read Only
0
When set, this bit indicates that a change has
occurred to the status of the link. The Self Status
Register (address 19h) may be read to determine the
current status of the link.
13
Descrambler Lock
Change
Read Only
0
When set, this bit indicates that a change has
occurred in the status of the descrambler. The Self
Status Register (address 19h) may be read to deter-
mine the current status of the scrambler lock.
12
Premature End
Error
Read Only
0
This bit is set when a premature end of frame is
detected for 100 Mb/s operation. A premature end is
defined as two consecutive IDLE patterns detected in
a frame prior to the End of Stream Delimiter.
11
DCR Rollover
Read Only
0
This bit is set when the MSB of the Disconnect Count
Register (address 12h) becomes set. This should
provide ample warning to the management layer so
that the DCR may be read before rolling over.
10
FCCR Rollover
Read Only
0
This bit is set when the MSB of the False Carrier
Count Register (address 13h) becomes set. This
should provide ample warning to the management
layer so that the FCCR may be read before saturat-
ing.
9
RECR Rollover
Read Only
0
This bit is set when the MSB of the Receive Error
Count Register (address 15h) becomes set. This
should provide ample warning to the management
layer so that the RECR may be read before rolling
over.
DS206TPP2
45
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Interrupt Status Register - Address 11h (Cont.)
BIT
NAME
TYPE
RESET
DESCRIPTION
8
Remote Loopback
Fault
Read Only
0
When set, this bit indicates that the Elastic Buffer has
detected an over-run or an under-run condition. In
any case, the frame generating this fault will be termi-
nated.
This should never happen since the depth of the elas-
tic buffer (10 bits) is greater than twice the maximum
number of bit times the receive and transmit clocks
may slip during a maximum length packet assuming
clock frequency tolerances of 100 ppm or less.
7
Reset Complete
Read Only
0
When set, this bit indicates that the internal analog
calibration cycle has completed, and all analog and
digital circuitry is ready for normal operation.
6
Jabber Detect
Read Only
0
In 10BASE-T mode, if the last transmission is longer
than 105 ms, then the packet output is terminated by
the jabber logic and this bit is set.
This bit is implemented with a latching function so
that the occurrence of a jabber condition causes it to
become set until it is cleared by a read to this register,
a read to the Basic Mode Status Register (address
01h), or a reset.
No jabber detect function has been defined for
100BASE-TX.
This bit is the same as in the Basic Mode Status Reg-
ister (address 01h).
5
Auto-Neg Complete Read Only
0
This bit is set when the auto-negotiation process has
completed. This is an indication that the Auto-Negoti-
ation Advertisement Register (address 04h), the
Auto-Negotiation Link Partner Ability Register
(address 05h), and the Auto-Negotiation Expansion
Register (address 06h) are valid.
This bit is the same as in the Basic Mode Status Reg-
ister (address 01h).
4
Parallel Detection
Fault
Read Only
0
When set, this bit indicates an error condition in
which auto-negotiation has detected that unstable
10BASE-T or 100BASE-TX link signalling was
received. This bit is self-clearing.
This bit is the same as in the Auto-Negotiation
Expansion Register (address 06h)
3
Parallel Fail
Read Only
0
When set, this bit indicates that a parallel detection
has occurred for a technology that is not currently
advertised by the local device.
46
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Interrupt Status Register - Address 11h (Cont.)
BIT
NAME
TYPE
RESET
DESCRIPTION
2
Remote Fault
Read Only
0
When auto-negotiation is enabled, this bit is set if the
Remote Fault bit is set in the Auto-Negotiation Link
Partner Ability Register (address 05h). When auto-
negotiation is disabled, this bit will be set when the
Far-End Fault Indication for 100BASE-TX is detected.
1
Page Received
Read Only
0
When set, this bit indicates that a valid word of auto-
negotiation data has been received and its integrity
verified. The first page of data will consist of the Base
Page, and all successive pages will consist of Next
Page data. This bit is self-clearing.
This bit is the same as in the Auto-Negotiation
Expansion Register (address 06h).
0
Reserved
Read Only
0
DS206TPP2
47
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Disconnect Count Register - Address 12h
15
14
13
12
11
10
9
8
Disconnect Counter
7
6
5
4
3
2
1
0
Disconnect Counter
BIT
NAME
TYPE
RESET
DESCRIPTION
15:0
Disconnect Counter Read/Write 0000h
This field contains a count of the number of times the
CS8952T has lost a Link OK condition. This counter
is cleared upon readout and will roll-over to 0000h.
48
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
False Carrier Count Register - Address 13h
15
14
13
12
11
10
9
8
False Carrier Counter
7
6
5
4
3
2
1
0
False Carrier Counter
BIT
NAME
TYPE
RESET
DESCRIPTION
15:0
False Carrier
Counter
Read Only
0000h
This field contains a count of the number of times the
CS8952T has detected a false-carrier -- that is, the
reception of a poorly formed Start-of-Stream Delimiter
(SSD). The counter is incremented at the end of such
events to prevent multiple increments. This counter is
cleared upon readout and will saturate at FFFFh.
DS206TPP2
49
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Scrambler Key Initialization Register - Address 14h
15
14
13
12
11
10
9
8
Load
Reserved
Scrambler Initialization Key
7
6
5
4
3
2
1
0
Scrambler Initialization Key
BIT
NAME
TYPE
RESET
DESCRIPTION
15
Load
Read/Set
0
When this bit is set, the scrambler will be loaded with
the value in the Scrambler Initialization Key field.
When the load is complete, this bit will clear automat-
ically.
14:11 Reserved
Read Only
0000
These bits should be read as don't cares and, when
written, should be written to 0.
10:0
Scrambler Initializa-
tion Key
Read/Write Reset value is
dependent on the
PHY Address field
of the Self Status
Register (address
19h).
This field allows the Scrambler to be loaded with a
user-definable key sequence. A value of 000h has
the effect of bypassing the scrambler function.
This is valuable for testing purposes to allow a deter-
ministic response to test stimulus without a synchro-
nization delay.
Note: This field is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
50
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Receive Error Count Register - Address 15h
15
14
13
12
11
10
9
8
Receive Error Counter
7
6
5
4
3
2
1
0
Receive Error Counter
BIT
NAME
TYPE
RESET
DESCRIPTION
15:0
Receive Error
Counter
Read Only
0000h
This counter increments for each packet in which one
or more receive errors is detected that is not due to a
collision event. This counter is cleared upon readout
and will roll-over to 0000h.
DS206TPP2
51
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Descrambler Key Initialization Register - Address 16h
15
14
13
12
11
10
9
8
Load
Reserved
Descrambler Initialization Key
7
6
5
4
3
2
1
0
Descrambler Initialization Key
BIT
NAME
TYPE
RESET
DESCRIPTION
15
Load
Read/Set
0
When this bit is set, the descrambler will be loaded
with the value in the Descrambler Initialization Key
field. When the load is complete, this bit will clear
automatically.
14:11 Reserved
Read Only
0000
These bits should be read as don't cares and, when
written, should be written to 0.
10:0
Descrambler Initial-
ization Key
Read/Write Reset value is
dependent on the
PHY Address field
of the Self Status
Register (address
19h).
This register allows the Descrambler to be loaded
with a user-definable key sequence. A value of 000h
has the effect of bypassing the descrambler function.
This is valuable for testing purposes to allow a deter-
ministic response to test stimulus without a synchro-
nization delay.
Note: This field is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
52
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
PCS Sub-Layer Configuration Register - Address 17h
15
14
13
12
11
10
9
8
Reserved
Time-Out
Select
Time-Out
Disable
Repeater
Mode
LED5 Mode
Unlock Regs
MR Preamble
Enable
Fast Test
7
6
5
4
3
2
1
0
CLK25 Dis-
able
Enable LT/100
CIM Disable
Tx Disable
Rx Disable
LED1 Mode
LED4 Mode
Digital Reset
BIT
NAME
TYPE
RESET
DESCRIPTION
15
Reserved
Read/Write 1
This bit is reserved and should be cleared to 0.
14
Time-Out Select
Read/Write 0
When this bit is set, the time-out counter in the
receive descrambler is set to time-out after 2 ms with-
out IDLES. When clear the counter is set to time-out
after 722 ms without IDLES.
13
Time-Out Disable
Read/Write 0
When this bit is set, the time-out counter in the
receive descrambler is disabled. When this bit is
clear, the time-out counter is enabled.
12
Repeater Mode
Read/Write Reset to the value
on the REPEATER
pin.
This bit defines the mode of the Carrier Sense (CRS)
signal. When this bit is set, CRS is asserted due to
receive activity only. When this bit is clear, CRS is
asserted due to either transmit or receive activity.
11
LED5 Mode
Read/Write 0
This bit defines the mode of Pin LED5. When this bit
is set, pin LED5 indicates the synchronization status
of the 100BASE-TX descrambler. When this bit is
clear, LED5 indicates a collision.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
10
Unlock Regs
Read/Write 0
When set, this bit unlocks certain read only control
registers for factory testing. Leave clear for proper
operation.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
DS206TPP2
53
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
PCS Sub-Layer Configuration Register - Address 17h (Cont.)
BIT
NAME
TYPE
RESET
DESCRIPTION
9
MF Preamble
Enable
Read/Write 0
When set, this bit will force all management frames
(via MDIO, MDC) to be preceded by a 32 bit pream-
ble pattern of contiguous ones to be considered valid.
When cleared, it allows management frames with or
without the preamble pattern. The status of this regis-
ter is (inversely) reflected in the MF Preamble bit in
the Basic Mode Status Register (address 01h).
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
8
Fast Test
Read/Write 0
When set, internal timers are sped up significantly in
order to facilitate production test. Leave clear for
proper operation.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
7
CLK25 Disable
Read/Write When TCM pin is
low, reset to 1; oth-
erwise, reset to 0
Setting this bit will disable (tri-state) the CLK25 output
pin, reducing digital noise and power consumption.
6
Enable LT/100
Read/Write 1
When set, normal link status checking is enabled.
When clear, this bit forces the link status to Link OK
(at 100 Mb/s), and will assert the LINK_OK LED.
5
CIM Disable
Read/Write Reset to the logic
inverse of the
value on the
REPEATER pin.
When set, this bit forces the Carrier Integrity Monitor
function to be disabled. When low, the Carrier Integ-
rity Monitor function is enabled, and detection of an
unstable link will disable the receive and transmit
functions.
4
Tx Disable
Read/Write 0
When set, this bit forces the 10 Mb/s and 100 Mb/s
outputs to be inactive. When clear, normal transmis-
sion is enabled.
If Tx Disable is set while a packet is being transmit-
ted, transmission is completed and no subsequent
packets are transmitted until Tx Disable is cleared
again. Also, if Tx Disable is cleared while TX_EN is
high, the transmitter will remain disabled until TX_EN
is deasserted. This prevents fragments from being
transmitted onto the network.
54
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
PCS Sub-Layer Configuration Register - Address 17h (Cont.)
BIT
NAME
TYPE
RESET
DESCRIPTION
3
Rx Disable
Read/Write 0
When set, the receiver is disabled and no incoming
packets pass through the receiver. The link will
remain established and, if operating at 100 Mb/s, the
descrambler will remain locked. When clear, the
receiver is enabled.
If Rx Disable is set while a packet is being received,
reception is completed and no subsequent receive
packets are allowed until Rx Disable is cleared again.
Also, if Rx Disable is cleared while a packet is being
received, the receiver will remain disabled until the
end of the incoming packet. This prevents fragments
from being sent to the MAC.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
2
LED1 Mode
Read/Write 0
This bit defines the mode of Pin LED1. When this bit
is set, pin LED1 indicates Carrier Integrity Monitor
status as determined by the CIM Status bit in the Self
Status Register (address 19h). When this bit is clear,
LED1 indicates 10 Mb/s or 100 Mb/s transmission
activity.
1
LED4 Mode
Read/Write 0
This bit defines the mode of Pin LED4. When this bit
is set, pin LED4 indicates full duplex mode for
10 Mb/s or 100 Mb/s. When this bit is clear, LED4
indicates Polarity in 10 Mb/s mode or full-duplex in
100 Mb/s mode.
0
Digital Reset
Read/Write 0
When set, this bit will reset all digital logic and regis-
ters to their initial values. The analog circuitry will not
be affected.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
DS206TPP2
55
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Loopback, Bypass, and Receiver Error Mask Register - Address 18h
15
14
13
12
11
10
9
8
Bad SSD
Enable
Bypass 4B5B
Reserved
Bypass
Symbol
Alignment
ENDEC
Loopback
Reserved
Remote
Loopback
Reserved
7
6
5
4
3
2
1
0
Strip Preamble
Alternate FDX
CRS
Loopback
Transmit
Disable
Code Error
Report Select
Premature
End Error
Report Select
Link Error
Report Enable
Packet Error
Report Enable
Code Error
Report Enable
BIT
NAME
TYPE
RESET
DESCRIPTION
15
Bad SSD Enable
Read/Write 1
When set, this bit enables the reporting of a bad SSD
(False-Carrier event) on the MII. These events will be
reported by setting RX_ER=1, RX_DV=0, and
RXD[3:0]=1110.
If the 4B5B encoders are being bypassed, this event
will be reported by setting RX_DV=0 and
RXD[4:0]=11110. If symbol alignment is bypassed,
the CS8952T does not detect carrier, and thus will not
report bad SSD events.
14
Bypass 4B5B
Read/Write Reset to the value
on the BP4B5B
pin.
When set, this bit causes the receive 5B4B decoder
and the transmit 4B5B encoder to be bypassed.
13
Reserved
Read/Write Reset to 0.
Reserved bit, should remain at zero.
12
Bypass Symbol
Alignment
Read/Write Reset to the value
on the BPALIGN
pin.
When set, this bit causes the following functions to be
bypassed: receiver descrambling, symbol alignment
and decoding, transmit symbol encoding, and trans-
mit scrambling.
11
ENDEC Loopback
Read/Write 0
When set, the 10BASE-T internal Manchester
encoder output is connected to the decoder input.
When clear, the CS8952T is configured for normal
operation.
10
Reserved
Read/Write 0
This bit is reserved.
9
Remote Loopback
Read/Write 0
When set, data received from the link is looped back
at the MII and sent back out to the link. Received data
will be presented on the MII pins. Transmit data at the
MII will be ignored.
Note: Setting Remote Loopback and PMD Loopback
simultaneously will cause neither loopback mode to
be entered, and should not be done.
56
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Loopback, Bypass, and Receiver Error Mask Register - Address 18h (Cont.)
BIT
NAME
TYPE
RESET
DESCRIPTION
8
Reserved
Read/Write 0
This bit is reserved.
7
Strip Preamble
Read/Write 0
When set this bit causes the 7 bytes of MAC pream-
ble to be stripped off of incoming 100 Mb/s frames.
The data received across the MII will begin with the 1
byte Start of Frame Delimiter (SFD).
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
6
Alternate FDX CRS Read/Write 0
This bit changes the behavior of the CRS pin only in
the full-duplex (FDX) mode of operation. When set,
CRS will be asserted for transmit data only. When
clear, CRS will be asserted only for receive data.
5
Loopback Transmit
Disable
Read/Write 1
This bit controls whether loopback data is transmitted
onto the network. When set, any data transmitted
during PMD or ENDEC loopback mode will NOT be
transmitted onto the network. When clear, data will be
transmitted on the TX+/- pins as well as looped back
onto the MII pins.
4
Code Error Report
Select
Read/Write 0
When set, this bit causes code errors to be reported
by a value of 5h on RXD[3:0] and the assertion of
RX_ER.
When clear, this bit causes code errors to be reported
by a value of 6h on RXD[3:0] and the assertion of
RX_ER.
This bit is superseded by the Code Error Report
Enable bit.
DS206TPP2
57
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Loopback, Bypass, and Receiver Error Mask Register - Address 18h (Cont.)
BIT
NAME
TYPE
RESET
DESCRIPTION
3
Premature End
Error Report Select
Read/Write 0
When set, this bit causes premature end errors to be
reported by a value of 4h on RXD[3:0] and the asser-
tion of RX_ER.
When clear, this bit causes premature end errors to
be reported by a value of 6h on RXD[3:0] and the
assertion of RX_ER.
A premature end error is caused by the detection of
two IDLE symbols in the 100 Mb/s receive data
stream prior to the End of Stream Delimiter.
2
Link Error Report
Enable
Read/Write 0
When set, this bit causes link errors to be reported by
a value of 3h on RXD[3:0] and the assertion of
RX_ER. When clear, link errors are not reported
across the MII.
1
Packet Error Report
Enable
Read/Write 0
When set, this bit causes packet errors to be reported
by a value of 2h on RXD[3:0] and the assertion of
RX_ER. When clear, packet errors are not reported
across the MII.
0
Code Error Report
Enable
Read/Write 0
When set, code errors are reported and transmitted
on RXD[3:0].
When clear, this bit enables the Code Error Report
values on RXD[3:0] as selected by the Code Error
Report Select bit and also causes the assertion of
TX_ER to transmit a HALT code group.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
58
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Self Status Register - Address 19h
15
14
13
12
11
10
9
8
Link OK
Power
Down
Receiving
Data
Descrambler
Lock
Disable CRS
on Time-out
Auto-Neg
Enable Status
PAUSE
FEFI Enable
7
6
5
4
3
2
1
0
Full Duplex
10BASE-T
Mode
CIM Status
PHY Address
BIT
NAME
TYPE
RESET
DESCRIPTION
15
Link OK
Read Only
0
When set, this bit indicates that a valid link connec-
tion has been detected. The type of link established
may be determined from bits 6, 7, and 9. When clear,
this bit indicates that a valid link connection does not
exist. This bit may be used to determine the current
status of the link.
14
Power Down
Read Only
0
When high, this bit indicates that the CS8952T is in a
low power state.
13
Receiving Data
Read Only
0
This bit is high whenever the CS8952T is receiving
valid data. It is a direct copy of the state of the
RX_DV pin accessible by software.
12
Descrambler Lock
Read Only
0
When high, this bit indicates that the descrambler has
successfully locked to the scrambler seed of the far-
end transmitter and is able to descramble received
data.
11
Disable CRS on
Time-out
Read/Write Reset to the logic
inverse of the
value on the
REPEATER pin.
This bit controls the state of the CRS pin upon a
descrambler time-out. When set, CRS will be forced
low upon a descrambler time-out, and will not be
released until the descrambler has re-acquired syn-
chronization.
10
Auto-Neg Enable
Status
Read Only
If auto-negotiation
is enabled via the
AN[1:0] pins, reset
to 1; otherwise,
reset to 0.
This bit reflects the value of bit 12 in the Basic Mode
Control Register (address 00h). When set, it indicates
that auto-negotiation has been enabled. When clear,
this bit indicates that the mode of the CS8952T has
been forced to that indicated by bits 6, and 7.
9
PAUSE
Read Only
0
When set, this bit indicates that the Flow-Control
PAUSE function has been negotiated. This indicates
that both the local device and the link partner have
advertised this capability.
8
FEFI Enable
Read/Write 0
This bit controls the Far-End Fault Generate and
Detect state machines. When this bit is set and auto-
negotiation is disabled (bit 10 is clear), both state
machines are enabled. When clear, this bit disables
both state machines.
7
Full Duplex
Read Only
If a full duplex
mode is enabled
via the AN[1:0]
pins, reset to 1;
otherwise, reset to
0.
When set, this bit indicates that the CS8952T has
been configured for Full-Duplex operation.
6
10BASE-T Mode
Read Only
0
When set, this bit indicates that the CS8952T has
been configured for 10 Mb/s operation.
DS206TPP2
59
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Self Status Register - Address 19h (Cont.)
BIT
NAME
TYPE
RESET
DESCRIPTION
5
CIM Status
Read Only
0
When clear, this bit indicates that a stable link con-
nection has been detected. When an unstable link is
detected and the Carrier Integrity Monitor Disable bit
in the PCS Sub-Layer Configuration Register
(address 17h) is clear, this bit is set and latched. It will
remain set until this register is read.
4:0
PHY Address Field Read/Write Reset to the val-
ues on the
PHYAD[4:0] pins.
The value on pins PHYAD[4:0] are latched into this
field at power-up or reset. These bits define the PHY
address used by the management layer to address
the PHY. The external logic must know this address
in order to select this particular CS8952T's registers
individually via the MDIO and MDC pins.
60
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
10BASE-T Status Register - Address 1Bh
15
14
13
12
11
10
9
8
Reserved
Polarity OK
10BASE-T
Serial
Reserved
7
6
5
4
3
2
1
0
Reserved
BIT
NAME
TYPE
RESET
DESCRIPTION
15:11 Reserved
Read Only
0 0000
10
Polarity OK
Read Only
0
When high, the polarity of the receive signal (at the
RXD+/RXD- inputs) is correct. If clear, the polarity is
reversed. If the Polarity Disable bit of 10BASE-T Con-
figuration Register (address 1Ch) is clear, then the
polarity is automatically corrected, if needed. The
Polarity OK status bit shows the true state of the
incoming polarity independent of the Polarity Disable
bit.
9
10BASE-T Serial
Read/Write Reset to the value
on the 10BT_SER
pin.
When set, this bit selects 10BASE-T serial mode.
When low, this bit selects 10BASE-T nibble mode.
This bit will only affect the CS8952T if it has been
configured for 10 Mb/s operation.
8:0
Reserved
Read Only
0 0000 0000
DS206TPP2
61
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
10BASE-T Configuration Register - Address 1Ch
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
National
Compatibility
Mode
LED3 Blink
Enable
Enable LT/10
SQE Enable
Reserved
Low Rx
Squelch
Polarity
Disable
Jabber Enable
BIT
NAME
TYPE
RESET
DESCRIPTION
15:8
Reserved
Read Only
0000 0000
7
National Compatibil-
ity Mode
Read/Write 1
When set, registers and bits that are not compatible
with the National DP83840 are disabled and writes to
these registers are ignored.
6
LED3 Blink Enable
Read/Write 0
When set, LED3 will blink during auto-negotiation and
will indicate Link Good status upon completion of
auto-negotiation. When clear, LED3 indicates Link
Good status only.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit (bit
7) is set.
5
Enable LT/10
Read/Write 1
When set, this bit enables the transmission of link
pulses.
When clear, link pulses are disabled and a good link
condition is forced. If link pulses are disabled during
100 Mb/s operation with auto-negotiation enabled,
the CS8952T will go into 10 Mb/s mode. If operating
in 100 Mb/s mode with no auto-negotiation, then
clearing this bit has no effect.
4
SQE Enable
Read/Write Reset to the logic
inverse of the
value on the
REPEATER pin.
When set, and if the CS8952T is in half-duplex mode,
this bit enables the 10BASE-T SQE function. When
the part is in repeater mode, this bit is cleared and
may not be set.
3
Reserved
Read Only
1
This bit should be read as a don't care and, when
written, should be written to 1.
2
Low Rx Squelch
Read/Write 0
When clear, the 10BASE-T receiver squelch thresh-
olds are set to levels defined by the ISO/IEC 8802-3
specification. When set, the thresholds are reduced
by approximately 6 dB. This is useful for operating
with "quiet" cables that are longer than 100 meters.
1
Polarity Disable
Read/Write 0
The 10BASE-T receiver automatically determines the
polarity of the received signal at the RXD+/RXD-
input. When this bit is clear, the polarity is corrected, if
necessary. When set, no effort is made to correct the
polarity. Polarity correction will only be performed dur-
ing 10BASE-T packet reception.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit (bit
7) is set.
62
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
10BASE-T Configuration Register - Address 1Ch (Cont.)
BIT
NAME
TYPE
RESET
DESCRIPTION
0
Jabber Enable
Read/Write 1
When set, the jabber function is enabled. When clear,
and if the CS8952T is in 10BASE-T full-duplex or
10BASE-T ENDEC loopback mode, the jabber func-
tion is disabled.
Note: When the National Compatibility Mode bit (bit
7) is set, the Jabber function may also be disabled for
10BASE-T half-duplex, although this is not recom-
mended.
DS206TPP2
63
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
DESIGN CONSIDERATIONS
The CS8952T is a mixed-signal device containing
the high-speed digital and analog circuits required
to implement Fast Ethernet communication. It is
important the designer adhere to the following
guidelines and recommendations for proper and re-
liable operation of the CS8952T. These guidelines
will also benefit the design with good EMC perfor-
mance.
Twisted Pair Interface
The recommended connection of the twisted-pair
interface is shown if Figure 6. The unused cable
pairs are terminated to increase the common-mode
performance. Common-mode performance is also
improved by connecting the center taps of the RX
and TX input circuits to the DC-isolated ground
plane. The 0.01 F capacitor C1 must provide 2KV
(1,500 Vrms for 60 seconds) of isolation to meet
802.3 requirements. If a shielded RJ45 connector is
used (recommended), the shield should be connect-
ed to chassis ground.
.
Internal Voltage Reference
A 4.99 k
1% biasing resistor must be connected
between the CS8952T RES pin and ground. This
resistor biases the internal analog circuits of the
CS8952T and should be placed as close as possible
to RES pin. Connect the other end of this resistor
directly to the ground plane. Connect the adjacent
CS8952T ground pins (pins 85 and 87) to the
grounded end of the resistor forming a "shield"
around the RES connection.
Clocking Schemes
The CS8952T may be clocked using one of three
possible schemes: using a 25 MHz crystal and the
49.9
0.1F
CS8952
TX+
TX-
RX+
RX-
80
81
91
92
T1
1
2
3
4
5
6
7
8
RJ-45
SHLD
SHLD
16
15
2
1
14
3
10
11
6
7
12
TG22-3506
5
1%
49.9
1%
0.1F
75
75
0.01F
2KV
51
51
51
51
51
51
Figure 6. Recommended Connection of Twisted-Pair Ports (Network Interface Card)
4.99K
VSS
RES
VSS
CS8952
Via to
Ground
Plane
87
86
85
1%
Figure 7. Biasing Resistor Connection and Layout
64
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
internal oscillator, using an external oscillator sup-
plied through the XTAL_I pin, or using an external
clock source supplied through the TX_CLK pin.
When a 25 MHz crystal is used, it should be placed
within one inch of the XTAL_I and XTAL_O pins
of the CS8952T. The crystal traces should be short,
have no vias, and run on the component side.
Table 10 lists examples of manufacturers of suit-
able crystals. The designer should evaluate their
crystal selection for suitability in their specific de-
sign.
Alternately, an external CMOS clock source may
be connected to the XTAL_I pin, with XTAL_O
left open. The input capacitance of the XTAL_I pin
is larger than the other inputs (a maximum of
35pF), since it includes the additional load capaci-
tance of the crystal oscillator. Care should be taken
to assure any external clock source attached to
XTAL_I is capable of driving higher capacitive
loads. The clock signal should be 25 MHz 0.01%
with a duty cycle between 45% and 55%.
The third alternative is to supply a TTL-level clock
to both a MAC and the CS8952T's TX_CLK pin.
In this case the XTAL_I pin should be left uncon-
nected, and the TCM pin should be left unconnect-
ed or pulled high. The clock skew between the
TX_CLK input and the TXD[4:0] pins is tightly
controlled, assuring data is latched correctly.
Recommended Magnetics
The CS8952T requires an isolation transformer
with a 1:1 turns ratio for both the transmit and re-
ceive signals. Table 10 lists examples of manufac-
turers
with
transformers
meeting
these
requirements. However, the designer should evalu-
ate the magnetics for suitability in their specific de-
sign.
Power Supply and Decoupling
The CS8952T supports connection to either a 3.3 V
or 5.0 V MII. When connected to a +5.0 V MII, all
power pins should be provided +5.0 V +/- 5%, and
all digital signal inputs should be referenced to
+5.0V. When interfaced with a 3.3 V MII,
VDD_MII power pins should be provided +3.3 V
+/- 5%, VDD power pins should be provided
+5.0 V +/- 5%, and all signal inputs, with the ex-
ception of XTAL_I, should be referenced to
+3.3 V.
Table 10. Support Component Manufacturers
Each CS8952T power pin should be connected to a
0.1 F bypass capacitor and then to the power
plane. The bypass capacitors should be located as
close to its corresponding power pin as possible.
Connect ground pins directly to the ground plane.
General Layout Recommendations
The following PCB layout recommendations will
help ensure reliable operation of the CS8952T and
good EMC performance.
Use a multilayer Printed Circuit Board with at
least one ground and one power plane. A typi-
cal +5V MII application would be as follows:
Layer 1: (top) Components and first choice sig-
nal routing
Layer 2: Ground
Layer 3: Power (+5V)
Component
Manufacturer
Part Number
Crystal
Raltron Electronics Corp.
10651 NW 19th St.
Miami, FL 33172
(305) 593-6033
www.raltron.com
AS-25.000-15-F-
EXT-SMD-TR-
CIR
Transformer
Halo Electronics, Inc.
P.O. Box 5826
Redwood City, CA 94063
USA
(650) 568-5800
www.haloelectronics.com
TG22-3506ND
Bel Fuse, Inc.
198 Van Vorst Street
Jersey City, NJ 07302 USA
(201) 432-0463
www.belfuse.com
S5558-5999-46
Pulse Engineering
12220 World Trade Drive
San Diego, CA 92128 USA
(619) 674-8100
www.pulseeng.com
PE-68515
DS206TPP2
65
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Layer 4: (bottom) Second choice signal rout-
ing, bypass components
Place transformer T1 as close to the RJ45 connec-
tor as possible with the secondary (network) side
facing the RJ45 and the primary (chip) side facing
the analog side (pins 76-100) of CS8952T. Place
the CS8952T in turn as close to T1 as possible.
Use the bottom layer for signal routing as a sec-
ond choice. You may place all components on
the top layer. However, bypass capacitors are
optimally placed as close to the chip as possible
and may be best located underneath the
CS8952T on the bottom layer. Termination
components at the RJ-45 and fiber transceiver
may also be optimally placed on the bottom
layer.
Connect a 0.1
F bypass capacitor to each
CS8952T VDD and VDD_MII pin. Place it as
close to its corresponding power pin as possible
and connect the other lead directly to the
ground plane.
The 4.99K reference resistor should be placed
as close to the RES pin as possible. Connect the
other end of this resistor to the ground plane us-
ing a via. Connect the adjacent VSS pins (pins
85 and 87) to the grounded end of the resistor
forming a shield as illustrated in Figure 7.
Controlled impedance is necessary for critical
signals TX+/- and RX+/-. These should be run
as microstrip transmission lines (100
differ-
ential, 50
single-ended). The MII signals
should be 68
microstrip transmission lines.
(For short MII signal paths one may standard-
ize on a given trace width for all traces without
significant degradation in signal integrity.)
Avoid routing traces other than the TX and RX
signals under transformer T1 and the RJ45 con-
nector. Signals may run on the bottom side un-
derneath the CS8952T as long as they stay
away from critical analog traces.
Connect all CS8952T ground and power pins
directly to the ground and power planes, re-
spectively. Note: The VDD_MII power pins
may need their own power plane or plane seg-
ment in +3.3 V MII applications.
Depending on the orientation and location of
the transformer, the CS8952T, and the RJ-45,
and on whether the application is for a NIC or a
switch, the RX and TX pairs may need to cross.
This should be done by changing layers on a
pair by pair basis only, using the minimum
number of vias, and making sure that each trace
within a pair "sees" the same path as its peer.
Figure 6 shows the CS8952T in a NIC or adapt-
er configuration. It may be configured for a hub
or repeater application by changing the wiring
to the RJ-45 as shown in Table 11.
Differential pair transmission lines should be
routed close together (one trace width spacing
edge-to-edge) and kept at least two trace widths
away from other traces, components, etc. TX
and RX pairs should be routed away from each
other and may use opposite sides of the PCB as
necessary, Each member of the differential pair
should "see" the same PCB terrain as its peer.
Unused spaces on the signal layers should be
filled with ground fill (pour). Vias should con-
nect the ground patches to the ground plane.
This is especially recommended (symmetrical-
66
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
ly) on both sides of the TX+/- traces.
Table 11. RJ-45 Wiring
No signal current carrying planes, i.e. no
ground or power plane, should be present un-
derneath the region between the transformer
secondary (network) side and the RJ-45. How-
ever, a chassis plane may be added in this re-
gion to pick up the metal tabs of a shielded RJ-
45. This chassis plane should be separated from
the ground and power planes by at least
50 mils. That is, all other ground and power
planes should be "cookie cuttered" so they are
voided in the area of the chassis plane. Gener-
ally speaking, parts should not cross the moat
except for the transformer.
Proper termination practices must be used with
all transmission lines, especially if sending/re-
ceiving high speed signals. Series terminations
must be kept close to the source and load termi-
nations close to the load.
Locate the crystal as close to the CS8952T as
possible, running short traces on the compo-
nent side in order to reduce parasitic load ca-
pacitance.
Add bulk capacitance at each connector where
power may be supplied. For example, MII pow-
er may be provided at the MII connector and at
a separate connector for test purposes. If so,
and the two connectors are not adjacent, then
the bulk capacitors should be duplicated in each
locations.
Use wide traces to connect the unused pairs ter-
mination resistors at T1 and the RJ-45 to the
2 KV capacitor or capacitors in order to mini-
mize their lead inductance.
CS8952T Pin
Assignment
T1 Primary Pin
Assignment
T1 Secondary
Pin Assignment
RJ-45 Pin Assignment
Adapter/NIC
Configuration
Hub/Repeater
Configuration
91 (RX+)
1 (RX+)
7 (RX+)
3 (RD+)
1 (RD+)
92 (RX-)
2 (RX-)
6 (RX-)
6 (RD-)
2 (RD-)
81 (TX-)
16 (TX-)
10 (TX-)
2 (TD-)
6 (TD-)
80 (TX+)
15 (TX+)
11 (TX+)
1 (TD+)
3 (TD+)
DS206TPP2
67
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
SPECIFICATIONS AND CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS = 0 V, all voltages with respect to 0 V.)
WARNING:
Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS = 0 V, all voltages with respect to 0 V.)
QUARTZ CRYSTAL REQUIREMENTS
(If a 25 MHz quartz crystal is used, it must meet the following specifications.)
Parameter
Symbol
Min
Max
Unit
Power Supply
Core
MII
V
DD
V
DD_MII
-0.3
-0.3
6.0
6.0
V
Input Current
Except Supply Pins
-
+/-10.0
mA
Input Voltage
-0.3
V
DD_MII
+
0.3
V
Output Voltage
-0.3
V
DD_MII
+
0.3
V
Ambient Temperature
Power Applied
-55
+125
C
Storage Temperature
-65
+150
C
Parameter
Symbol
Min
Max
Unit
Power Supply
Core
MII
V
DD
V
DD_MII
4.75
3.0
5.25
5.25
V
V
Operating Ambient Temperature
T
A
0
70
C
Parameter
Min
Typ
Max
Unit
Parallel Resonant Frequency
-
25.0
-
MHz
Resonant Frequency Error (CL = 15 pF)
-50
-
+50
ppm
Resonant Frequency Change Over Operating Temperature
-40
-
+40
ppm
Crystal Load Capacitance
-
15
-
pF
Motional Crystal Capacitance
-
0.021
-
pF
Series Resistance
-
-
18
Shunt Capacitance
-
-
7
pF
68
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
DC CHARACTERISTICS
(Over recommended operating conditions)
Parameter
Symbol
Min
Typ
Max
Unit
Power Supply
Power Supply Current
100BASE-TX (Note 1)
10BASE-T (Note 1)
1.
With digital outputs connected to CMOS loads.
I
DD
-
-
135
80
145
-
mA
Hardware Power-Down
(Note 1)
I
DDHPDN
-
900
-
A
Software Power-Down
(Note 1)
I
DDSPDN
-
20
-
mA
Low Power Power-Up
(Note 1)
I
DDSLPUP
-
900
-
A
Oscillator
XTAL_I Input Low Voltage
V
IXH
-0.3
-
0.2
V
XTAL_I Input High Voltage
V
IXH
3.0
-
V
DD
+ 0.3
V
XTAL_I Input Low Current
I
IXL
-40
-
-
A
XTAL_I Input High Current
I
IXH
-
-
40
A
XTAL_I Input Capacitance
C
L
35
-
pF
XTAL_I Input Cycle Time
t
IXC
39.996
-
40.004
ns
XTAL_I Input Low Time
t
IXL
18
-
22
ns
XTAL_I Input High Time
t
XH
18
-
22
ns
Digital I/O
Output Low Voltage
CLK25, MII_IRQ, SPD10, SPD100
I
OL
= 4.0mA
LED[4:0]
I
OL
= 10.0mA
V
OL
-
-
-
-
0.4
0.4
V
Output Low Voltage (MII_DRV = 1)
COL, CRS, MDIO, RXD[3:0],
RX_CLK, RX_DV, RX_ER,
TX_CLK
I
OL
= 4.0mA
V
DD_MII
= 5V; I
OL
= 43.0mA
V
DD_MII
= 3.3V, I
OL
= 26.0mA
V
OL
-
-
-
-
-
-
0.4
3.05
2.1
V
Output Low Voltage (MII_DRV = 0)
COL, CRS, MDIO, RXD[3:0],
RX_CLK, RX_DV, RX_ER,
TX_CLK
I
OL
= 4.0mA
V
OL
-
-
0.4
V
DS206TPP2
69
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
DC CHARACTERISTICS (CONT.)
Parameter
Symbol
Min
Typ
Max
Unit
Digital I/O (cont.)
Output High Voltage
CLK25, SPD10, SPD100
I
OH
= -4.0mA
V
OH
2.4
-
-
V
Output High Voltage (MII_DRV = 1)
COL, CRS, MDIO, RXD[3:0],
RX_CLK, RX_DV, RX_ER,
TX_CLK
I
OH
= -4.0mA
V
DD_MII
= 5V; I
OH
= -20.0mA
V
DD_MII
= 3.3V, I
OH
= -20.0mA
V
OH
2.4
1.1
1.1
-
-
-
-
-
-
V
Output High Voltage (MII_DRV = 0)
COL, CRS, MDIO, RXD[3:0],
RX_CLK, RX_DV, RX_ER,
TX_CLK
I
OH
= -4.0mA
V
OH
2.4
-
-
V
Input Low Voltage
All Inputs Except AN[1:0], TCM, TXSLEW[1:0],
XTAL_I
V
IL
-
-
0.8
V
Input High Voltage
All Inputs Except AN[1:0], TCM, TXSLEW[1:0],
XTAL_I
V
IH
2.0
-
V
DD_MII
+
0.3
V
Tri-Level Input Voltages
AN[1:0], TCM, TXSLEW[1:0]
V
IL
V
IM
V
IH
-
1/3 V
DD_MII
+ 20%
2/3 V
DD_MII
+ 20%
-
-
-
1/3 V
DD_MII
- 20%
2/3 V
DD_MII
- 20%
-
V
Input Low Current
MDC, TXD[3:0], TX_CLK, TX_EN,
TX_ER
V
I
= 0.0V
MDIO
V
I
= 0.0V
I
IL
-20
-3800
-
-
-
-
A
Input High Current
MDC, TXD[3:0], TX_CLK, TX_EN,
TX_ER
V
I
= 5.0V
MDIO
V
I
= 5.0V
I
IH
-
-
-
-
200
20
A
Input Leakage Current
All Other Inputs
0<=V<=V
DD
I
LEAK
-10
-
+10
A
70
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
SWITCHING CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
10BASE-T Interface
Transmitter Differential Output Voltage (Peak)
V
OD
2.2
-
2.8
V
Receiver Normal Squelch Level (Peak)
V
ISQ
300
-
525
mV
Receiver Low Squelch Level (LoRxSquelch bit
set)
V
SQL
125
-
290
mV
100BASE-TX Interface
Transmitter Differential Output Voltage (Peak)
V
OP
0.95
-
1.05
V
Transmitter Signal Amplitude Symmetry
V
SYM
98
-
102
%
Transmitter Differential Output Impedance
Z
OUT
-
100
-
ohms
Transmit Rise/Fall Time
t
RF
3.0
-
5.0
ns
Transmit Rise/Fall Symmetry
t
RFS
-
-
0.5
ns
Transmit Duty Cycle Distortion
t
DCD
-
-
+/-0.5
ns
Transmit Overshoot/Undershoot
t
OS
-
-
5
%
Transmit Jitter
t
JT
-
400
1400
ps
Receive Signal Detect Assert Threshold
-
-
1.0
V
p-p
Receive Signal Detect De-assert Threshold
0.2
-
-
V
p-p
Receive Signal Detect Assert Time
-
-
1000
s
Receive Signal Detect De-assert Time
-
-
350
s
DS206TPP2
71
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
SWITCHING CHARACTERISTICS (CONT.)
Parameter
Symbol
Min
Typ
Max
Unit
10BASE-T Serial Mode Transmit Timing
TX_CLK Period
t
TCP
-
100
-
ns
TX_CLK Pulse Width
t
TCH
, t
TCL
-
50
-
ns
Transmit Data Setup to TX_CLK
t
TDS
10
-
-
ns
Transmit Data Hold from TX_CLK
t
TDH
10
-
-
ns
Transmit Throughput Delay
t
TPD
-
-
500
ns
TX+/- Pair Jitter into 100
Load
t
TXJ
-
-
8
ns
TX+/- Pair Positive Hold Time at End of Packet
t
TXH
250
-
-
ns
TX+/- Pair Return to
50 mV after Last Positive
Transition
t
TXOFF
-
-
4.5
s
In/Out
TXD0
TX_CLK
TX+/TX-
t
TDS
Out
TX_EN
In
t
TXH
t
TDH
t
TCP
In
t
TXJ
t
TCH
t
TCL
t
TXOFF
t
TPD
72
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
SWITCHING CHARACTERISTICS (CONT.)
Parameter
Symbol
Min
Typ
Max
Unit
10BASE-T Serial Mode Receive Timing
Allowable Received Jitter
t
RXJ
-
-
+/-13.5
ns
Carrier Sense Assertion Delay
t
RCRSA
300
-
600
ns
Carrier Sense Deassertion Delay
t
RCRSD
-
-
400
ns
Collision Assertion Delay
t
RCOLA
300
-
600
ns
Collision Deassertion Delay
t
RCOLD
-
-
400
ns
RX_CLK Period
t
RCP
-
100
-
ns
RX_CLK Pulse Width
t
RCH
, t
RCL
-
50
-
ns
Carrier Sense Hold from RX_CLK
t
RCRSH
35
-
-
ns
RX_CLK Rising Edges After Carrier Sense Deas-
serted
t
RCYC
6
-
-
#
Receive Data Throughput Delay
t
RLAT
-
-
250
ns
Receive Data Setup to RX_CLK
t
RDS
35
-
-
ns
Receive Data Hold from RX_CLK
t
RDH
50
-
-
ns
RXD0
RX_CLK
RX+/RX-
t
RDS
t
RLAT
CRS
t
RCP
t
RCH
t
RCL
t
RDH
t
RCRSA
t
RCRSD
COL
t
RCOLA
t
RCOLD
t
RCYC
t
RCSRH
t
RXJ
DS206TPP2
73
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
SWITCHING CHARACTERISTICS (CONT.)
Parameter
Symbol
Min
Typ
Max
Unit
10Base-T Jabber/Unjabber Timing
Maximum Transmit Time
t
JAB
-
105
-
ms
Unjabber Time
t
UNJAB
-
406
-
ms
Parameter
Symbol
Min
Typ
Max
Unit
10Base-T SQE (Heartbeat) Timing
COL (SQE) Delay after TX_EN off
t
SQED
-
1.4
-
s
COL (SQE) Pulse Width
t
SQEP
-
1.3
-
s
t
JAB
TX_EN
TX+/TX-
t
UNJAB
COL
In
Out
Out
t
SQED
TX_EN
TX_CLK
In/Out
COL
t
SQEP
In
Out
t
TES
74
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
SWITCHING CHARACTERISTICS (CONT.)
Parameter
Symbol
Min
Typ
Max
Unit
Auto-negotiation and Fast Link Pulses
Clock/Data Pulse Width
t
LPW
80
100
130
ns
Clock Pulse to Data Pulse Time
t
LCDW
55.5
64
69.5
s
Clock Pulse to Clock Pulse Time
t
LCCW
111
128
139
s
Fast Link Pulse (FLP) Burst Width
t
FLW
-
2
-
ms
FLP Burst to FLP Burst Time
t
LPP
15
16
17
ms
Fast Link Pulses per Burst
17
-
33
10BASE-T Link Integrity
First Transmitted Link Pulse after Last Transmit-
ted Packet
t
LN1
15
16
17
ms
Minimum Received Link Pulses Separation
t
LN4
-
-
7
ms
Maximum Received Link Pulse Separation
t
LN5
50
-
-
ms
Last Receive Activity to Link Fail (Link Loss
Timer)
t
LN6
50
52
150
ms
t
LPW
Fast Link Pulses
FLP Bursts
t
LCDW
t
FLW
t
LPP
Normal Link Pulses
Clock
Pulse
Clock
Pulse
Data
Pulse
t
LCCW
t
LPW
DS206TPP2
75
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
SWITCHING CHARACTERISTICS (CONT.)
Parameter
Symbol
Min
Typ
Max
Unit
100BASE-X MII Receive Timing
"Start of Stream" to CRS asserted
t
RCRSA
-
10
11
BT
"End of Stream" to CRS de-asserted
t
RCRSD
-
-
21
BT
"Start of Stream" to COL asserted
t
RCOLA
-
-
11
BT
"End of Stream" to COL de-asserted
t
RCOLD
-
-
21
BT
RX_CLK Period
t
RCP
-
40
-
ns
RX_CLK Pulse Width
t
RCL,
t
RCH
-
20
-
ns
"Start of Stream" to RXD latency
Aligned
Alignment Bypassed
t
RLAT
12
5
15
-
19
9
BT
RXD[3:0],RX_ER/RXD4,RX_DV setup to rising
edge of RX_CLK
t
RDS
10
-
-
ns
RXD[3:0],RX_ER/RXD4,RX_DV hold from rising
edge of RX_CLK
t
RDH
10
-
-
ns
RX_EN asserted to RX_DV, RX_ER, RXD[3:0]
valid
t
REN
-
-
60
ns
RX_EN de-asserted to RX_DV, RX_ER,
RXD[3:0], RX_ER/RXD4 tristated
t
RDIS
-
-
60
ns
Out
RXD[4:0],
RX_ER
RX_CLK
RX+/RX-
RX_DV
t
RDS
t
RLAT
Out
Out
In
CRS
Out
t
RCP
t
RCH
t
RCL
t
RDH
t
RCRSA
t
RCRSD
COL
Out
t
RCOLA
t
RCOLD
RXD[4:0],
RX_DV,
RX_ER
RX_EN
In
Out
t
REN
t
RDIS
76
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
SWITCHING CHARACTERISTICS (CONT.)
Parameter
Symbol
Min
Typ
Max
Unit
100BASE-X MII Transmit Timing
TX_CLK Period
t
TCP
-
40
-
ns
TX_CLK Pulse Width
t
TCL,
t
TCH
-
20
-
ns
TXD[3:0], TX_ER, TX_EN Setup to TX_CLK High
t
TDS
10
-
-
ns
TXD[3:0], TX_ER, TX_EN Hold after TX_CLK
High
t
TDH
0
-
-
ns
TX_CLK to CRS asserted latency
t
TCRSA
-
-
8
BT
TX_CLK to CRS de-asserted latency
t
TCRSD
-
-
8
BT
TX_CLK to TX+/- output (TX Latency)
Aligned
Alignment Bypassed
t
TPD
6
-
7
6
8
7
BT
In/Out
TXD[4:0],
TX_ER
TX_CLK
TX+/TX-
TX_EN
t
TCRSA
In
In
Out
CRS
Out
t
TPD
t
TCP
t
TCH
t
TCL
t
TDS
t
TDH
t
TCRSD
DS206TPP2
77
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
SWITCHING CHARACTERISTICS (CONT.)
Parameter
Symbol
Min
Typ
Max
Unit
10BASE-T MII Receive Timing
RX+/- preamble to CRS asserted
t
RCRSA
-
5
7
BT
RX+/- end of packet to CRS de-asserted
t
RCRSD
2.5
3
BT
RX+/- preamble to COL asserted
t
RCOLA
0
-
7
BT
RX+/- end of packet to COL de-asserted
t
RCOLD
-
-
3
BT
RX_CLK Period
t
RCP
-
400
-
ns
RX_CLK Pulse Width
t
RCL,
t
RCH
-
200
-
ns
"Start of Stream" to RXD latency
t
RLAT
-
13
17
BT
RXD[3:0], RX_ER, RX_DV setup to rising edge of
RX_CLK
t
RDS
30
-
-
ns
RXD[3:0], RX_ER, RX_DV hold from rising edge
of RX_CLK
t
RDH
30
-
-
ns
RX_EN asserted to RX_DV, RXD[3:0], RX_ER
valid
t
REN
-
-
60
ns
RX_EN de-asserted to RX_DV, RXD[3:0]. RX_ER
in high impedance state
t
RDIS
-
-
60
ns
Out
RXD[3:0],
RX_ER
RX_CLK
RX+/RX-
RX_DV
t
RDS
t
RLAT
Out
Out
In
CRS
Out
t
RCP
t
RCH
t
RCL
t
RDH
t
RCRSA
t
RCRSD
COL
Out
t
RCOLA
t
RCOLD
RXD[4:0],
RX_DV,
RX_ER
RX_EN
In
Out
t
REN
t
RDIS
78
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
SWITCHING CHARACTERISTICS (CONT.)
Parameter
Symbol
Min
Typ
Max
Unit
10BASE-T MII Transmit Timing
TX_CLK Period
t
TCP
-
400
-
ns
TX_CLK Pulse Width
t
TCL,
t
TCH
-
200
-
ns
TXD[3:0], TX_EN, TX_ER Setup to TX_CLK High
t
TDS
10
-
-
ns
TXD[3:0], TX_EN, TX_ER Hold after TX_CLK
High
t
TDH
0
-
-
ns
TX_CLK to CRS asserted latency
t
TCRSA
0
-
4
BT
TX_CLK to CRS de-asserted latency
t
TCRSD
0
-
16
BT
TX_CLK to TX+/- output (TX Latency)
t
TPD
6
-
14
BT
TX+/- hold at end of packet
t
TXH
250
-
-
ns
TX+/- return to idle (<= 50 mV)
t
TXOFF
-
-
4.5
s
In/Out
TXD[3:0],
TX_ER
TX_CLK
TX+/TX-
TX_EN
t
TCRSA
In
In
Out
CRS
Out
t
TPD
t
TCP
t
TCH
t
TCL
t
TDS
t
TDH
t
TCRSD
t
TXH
t
TXOFF
DS206TPP2
79
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
SWITCHING CHARACTERISTICS (CONT.)
Parameter
Symbol
Min
Typ
Max
Unit
10BASE-T Serial Receive Timing
Allowable receive jitter at bit cell center
t
RXJ
-
-
+/- 13.5
ns
RX+/- active to CRS active
t
RCRSA
-
-
600
ns
CRS de-asserted after RX+/- inactive
t
RCRSD
-
-
400
ns
RX+/- active to COL active
t
RCOLA
-
-
600
ns
COL de-asserted after RX+/- inactive
t
RCOLD
-
-
400
ns
RX_CLK Period
t
RCP
-
400
-
ns
RX_CLK Pulse Width
t
RCL,
t
RCH
-
200
-
ns
CSR hold from RX_CLK
t
RCSRH
5
-
-
ns
RX_CLK hold after CRS off
t
RCYC
5
-
-
cycles
RXD[0] throughput delay
t
RLAT
-
-
1200
ns
RXD[0] setup from RX_CLK
t
RDS
35
-
-
ns
RXD[0] hold from RX_CLK
t
RDH
50
-
-
ns
Out
RXD0
RX_CLK
RX+/RX-
t
RDS
t
RLAT
In
CRS
Out
t
RCP
t
RCH
t
RCL
t
RDH
t
RCRSA
t
RCRSD
COL
Out
t
RCOLA
t
RCOLD
t
RCYC
Out
t
RCSRH
t
RXJ
80
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
SWITCHING CHARACTERISTICS (CONT.)
Parameter
Symbol
Min
Typ
Max
Unit
10BASE-T Serial Transmit Timing
TX_CLK Period
t
TCP
-
400
-
ns
TX_CLK Pulse Width
t
TCL,
t
TCH
-
200
-
ns
TXD[0], TX_EN Setup from TX_CLK
t
TDS
10
-
-
ns
TXD[0], TX_EN Hold after TX_CLK
t
TDH
10
-
-
ns
Transmit throughput delay
t
TPD
-
-
500
ns
TXD+/- jitter
t
TPD
-
-
+/- 8
ns
TX+/- hold at end of packet
t
TXH
250
-
-
ns
TX+/- return to idle (<= 50 mV)
t
TXOFF
-
-
4.5
s
In/Out
TXD0
TX_CLK
TX+/TX-
t
TDS
Out
TX_EN
In
t
TXH
t
TDH
t
TCP
In
t
TXJ
t
TCH
t
TCL
t
TXOFF
t
TPD
DS206TPP2
81
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
SWITCHING CHARACTERISTICS (CONT.)
Parameter
Symbol
Min
Typ
Max
Unit
Serial Management Interface
MDC Period
t
MDCP
60
-
-
ns
MDC Pulse Width
t
MDCL,
t
MDCH
40
-
60
%
MDIO Setup to MDC (MDIO as input)
t
MDIS
10
-
-
ns
MDIO Hold after MDC (MDIO as input)
t
MDIH
10
-
-
ns
MDC to MDIO valid (MDIO as output)
t
MDO
0
-
40
ns
MDC
MDIO (Input)
Valid Data
In
In
Out
MDIO (Output)
Valid Data
t
MDCP
t
MDIH
t
MDIS
t
MDO
t
MDCH
t
MDCL
82
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
MECHANICAL SPECIFICATIONS
Package Dimensions
DIM
Min
Max
Unit
A
-
1.60
mm
A1
0.05
0.15
mm
B
0.17
0.27
mm
D
15.70
16.30
mm
D1
13.90
14.10
mm
E
15.70
16.30
mm
E1
13.90
14.10
mm
e (Note 1)
0.40
0.60
mm
L
0.45
0.75
mm
0.00
7.00
degrees
1.
Nominal pin pitch is 0.50 mm.
E1
E
D1
D
1
e
L
B
A1
A
DS206TPP2
83
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Recommended PCB Footprint
DIM
Min
Typ
Max
Unit
C
-
15.40
-
mm
D
-
12.00
-
mm
E
-
0.50
-
mm
G
13.80
-
14.00
mm
X
0.30
-
0.40
mm
Y
-
1.60
-
mm
Z
16.80
-
17.00
mm
E
C
D
G
Z
Y
X
84
DS206TPP2
CS8952T
CrystalLANTM 100BASE-X and 10BASE-T Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
REVISION HISTORY
Revision
Changes
PP1
- Initial publication.
PP2
- Added electrical and timing specifications.
- Reformatted register information.
- Changed order of pin description and electrical specifications sections.
PP3
- Changed VDD_MII pin description to make it clear it powers all I/O pads except XTAL_I, not just
MII.
- Added V
IH
max specification in DC Characteristics section.
- Changed XTAL_I input capacitance specification from max to typ since it is not actually mea-
sured at test.
- Moved electrical specification and pin description sections back where they were in PP1.
- Added XTAL_I pin to V
IL
and V
IH
exception lists.
- Fixed pin diagram figure to reverse RX_NRZ+/- and TEST0/1.
- Added typical PCB footprint in mechanical section.
- Changed XTAL_I electrical specification to reflect the fact it is referenced to VDD instead of
VDD_MII.
- Added more verbiage to Functional Description.
Notes