This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

MAR `05

DS636PP5

http://www.cirrus.com

Entry-level ARM9

System-on-chip Processor

EP9301 Data Sheet

Preliminary Product Information

FEATURES

· 166-MHz ARM920T Processor

· 16-kbyte Instruction Cache
· 16-kbyte Data Cache

· Linux

, Microsoft

Windows

CE, enabled MMU

· 66-MHz System Bus

· MaverickKey

IDs

· 32-bit unique ID can be used for DRM-compliant,

128-bit random ID.

· Integrated Peripheral Interfaces

· 16-bit SDRAM Interface (up to 4 banks)
· 16-bit SRAM / FLASH / ROM
· Serial EEPROM Interface
· 1/10/100 Mbps Ethernet MAC
· Two UARTs
· Two-port USB 2.0 Full-speed Host (OHCI)

(12 Mbits per second)

· IrDA Interface
· ADC
· Serial Peripheral Interface (SPI) Port

· 6-channel Serial Audio Interface (I

· 2-channel Low-cost Serial Audio Interface (AC'97)

· Internal Peripherals

· 12 Direct Memory Access (DMA) Channels
· Real-time Clock with software Trim
· Dual PLL controls all clock domains.
· Watchdog Timer
· Two General-purpose 16-bit Timers
· One General-purpose 32-bit Timer
· One 40-bit Debug Timer
· Interrupt Controller
· Boot ROM

· Package

· 208-pin LQFP

Unified

SDRAM I/F

(2) USB

Hosts

Ethernet

MAC

Bus Bridge

Boot
ROM

MaverickKey

12 Channel DMA

SRAM &

Flash I/F

ARM920T

MMU

D-Cache

16KB

I-Cache

16KB

Processor Bus

Peripheral Bus

Serial
Audio

Interface

Interrupts

& GPIO

Clocks &

Timers

(2) UARTs

IrDA

MMUNIC

TIONS P

RTS

SER INTERFAC

MEMORY AND STORAGE

DS636PP5

EP9301
Entry Level ARM9 System-on-Chip Processor

The EP9301 is an ARM920T-based system-on-a-chip
design with a large peripheral set targeted to a variety of
applications:

· Industrial controls
· Digital media servers
· Integrated home media gateways
· Digital audio jukeboxes
· Streaming audio players
· Set-top boxes
· Point-of-sale terminals
· Thin clients
· Biometric security systems
· GPS & fleet management systems
· Educational toys
· Industrial computers
· Industrial hand-held devices
· Voting machines
· Medical equipment

The EP9301 is one of a series of ARM920T-based
devices. Other members of the family have different
peripheral sets, a coprocessor, and different package
configurations.

The ARM920T microprocessor core has a separate 16-
kbyte, 64-way set-associative instruction and data
caches.

The MaverickKey

unique hardware programmed IDs

are a solution to the growing concern over secure web
content and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.
A high-performance 1/10/100 Mbps Ethernet media
access controller (EMAC) is included along with external
interfaces to SPI, AC'97 and I

S audio. A two-port USB

2.0 Full-speed Host (OHCI) (12 Mbits per second), two
UARTs, and a analog voltage measurement analog-to-
digital converter (ADC) are included as well.

The EP9301 is a high-performance, low-power RISC-
based, single-chip computer built around an ARM920T
microprocessor core with a maximum operating clock
rate of 166 MHz. The ARM core operates from a 1.8 V
supply, while the I/O operates at 3.3 V with power usage
between 100 mW and 675 mW.

OVERVIEW

Table A. Change History

Revision

Date

Changes

October 2003

Initial Release.

February 2004

Update timing specifications.

July 2004

Update AC data.

July 2004

Add ADC data.

March 2005

Update with most-current characterization data.

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

Table of Contents

FEATURES .........................................................................................................1
OVERVIEW .........................................................................................................2

Processor Core - ARM920T ......................................................................................... 6
MaverickKeyTM Unique ID ............................................................................................ 6
General Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH) ........................ 6
Ethernet Media Access Controller (MAC) .................................................................... 7
Serial Interfaces (SPI, I2S, and AC '97) ....................................................................... 7
12-bit Analog-to-digital Converter (ADC) ..................................................................... 7
Universal Asynchronous Receiver/Transmitters (UARTs) ............................................ 8
Dual Port USB Host ..................................................................................................... 8
Two-Wire Interface With EEPROM Support ................................................................ 8
Real-Time Clock with Software Trim ............................................................................ 8
PLL and Clocking ......................................................................................................... 9
Timers .......................................................................................................................... 9
Interrupt Controller ....................................................................................................... 9
Dual LED Drivers ......................................................................................................... 9
General Purpose Input/Output (GPIO) ......................................................................... 9
Reset and Power Management ................................................................................. 10
Hardware Debug Interface ......................................................................................... 10
12-Channel DMA Controller ....................................................................................... 10
Internal Boot ROM ..................................................................................................... 10

Electrical Specifications ................................................................................. 11

Absolute Maximum Ratings ........................................................................................11
Recommended Operating Conditions .........................................................................11
DC Characteristics ..................................................................................................... 12

Timings .............................................................................................................13

Memory Interface ....................................................................................................... 14
Ethernet MAC Interface ............................................................................................ 27
Audio Interface ........................................................................................................... 29
AC'97 ........................................................................................................................ 32
ADC ........................................................................................................................... 33
JTAG .......................................................................................................................... 34

208 Pin LQFP Package Outline .....................................................................35

208 Pin LQFP Pinout ................................................................................................. 36

Acronyms and Abbreviations ........................................................................40
Units of Measurement .....................................................................................40
ORDERING INFORMATION ............................................................................41

DS636PP5

EP9301
Entry Level ARM9 System-on-Chip Processor

List of Figures

Figure 1. Timing Diagram Drawing Key .................................................................................13
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement ..................................... 14
Figure 3. SDRAM Burst Read Cycle Timing Measurement ................................................... 15
Figure 4. SDRAM Burst Write Cycle Timing Measurement ................................................... 16
Figure 5. SDRAM Auto Refresh Cycle Timing Measurement ................................................ 17
Figure 6. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement .................... 18
Figure 7. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement .................... 19
Figure 8. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement .................. 20
Figure 9. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement .................. 21
Figure 10. Static Memory Burst Read Cycle Timing Measurement .......................................22
Figure 11. Static Memory Burst Write Cycle Timing Measurement .......................................23
Figure 12. Static Memory Single Read Wait Cycle Timing Measurement ............................. 24
Figure 13. Static Memory Single Write Wait Cycle Timing Measurement .............................. 25
Figure 14. Static Memory Turnaround Cycle Timing Measurement .......................................26
Figure 15. Ethernet MAC Timing Measurement ..................................................................... 28
Figure 16. TI Single Transfer Timing Measurement ............................................................... 29
Figure 17. Microwire Frame Format, Single Transfer ............................................................ 29
Figure 18. SPI Format with SPH=1 Timing Measurement ..................................................... 30
Figure 19. Inter-IC Sound (I2S) Timing Measurement ........................................................... 31
Figure 20. AC `97 Configuration Timing Measurement .......................................................... 32
Figure 21. ADC Transfer Function ......................................................................................... 33
Figure 22. JTAG Timing Measurement .................................................................................. 34

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

List of Tables

Table A. Change History .......................................................................................................... 2
Table B. General Purpose Memory Interface Pin Assignments .............................................. 6
Table C. Ethernet Media Access Controller Pin Assignments ................................................. 7
Table D. Audio Interfaces Pin Assignment .............................................................................. 7
Table E. 12-bit Analog-to-Digital Converter Pin Assignments ................................................. 7
Table F. Universal Asynchronous Receiver/Transmitters Pin Assignments ............................ 8
Table G. Dual Port USB Host Pin Assignments ....................................................................... 8
Table H. Two-Wire Port with EEPROM Support Pin Assignments .......................................... 8
Table I. Real-Time Clock with Pin Assignments ..................................................................... 8
Table J. PLL and Clocking Pin Assignments .......................................................................... 9
Table K. Interrupt Controller Pin Assignment .......................................................................... 9
Table L. Dual LED Pin Assignments ....................................................................................... 9
Table M.General Purpose Input/Output Pin Assignment ........................................................ 9
Table N. Reset and Power Management Pin Assignments ................................................... 10
Table O. Hardware Debug Interface ...................................................................................... 10
Table P. Pin List in Numerical Order by Pin Number ............................................................. 36
Table Q. Pin Description ...................................................................................................... 38
Table R. Pin Multiplex Usage Information ............................................................................. 39

DS636PP5

EP9301
Entry Level ARM9 System-on-Chip Processor

Processor Core - ARM920T

The ARM920T is a Harvard architecture processor with
separate 16-kbyte instruction and data caches with an 8-
word line length but a unified memory. The processor
utilizes a five-stage pipeline consisting of fetch, decode,
execute, memory, and write stages. Key features include:

· ARM (32-bit) and Thumb (16-bit compressed)

instruction sets

· 32-bit Advanced Micro-Controller Bus Architecture

(AMBA)

· 16 kbyte Instruction Cache with lockdown
· 16 kbyte Data Cache (programmable write-through or

write-back) with lockdown

· MMU for Linux

, Microsoft

Windows

CE and other

operating systems

· Translation Look Aside Buffers with 64 Data and 64

Instruction Entries

· Programmable Page Sizes of 1 Mbyte, 64 kbyte,

4 kbyte, and 1 kbyte

· Independent lockdown of TLB Entries

MaverickKey

Unique ID

MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.

Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP9301 through the use of laser
probing technology. These IDs can then be used to
match secure copyrighted content with the ID of the
target device the EP9301 is powering, and then deliver
the copyrighted information over a secure connection. In
addition, secure transactions can benefit by also
matching device IDs to server IDs. MaverickKey IDs
provide a level of hardware security required for today's
Internet appliances.

General Purpose Memory Interface (SDRAM,
SRAM, ROM, FLASH)

The EP9301 features a unified memory address model
where all memory devices are accessed over a common
address/data bus. Memory accesses are performed via
the Processor bus. The SRAM memory controller
supports 8- and 16-bit devices and accommodates an
internal boot ROM concurrently with 16-bit SDRAM
memory.

· 1 to 4 banks of 16-bit, 66 MHz SDRAM
· Address and data bus shared between SDRAM,

SRAM, ROM, and FLASH memory

· NOR FLASH memory supported

Table B. General Purpose Memory Interface Pin Assignments

Pin Mnemonic

Pin Description

SDCLK

SDRAM Clock

SDCLKEN

SDRAM Clock Enable

SDCSn[3:0]

SDRAM Chip Selects 3-0

RASn

SDRAM RAS

CASn

SDRAM CAS

SDWEn

SDRAM Write Enable

CSn[7:6] and CSn[3:0]

Chip Selects 7, 6, 3, 2, 1, 0

AD[25:0]

Address Bus 25-0

DA[15:0]

Data Bus 15-0

DQMn[1:0]

SDRAM Output Enables / Data Masks

WRn

SRAM Write Strobe

RDn

SRAM Read / OE Strobe

WAITn

SRAM Wait Input

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

Ethernet Media Access Controller (MAC)

The MAC subsystem is compliant with the ISO/TEC
802.3 topology for a single shared medium with several
stations. Multiple MII-compliant PHYs are supported.
Features include:

· Supports 1/10/100 Mbps transfer rates for home /

small-business / large-business applications

· Interfaces to an off-chip PHY through industry

standard Media Independent Interface (MII)

Serial Interfaces (SPI, I

S, and AC '97)

The Serial Peripheral Interface (SPI) port can be
configured as a master or a slave, supporting the
National Semiconductor

, Motorola

, and Texas

Instruments

signaling protocols.

The AC'97 port supports multiple codecs for multichannel
audio output with a single stereo input. The I

S port

supports stereo 24-bit audio.

These ports are multiplexed so that the I

S port will take

over either the AC'97 pins or the SPI pins.

· Normal Mode: One SPI Port and one AC'97 Port

· I

S on SSP Mode: One AC'97 Port and one I

S Port

· I

S on AC'97 Mode: One SPI Port and one I

S Port

Note:

S may not be output on AC'97 and SSP ports at the

same time.

12-bit Analog-to-digital Converter (ADC)

The ADC block consists of a 12-bit analog-to-digital
converter with a analog input multiplexer. The multiplexer
can select to measure battery voltage and other
miscellaneous voltages on the external measurement
pins. Features include:

· 5 external pins for ADC measurement
· Measurement pin input range: 0 to 3.3 V.
· ADC-conversion-complete interrupt signal

Table C. Ethernet Media Access Controller Pin Assignments

Pin Mnemonic

Pin Description

MDC

Management Data Clock

MDIO

Management Data I/O

RXCLK

Receive Clock

MIIRXD[3:0]

Receive Data

RXDVAL

Receive Data Valid

RXERR

Receive Data Error

TXCLK

Transmit Clock

MIITXD[3:0]

Transmit Data

TXEN

Transmit Enable

TXERR

Transmit Error

CRS

Carrier Sense

CLD

Collision Detect

Table D. Audio Interfaces Pin Assignment

Pin

Name

Normal Mode

S on SSP

Mode

S on AC'97

Mode

Pin

Description

Pin Description Pin Description

SCLK1

SPI Bit Clock

I2S Serial Clock

SPI Bit Clock

SFRM1

SPI Frame Clock I2S Frame Clock

SPI Frame Clock

SSPRX1 SPI Serial Input

I2S Serial Input

SPI Serial Input

SSPTX1

SPI Serial
Output

I2S Serial Output

SPI Serial Output

(No I2S Master
Clock)

ARSTn

AC'97 Reset

I2S Master Clock

ABITCLK AC'97 Bit Clock

AC'97 Bit Clock

I2S Serial Clock

ASYNC

AC'97 Frame
Clock

I2S Frame Clock

ASDI

AC'97 Serial
Input

AC'97 Serial Input I2S Serial Input

ASDO

AC'97 Serial
Output

AC'97 Serial Output I2S Serial Output

Table E. 12-bit Analog-to-Digital Converter Pin Assignments

Pin Mnemonic

Pin Description

ADC[0] (Ym, pin 135)

External Analog Measurement Input

ADC[1] (sXp, pin 134)

External Analog Measurement Input

ADC[2] (sXm, pin 133)

External Analog Measurement Input

ADC[3] (sYp, pin 132)

External Analog Measurement Input

ADC[4] (sYm, pin 131)

External Analog Measurement Input

DS636PP5

EP9301
Entry Level ARM9 System-on-Chip Processor

Universal Asynchronous
Receiver/Transmitters (UARTs)

Two 16550-compatible UARTs are supplied. One
provides asynchronous HDLC (High-level Data Link
Control) protocol support for full duplex transmit and
receive. The HDLC receiver handles framing, address
matching, CRC checking, control-octet transparency, and
optionally passes the CRC to the host at the end of the
packet. The HDLC transmitter handles framing, CRC
generation, and control-octet transparency. The host
must assemble the frame in memory before
transmission. The HDLC receiver and transmitter use the
UART FIFOs to buffer the data streams. The second
UART provides IrDA

compatibility.

· UART1 supports modem bit rates up to 115.2 kbps,

supports HDLC and includes a 16 byte FIFO for
receive and a 16 byte FIFO for transmit. Interrupts are
generated on Rx, Tx and modem status change.

· UART2 contains an IrDA encoder operating at either

the slow (up to 115 kbps), medium (0.576 or 1.152
Mbps), or fast (4 Mbps) IR data rates. It also has a 16
byte FIFO for receive and a 16 byte FIFO for transmit.

Dual Port USB Host

The USB Open Host Controller Interface (Open HCI)
provides full speed serial communications ports at a
baud rate of 12 Mbits/sec. Up to 127 USB devices
(printer, mouse, camera, keyboard, etc.) and USB hubs
can be connected to the USB host in the USB "tiered-
start" topology.

This includes the following feature:

· Compliance with the USB 2.0 specification
· Compliance with the Open HCI Rev 1.0 specification

· Supports both low speed (1.5 Mbps) and full speed

(12 Mbps) USB device connections

· Root HUB integrated with 2 downstream USB ports
· Transceiver buffers integrated, over-current protection

on ports

· Supports power management
· Operates as a master on the bus
The Open HCI host controller initializes the master DMA
transfer with the AHB bus:

· Fetches endpoint descriptors and transfer descriptors
· Accesses endpoint data from system memory
· Accesses the HC communication area
· Writes status and retire transfer descriptor

Note:

USBm[1] and USBp[1] are not bonded out.

Two-Wire Interface With EEPROM Support

The two-wire interface provides communication and
control for synchronous-serial-driven devices.

Real-Time Clock with Software Trim

The software trim feature on the real time clock (RTC)
provides software controlled digital compensation of the
32.768 KHz input clock. This compensation is accurate to

1.24 sec/month.

Note:

A real time clock must be connected to RTCXTALI or
the EP9301device will not boot.

Table F. Universal Asynchronous Receiver/Transmitters Pin

Assignments

Pin Mnemonic

Pin Name - Description

TXD0

UART1 Transmit

RXD0

UART1 Receive

CTSn

UART1 Clear To
Send / Transmit Enable

DSRn / DCDn

UART1 Data Set
Ready / Data Carrier Detect

DTRn

UART1 Data Terminal Ready

RTSn

UART1 Ready To Send

EGPIO[0] / RI

UART1 Ring Indicator

TXD1 / SIROUT

UART2 Transmit / IrDA
Output

RXD1 / SIRIN

UART2 Receive / IrDA Input

Table G. Dual Port USB Host Pin Assignments

Pin Mnemonic

Pin Name - Description

USBp[2,0]

USB Positive signals

USBm[2,0]

USB Negative Signals

Table H. Two-Wire Port with EEPROM Support Pin Assignments

Pin Mnemonic

Pin Name - Description

Alternative

Usage

EECLK

Two-wire Interface Clock

General
Purpose I/O

EEDATA

Two-wire Interface Data

General
Purpose I/O

Table I. Real-Time Clock with Pin Assignments

Pin Mnemonic

Pin Name - Description

RTCXTALI

Real-Time Clock Oscillator Input

RTCXTALO

Real-Time Clock Oscillator Output

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

PLL and Clocking

The Processor and the Peripheral Clocks operate from a
single 14.7456 MHz crystal.

The Real Time Clock operates from a 32.768 KHz
external oscillator.

Timers

The Watchdog Timer ensures proper operation by
requiring periodic attention to prevent a reset-on-time-
out.

Two 16-bit timers operate as free-running down counters
or as periodic timers for fixed-interval interrupts and have
a range of 0.03 ms to 4.27 seconds.

One 32-bit timer, plus a 6-bit prescale counter, has a
range of 0.03

s to 73.3 hours.

One 40-bit debug timer, plus a 6-bit prescale counter, has
a range of 1.0

s to 12.7 days.

Interrupt Controller

The interrupt controller allows up to 54 interrupts to
generate an Interrupt Request (IRQ) or Fast Interrupt
Request (FIQ) signal to the processor core. Thirty-two
hardware priority assignments are provided for assisting
IRQ vectoring, and two levels are provided for FIQ
vectoring. This allows time-critical interrupts to be
processed in the shortest time possible. Internal
interrupts may be programmed as active high or active
low level sensitive inputs. GPIO pins programmed as
interrupts may be programmed as active high level
sensitive, active low level sensitive, rising edge triggered,
falling edge triggered, or combined rising/falling edge
triggered.

· Supports 54 interrupts from a variety of sources (such

as UARTs, GPIO and ADC)

· Routes interrupt sources to either the ARM920T's

IRQ or FIQ (Fast IRQ) inputs

· Three dedicated off-chip interrupt lines INT[2:0]

operate as active-high level-sensitive interrupts

· Any of the 19 GPIO lines maybe configured to

generate interrupts

· Software supported priority mask for all FIQs and

IRQs

Note:

INT[2] is not bonded out.

Dual LED Drivers

Two pins are assigned specifically to drive external
LEDs.

General Purpose Input/Output (GPIO)

The 16 EGPIO and the 3 FGPIO pins may each be
configured individually as an output, an input or an
interrupt input.

There are 10 pins that may alternatively be used as input,
output, or open-drain pins, but do not support interrupts.
These pins are:

· Ethernet MDIO

· Both LED Outputs

· EEPROM Clock and Data

· HGPIO[5:2]

· CGPIO[0]

6 pins may alternatively be used as inputs only:

· CTSn, DSRn / DCDn

· 3 Interrupt Lines

2 pins may alternatively be used as outputs only:

· RTSn

· ARSTn

Table J. PLL and Clocking Pin Assignments

Pin Mnemonic

Pin Name - Description

XTALI

Main Oscillator Input

XTALO

Main Oscillator Output

VDD_PLL

Main Oscillator Power

GND_PLL

Main Oscillator Ground

Table K. External Interrupt Controller Pin Assignment

Pin Mnemonic

Pin Name - Description

INT[3] and INT[1:0]

External Interrupts 2, 1, 0

Table L. Dual LED Pin Assignments

Pin Mnemonic

Pin Name -

Description

Alternative Usage

GRLED

Green LED

General Purpose I/O

REDLED

Red LED

General Purpose I/O

Table M. General Purpose Input/Output Pin Assignment

Pin Mnemonic

Pin Name - Description

EGPIO[15:0]

Expanded General Purpose Input / Output
Pins with Interrupts

FGPIO[3:1]

Expanded General Purpose Input / Output
Pins with Interrupts

DS636PP5

EP9301
Entry Level ARM9 System-on-Chip Processor

Reset and Power Management

The chip may be reset through the PRSTn pin or through
the open drain common reset pin, RSTOn.

Clocks are managed on a peripheral-by-peripheral basis
and may be turned off to conserve power.

The processor clock is dynamically adjustable from 0 to
166 MHz.

Hardware Debug Interface

The JTAG interface allows use of ARM's Multi-ICE or
other in-circuit emulators.

12-channel DMA Controller

The DMA module contains 12 separate DMA channels.
Ten of these may be used for peripheral-to-memory or
memory-to-peripheral access. Two of these are
dedicated to memory-to-memory transfers. Each DMA
channel is connected to the 16-bit DMA request bus.

The request bus is a collection of requests, Serial Audio
and UARTs. Each DMA channel can be used
independently or dedicated to any request signal. For
each DMA channel, source and destination addressing
can be independently programmed to increment,
decrement, or stay at the same value. All DMA
addresses are physical, not virtual addresses.

Internal Boot ROM

The Internal 16 kbyte ROM allows booting from FLASH
memory, SPI or UART. Consult the EP93xx User's
Manual for operational details.

Table N. Reset and Power Management Pin Assignments

Pin Mnemonic

Pin Name - Description

PRSTn

Power On Reset

RSTOn

User Reset In/Out Open Drain
Preserves Real Time Clock value

Table O. Hardware Debug Interface

Pin Mnemonic

Pin Name - Description

TCK

JTAG Clock

TDI

JTAG Data In

TDO

JTAG Data Out

TMS

JTAG Test Mode Select

TRSTn

JTAG Port Reset

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

Electrical Specifications

Absolute Maximum Ratings

Note:

1. Includes all power generated by AC and/or DC output loading.
2. The power supply pins are at recommended maximum values.
3. At ambient temperatures above 70° C, total power dissipation must be limited to less than 2.5 Watts.

WARNING: Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Recommended Operating Conditions

(All grounds = 0 V, all voltages with respect to 0 V)

Parameter

Symbol

Min

Max

Unit

Power Supplies

RVDD
CVDD

VDD_PLL

VDD_ADC

-
-
-
-

3.96
2.16
2.16
3.96

V
V
V
V

Total Power Dissipation

(Note 1)

Input Current per Pin, DC (Except supply pins)

±10

Output current per pin, DC

±50

Digital Input voltage

(Note 2)

-0.3

RVDD+0.3

Storage temperature

-40

+125

°C

(All grounds = 0 V, all voltages with respect to 0 V)

Parameter

Symbol

Min

Typ

Max

Unit

Power Supplies

RVDD
CVDD

VDD_PLL

VDD_ADC

3.0

1.65
1.65

3.0

3.3

1.80
1.80

3.3

3.6

1.94
1.94

3.6

V
V
V
V

Operating Ambient Temperature - Commercial

+25

+70

°C

Operating Ambient Temperature - Industrial

-40

+25

+85

°C

Processor Clock Speed - Commercial

FCLK

166

MHz

Processor Clock Speed - Industrial

FCLK

166

MHz

System Clock Speed - Commercial

HCLK

MHz

System Clock Speed - Industrial

HCLK

MHz

DS636PP5

EP9301
Entry Level ARM9 System-on-Chip Processor

DC Characteristics

Note:

4. For open drain pins, high level output voltage is dependent on the external load.
5. All inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper operation (See

Table Q on

page 38

). If an input is not driven, it should be tied to power or ground, depending on the particular function. If an I/O pin is not

driven and programmed as an input, it should be tied to power or ground through its own resistor.

= 0 to 70° C; CVDD = VDD_PLL = 1.8; RVDD = 3.3 V;

All grounds = 0 V; all voltages with respect to 0 V unless otherwise noted)

Parameter

Symbol

Min

Max

Unit

High level output voltage

Iout = -4 mA

(Note 4)

0.85

RVDD

Low level output voltage

Iout = 4 mA

0.15

RVDD

High level input voltage

(Note 5)

0.65

RVDD

VDD + 0.3

Low level input voltage

(Note 5)

0.3

0.35

RVDD

High level leakage current

Vin = 3.3 V

(Note 5)

µA

Low level leakage current

Vin = 0

(Note 5)

-10

µA

Parameter

Min

Typ

Max

Unit

Power Supply Pins (Outputs Unloaded), 25° C

Power Supply Current:

CVDD / VDD_PLL Total
RVDD

-
-

180

230

mA
mA

Low-Power Mode Supply Current

CVDD / VDD_PLL Total
RVDD

-
-

1.0

3.5

mA
mA

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

Timings

Timing Diagram Conventions

This data sheet contains one or more timing diagrams. The following key explains the components used in these
diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached
unless specifically stated.

Figure 1. Timing Diagram Drawing Key

Timing Conditions

Unless specified otherwise, the following conditions are true for all timing measurements.

· T

= 0 to 70° C

· CVDD = VDD_PLL = 1.8V

· RVDD = 3.3 V

· All grounds = 0 V

· Logic 0 = 0 V, Logic 1 = 3.3 V

· Output loading = 50 pF

· Timing reference levels = 1.5 V

· The Processor Bus Clock (HCLK) is programmable and is set by the user. The frequency is typically between

33 MHz and 100 MHz (92 MHz for industrial conditions).

Clock

High to Low

High/Low to High

Bus Change

Bus Valid

Undefined/Invalid

Valid Bus to Tristate

Bus/Signal Omission

DS636PP5

EP9301
Entry Level ARM9 System-on-Chip Processor

Memory Interface

SDRAM Load Mode Register Cycle

Figure 2

through

Figure 5

define the timings associated with all phases of the SDRAM. The following table contains the

values for the timings of each of the SDRAM modes.

Parameter

Symbol

Min

Typ

Max

Unit

SDCLK high time

clk_high

HCLK

) / 2

SDCLK low time

clk_low

HCLK

) / 2

SDCLK rise/fall time

clkrf

Signal delay from SDCLK rising edge time

Signal hold from SDCLK rising edge time

DQMn delay from SDCLK rising edge time

DQd

DQMn hold from SDCLK rising edge time

DQh

DA valid setup to SDCLK rising edge time

DAs

DA valid hold from SDCLK rising edge time

DAh

Figure 2. SDRAM Load Mode Register Cycle Timing Measurement

SDCLK

SDCSn

RASn

CASn

SDWEn

DQMn

OP-Code

clk_high

clk_low

clkrf

DS636PP5

EP9301
Entry Level ARM9 System-on-Chip Processor

Static Memory 32-bit Read on 8-bit External Bus

Parameter

Symbol

Min

Typ

Max

Unit

AD setup to CSn assert time

ADs

HCLK

CSn assert to Address transition time

AD1

HCLK

(WST1 + 1)

Address assert time

AD2

HCLK

(WST1 + 1)

AD transition to CSn deassert time

AD3

HCLK

(WST1 + 2)

AD hold from CSn deassert time

ADh

HCLK

RDn assert time

RDpwL

HCLK

WST1 + 5)

CSn to RDn delay time

RDd

CSn assert to DQMn assert delay time

DQMd

DA setup to AD transition time

DAs1

DA setup to RDn deassert time

DAs2

HCLK

DA hold from AD transition time

DAh1

DA hold from RDn deassert time

DAh2

Figure 6. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement

CSn

WRn

RDn

DQMn

ADs

AD1

AD2

DAs1

RDd

DAh1

DAs1

DAs2

DAh2

ADh

WAIT

RDd

DQMd

AD3

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

Static Memory 32-bit Write on 8-bit External Bus

Parameter

Symbol

Min

Typ

Max

Unit

AD setup to WRn assert time

ADs

HCLK

WRn/DQMn deassert to AD transition time

ADd

HCLK

AD hold from WRn deassert time

ADh

HCLK

CSn hold from WRn deassert time

CSh

CSn to WRn assert delay time

WRd

WRn assert time

WRpwL

HCLK

(WST1 + 1)

WRn deassert time

WRpwH

HCLK

2) + 14

CSn to DQMn assert delay time

DQMd

DQMn assert time

DQMpwL

HCLK

(WST1 + 1)

DQMn deassert time

DQMpwH

HCLK

2) + 7

WRn / DQMn deassert to DA transition time

DAh

HCLK

WRn / DQMn assert to DA valid time

DAV

Figure 7. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement

CSn

WRn

RDn

DQMn

ADs

WRd

DQMd

WRpwL

DAh

WRpwH

ADd

CSh

ADh

DQMpwL

DQMpwH

WRpwL

WRpwH

WRpwL

WRpwH

DQMpwL

DQMpwH

DQMpwL

DQMpwH

DAh

ADd

WAIT

DAV

DS636PP5

EP9301
Entry Level ARM9 System-on-Chip Processor

Static Memory 32-bit Read on 16-bit External Bus

Parameter

Symbol

Min

Typ

Max

Unit

AD setup to CSn assert time

ADs

HCLK

CSn assert to AD transition time

ADd1

HCLK

(WST1 + 1)

AD transition to CSn deassert time

ADd2

HCLK

(WST1 + 2)

AD hold from CSn deassert time

ADh

HCLK

RDn assert time

RDpwL

HCLK

((2

WST1) + 3)

CSn to RDn delay time

RDd

CSn assert to DQMn assert delay time

DQMd

DA setup to AD transition time

DAs1

DA to RDn deassert time

DAs2

HCLK

+ 12

DA hold from AD transition time

DAh1

DA hold from RDn deassert time

DAh2

Figure 8. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement

CSn

WRn

RDn

DQMn

RDpwl

ADd1

RDh

DQMh

DAh2

DAs1

DAh1

DAs2

WAIT

ADs

RDd

DQMd

ADh

ADd2

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

Static Memory 32-bit Write on 16-bit External Bus

Parameter

Symbol

Min

Typ

Max

Unit

AD setup to WRn assert time

ADs

HCLK

WRn/DQMn deassert to AD transition time

ADd

HCLK

+ 6

AD hold from WRn deassert time

ADh

HCLK

× 2

CSn hold from WRn deassert time

CSh

CSn to WRn assert delay time

WRd

WRn assert time

WRpwL

HCLK

× (WST1 + 1)

WRn deassert time

WRpwH

HCLK

× 2) + 14

CSn to DQMn assert delay time

DQMd

DQMn assert time

DQMpwL

HCLK

× (WST1 + 1)

DQMn deassert time

DQMpwH

HCLK

× 2) + 7

WRn / DQMn deassert to DA transition time

DAh1

HCLK

WRn / DQMn assert to DA valid time

DAV

Figure 9. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement

CSn

WRn

RDn

DQMn

ADs

WRd

WRpwL

DAh

ADd

WRpwH

DQMd

ADh

DAh

WRpwL

DQpwL

DQpwH

DQpwL

WAIT

CSh

DAV

DS636PP5

EP9301
Entry Level ARM9 System-on-Chip Processor

Static Memory Burst Read Cycle

Note:

These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.

Parameter

Symbol

Min

Typ

Max

Unit

CSn assert to Address 1 transition time

ADd1

HCLK

(WST1 + 1)

Address assert time

ADd2

HCLK

(WST2 + 1)

AD transition to CSn deassert time

ADd3

HCLK

(WST1 + 2)

AD hold from CSn deassert time

ADh

HCLK

CSn to RDn delay time

RDd

CSn to DQMn assert delay time

DQMd

DA setup to AD transition time

DAs1

DA setup to CSn deassert time

DAs2

HCLK

+ 12

DA hold from AD transition time

DAh1

DA hold from RDn deassert time

DAh2

Figure 10. Static Memory Burst Read Cycle Timing Measurement

CSn

WRn

RDn

DQMn

ADd1

ADd2

RDd

DQMd

DAs1

DAh1

DAs1

DAh1

DAs1

DAh1

DAs2

DAh2

ADh

WAIT

ADd3

ADs

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

Static Memory Burst Write Cycle

Note:

These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.

Parameter

Symbol

Min

Typ

Max

Unit

AD setup to WRn assert time

ADs

HCLK

AD hold from WRn deassert time

ADh

HCLK

WRN/DQMn deassert to AD transition time

ADd

HCLK

+ 6

CSn hold from WRn deassert time

CSh

CSn to WRn assert delay time

WRd

CSn to DQMn assert delay time

DQMd

DQMn assert time

DQpwL

HCLK

(WST1 + 1)

DQMn deassert time

DQpwH

HCLK

2) + 14

WRn assert time

WRpwL

HCLK

(WST1 + 11)

WRn deassert time

WRpwH

HCLK

2) + 7

WRn/DQMn deassert to DA transition time

DAh

HCLK

WRn/DQMn assert to DA valid time

DAv

Figure 11. Static Memory Burst Write Cycle Timing Measurement

CSn

WRn

DQMn

WAIT

ADs

ADd

WRpwL

DQpwL

DQpwH

WRpwH

DAv

DAh

WRd

DQMd

CSh

ADh

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

Ethernet MAC Interface

STA - Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer

(PHY) interface to the wireless medium.

PHY - Ethernet physical layer interface.

Parameter

Symbol

Min

Typ

Max

Unit

10 Mbit

mode

100 Mbit

mode

10 Mbit

mode

100 Mbit

mode

10 Mbit

mode

100 Mbit

mode

TXCLK cycle time

TX_per

400

TXCLK high time

TX_high

140

200

260

TXCLK low time

TX_low

140

200

260

TXCLK to signal transition delay time

TXd

TXCLK rise/fall time

TXrf

RXCLK cycle time

RX_per

400

RXCLK high time

RX_high

140

200

260

RXCLK low time

RX_low

140

200

260

RXDVAL / RXERR setup time

RXs

RXDVAL / RXERR hold time

RXh

RXCLK rise/fall time

RXrf

MDC cycle time

MDC_per

400

MDC high time

MDC_high

160

MDC low time

MDC_low

160

MDC rise/fall time

MDCrf

MDIO setup time (STA sourced)

MDIOs

MDIO hold time (STA sourced)

MDIOh

MDC to MDIO signal transition delay time
(PHY sourced)

MDIOd

300

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

Audio Interface

Note:

The tspix_clk is programmable by the user.

Texas Instruments' Synchronous Serial Format

Microwire

The following table contains the values for the timings of each of the SPI modes.

Parameter

Symbol

Min

Typ

Max

Unit

SCLK cycle time

clk_per

tspix_clk

SCLK high time

clk_high

(tspix_clk) / 2

SCLK low time

clk_low

(tspix_clk) / 2

SCLK rise/fall time

clkrf

Data from master valid delay time

DMd

Data from master setup time

DMs

Data from master hold time

DMh

Data from slave setup time

DSs

Data from slave hold time

DSh

Figure 16. TI Single Transfer Timing Measurement

Figure 17. Microwire Frame Format, Single Transfer

SCLK

SFRM

SSPTXD/

SSPRXD

4 to 16 bits

MSB

LSB

clk_per

clk_low

clk_high

clkrf

SCLK

SFRM

SSPTXD

SSPRXD

MSB

LSB

4 to 16 bits output data

clkrf

clk_high

clk_low

clk_per

MSB

LSB

8-bit control

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

Inter-IC Sound - I

Note:

i2s_clk

is programmable by the user.

Parameter

Symbol

Min

Typ

Max

Unit

SCLK cycle time

clk_per

i2s_clk

SCLK high time

clk_high

i2s_clk

) / 2

SCLK low time

clk_low

i2s_clk

) / 2

SCLK rise/fall time

clkrf

SCLK to LRCLK assert delay time

LRd

Hold between SCLK assert then LRCLK deassert
or
Hold between LRCLK deassert then SCLK assert

LRh

SDI to SCLK deassert setup time

SDIs

SDI from SCLK deassert hold time

SDIh

SCLK assert to SDO delay time

SDOd

SDO from SCLK assert hold time

SDOh

Figure 19. Inter-IC Sound (I

S) Timing Measurement

SCLK

LRCLK

SDI

LRd

LRh

SDIh

clk_high

SDIs

clk_low

clk_per

clkrf

SDOh

SDO

SDOd

DS636PP5

EP9301
Entry Level ARM9 System-on-Chip Processor

AC'97

Parameter

Symbol

Min

Typ

Max

Unit

ABITCLK input cycle time

clk_per

81.4

ABITCLK input high time

clk_high

ABITCLK input low time

clk_low

ABITCLK input rise/fall time

clkrf

ASDI setup to ABITCLK falling

ASDI hold after ABITCLK falling

ASDI input rise/fall time

rfin

ABITCLK rising to ASDO / ASYNC valid, C

= 55 pF

ASYNC / ASDO rise/fall time, C

= 55 pF

rfout

Figure 20. AC `97 Configuration Timing Measurement

ABITCLK

ASDI

ASDO

ASYNC

rfout

rfin

rfout

clkrf

clk_high

clk_low

clk_per

clkrf

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

ADC

Note:

ADIV refers to bit 16 in the KeyTchClkDiv register.
ADIV = 0 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 4.
ADIV = 1 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 16.

Using the ADC:

This ADC has a state-machine based conversion engine that automates the conversion process. The initiator for a
conversion is the read access of the TSXYResult register by the CPU. The data returned from reading this register
contains the result as well as the status bit indicating the state of the ADC. However, this peripheral requires a delay
between each successful conversion and the issue of the next conversion command, or else the returned value of
successive samples may not reflect the analog input. Since the state of the ADC state machine is returned through the
same channel used to initiate the conversion process, there must be a delay inserted after every complete conversion.
Note that reading TSXYResult during a conversion will not affect the result of the ongoing process.

The following is a recommended procedure for safely polling the ADC from software:

1. Read the TSXYResult register into a local variable to initiate a conversion.
2. If the value of bit 31 of the local variable is '0' then repeat step 1.
3. Delay long enough to meet the maximum sample rate as shown above.
4. Mask the local variable with 0xFFFF to remove extraneous data.
5. If signed mode is used, do a sign extend of the lower halfword.
6. Return the sampled value.

Parameter

Comment

Value

Units

Resolution

No missing codes

Range of 0 to 3.3 V

50K counts (approximate)

Integral non-linearity

0.01%

Offset error

±15

Full scale error

0.2%

Maximum sample rate

ADIV = 0
ADIV = 1

3750

925

Samples per second
Samples per second

Channel switch settling time

ADIV = 0
ADIV = 1

500

Noise (RMS) - typical

120

Figure 21. ADC Transfer Function

Vref/2

Vref

0000

FFFF

61A8

9E58

A/D Converter Transfer Function

(approximately ±25,000 counts)

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

208 Pin LQFP Package Outline

2.19

208-Pin LQFP (28

× 28 × 1.40-mm Body)

NOTES:
1) Dimensions are in millimeters, and controlling dimension is millimeter.

2) Package body dimensions do not include mold protrusion, which is 0.25 mm (0.010 in).

3) Pin 1 identification may be either ink dot or dimple.

4) Package top dimensions can be smaller than bottom dimensions by 0.20 mm (0.008 in).

5) The `lead width with plating' dimension does not include a total allowable dambar protrusion of 0.08 mm

(at maximum material condition).

6) Ejector pin marks in molding are present on every package.

7) Drawing above does not reflect exact package pin count.

Pin 1 Indicator

29.60 (1.165)
30.40 (1.197)

0.17 (0.007)
0.27 (0.011)

27.80 (1.094)
28.20 (1.110)

0.50

(0.0197)

BSC

29.60 (1.165)
30.40 (1.197)

27.80 (1.094)
28.20 (1.110)

1.35 (0.053)
1.45 (0.057)

° MIN

° MAX

0.09 (0.004)
0.20 (0.008)

1.40 (0.055)

0.45 (0.018)
0.75 (0.030)

0.05 (0.002)

1.00 (0.039) BSC

Pin 1

Pin 208

1.60 (0.063)

0.15 (0.006)

DS636PP5

EP9301
Entry Level ARM9 System-on-Chip Processor

208 Pin LQFP Pinout

The following table shows the 208 pin LQFP pinout.

· VDD_core is CVDD.
· VDD_ring is RVDD.
· NC means that the pin is not connected.

Pin List

The following Low-Profile Quad Flat Pack (LQFP) pin assignment table is sorted in order of pin.

Table P. Pin List in Numerical Order by Pin Number

Pin

Number

Pin

Name

Pin

Number

Pin

Name

Pin

Number

Pin

Name

Pin

Number

Pin

Name

Pin

Number

Pin

Name

Pin

Number

Pin

Name

CSn[7]

AD[5]

AD[9]

106

USBp[0]

141

EGPIO[10]

176

TXEN

CSn[6]

DA[12]

DA[1]

107

ABITCLK

142

EGPIO[9]

177

MIITXD[0]

CSn[3]

AD[4]

AD[8]

108

CTSn

143

EGPIO[8]

178

MIITXD[1]

CSn[2]

DA[11]

DA[0]

109

RXD[0]

144

EGPIO[7]

179

MIITXD[2]

CSn[1]

AD[3]

DSRn

110

RXD[1]

145

EGPIO[6]

180

MIITXD[3]

AD[25]

vdd_ring

DTRn

111

vdd_ring

146

EGPIO[5]

181

TXCLK

vdd_ring

gnd_ring

TCK

112

gnd_ring

147

EGPIO[4]

182

RXERR

gnd_ring

DA[10]

TDI

113

TXD[0]

148

EGPIO[3]

183

RXDVAL

AD[24]

AD[2]

TDO

114

TXD[1]

149

gnd_ring

184

MIIRXD[0]

SDCLK

DA[9]

TMS

115

CGPIO[0]

150

vdd_ring

185

MIIRXD[1]

AD[23]

AD[1]

vdd_ring

116

gnd_core

151

EGPIO[2]

186

MIIRXD[2]

vdd_core

DA[8]

gnd_ring

117

PLL_GND

152

EGPIO[1]

187

gnd_ring

gnd_core

AD[0]

BOOT[1]

118

XTALI

153

EGPIO[0]

188

vdd_ring

SDWEn

vdd_ring

BOOT[0]

119

XTALO

154

ARSTn

189

MIIRXD[3]

SDCSn[3]

gnd_ring

120

PLL_VDD

155

TRSTn

190

RXCLK

SDCSn[2]

121

vdd_core

156

ASDI

191

MDIO

SDCSn[1]

EECLK

122

gnd_ring

157

USBm[2]

192

MDC

SDCSn[0]

vdd_ring

EEDAT

123

vdd_ring

158

USBp[2]

193

RDn

vdd_ring

gnd_ring

ASYNC

124

RSTOn

159

WAITn

194

WRn

gnd_ring

AD[15]

vdd_core

125

PRSTn

160

EGPIO[15]

195

AD[16]

RASn

DA[7]

gnd_core

126

CSn[0]

161

gnd_ring

196

AD[17]

CASn

vdd_core

ASDO

127

gnd_core

162

vdd_ring

197

gnd_core

DQMn[1]

gnd_core

SCLK1

128

vdd_core

163

EGPIO[14]

198

vdd_core

DQMn[0]

AD[14]

SFRM1

129

gnd_ring

164

EGPIO[13]

199

HGPIO[2]

AD[22]

DA[6]

SSPRX1

130

vdd_ring

165

EGPIO[12]

200

HGPIO[3]

AD[21]

AD[13]

SSPTX1

131

ADC[4]

166

gnd_core

201

HGPIO[4]

vdd_ring

DA[5]

GRLED

132

ADC[3]

167

vdd_core

202

HGPIO[5]

gnd_ring

AD[12]

RDLED

133

ADC[2]

168

FGPIO[3]

203

gnd_ring

DA[15]

DA[4]

vdd_ring

134

ADC[1]

169

FGPIO[2]

204

vdd_ring

AD[7]

AD[11]

100

gnd_ring

135

ADC[0]

170

FGPIO[1]

205

AD[18]

DA[14]

vdd_ring

101

INT[3]

136

ADC_VDD

171

gnd_ring

206

AD[19]

AD[6]

gnd_ring

102

INT[1]

137

RTCXTALI

172

vdd_ring

207

AD[20]

DA[13]

DA[3]

103

INT[0]

138

RTCXTALO

173

CLD

208

SDCLKEN

vdd_core

AD[10]

104

RTSn

139

ADC_GND

174

CRS

gnd_core

DA[2]

105

USBm[0]

140

EGPIO[11]

175

TXERR

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

The following section focuses on the EP9301 pin signals
from two viewpoints - the pin usage and pad
characteristics, and the pin multiplexing usage. The first
table (

Table Q

) is a summary of all the EP9301 pin

signals. The second table (

Table R

) illustrates the pin

signal multiplexing and configuration options.

Table Q

is a summary of the EP9301 pin signals, which

illustrates the pad type and pad pull type (if any). The
symbols used in the table are defined as follows. (Note: A
blank box means Not Applicable (NA) or, for Pull Type,
No Pull (NP).)

Under the Pad Type column:

· A - Analog pad
· P - Power pad
· G - Ground pad
· I - Pin is an input only
· I/O - Pin is input/output
· 4mA - Pin is a 4mA output driver
· 8mA - Pin is an 8mA output driver
· 12mA - Pin is an 12mA output driver
See the text description for additional information about
bi-directional pins.

Under the Pull Type Column:

· PU - Resistor is a pull up to the RVDD supply
· PD - Resistor is a pull down to the RGND supply

DS636PP5

EP9301
Entry Level ARM9 System-on-Chip Processor

Table Q. Pin Description

Pin Name

Block

Pad

Type

Pull

Type

Description

TCK

JTAG

JTAG clock in

TDI

JTAG

JTAG data in

TDO

JTAG

4ma

JTAG data out

TMS

JTAG

JTAG test mode select

TRSTn

JTAG

JTAG reset

BOOT[1:0]

System

Boot mode select in

XTALI

PLL

Main oscillator input

XTALO

PLL

Main oscillator output

VDD_PLL

PLL

Main oscillator power, 1.8V

GND_PLL

PLL

Main oscillator ground

RTCXTALI

RTC

RTC oscillator input

RTCXTALO

RTC

RTC oscillator output

WRn

EBUS

4ma

SRAM Write strobe out

RDn

EBUS

4ma

SRAM Read / OE strobe out

WAITn

EBUS

SRAM Wait in

AD[25:0]

EBUS

8ma

Shared Address bus out

DA[15:0]

EBUS

8ma

Shared Data bus in/out

CSn[3:0]

EBUS

4ma

Chip select out

CSn[7:6]

EBUS

4ma

Chip select out

DQMn[1:0]

EBUS

8ma

Shared data mask out

SDCLK

SDRAM

8ma

SDRAM clock out

SDCLKEN

SDRAM

8ma

SDRAM clock enable out

SDCSn[3:0]

SDRAM

4ma

SDRAM chip selects out

RASn

SDRAM

8ma

SDRAM RAS out

CASn

SDRAM

8ma

SDRAM CAS out

SDWEn

SDRAM

8ma

SDRAM write enable out

ADC[4:0]

ADC

External Analog Measurement Input

VDD_ADC

ADC

ADC power, 3.3V

GND_ADC

ADC

ADC ground

USBp[2, 0]

USB

USB positive signals

USBm[2, 0]

USB

USB negative signals

TXD0

UART1

4ma

Transmit out

RXD0

UART1

Receive in

CTSn

UART1

Clear to send / transmit enable

DSRn

UART1

Data set ready / Data Carrier Detect

DTRn

UART1

4ma

Data Terminal Ready output

RTSn

UART1

4ma

Ready to send

TXD1

UART2

4ma

Transmit / IrDA output

RXD1

UART2

Receive / IrDA input

MDC

EMAC

4ma

Management data clock

MDIO

EMAC

4ma

Management data input/output

RXCLK

EMAC

Receive clock in

MIIRXD[3:0]

EMAC

Receive data in

RXDVAL

EMAC

Receive data valid

RXERR

EMAC

Receive data error

TXCLK

EMAC

Transmit clock in

MIITXD[3:0]

EMAC

4ma

Transmit data out

TXEN

EMAC

4ma

Transmit enable

TXERR

EMAC

4ma

Transmit error

CRS

EMAC

Carrier sense

CLD

EMAC

Collision detect

GRLED

LED

12ma

Green LED

RDLED

LED

12ma

Red LED

EECLK

EEPROM

4ma

EEPROM / Two-wire Interface clock

EEDAT

EEPROM

4ma

EEPROM / Two-wire Interface data

ABITCLK

AC97

8ma

AC97 bit clock

ASYNC

AC97

8ma

AC97 frame sync

ASDI

AC97

AC97 Primary input

ASDO

AC97

8ma

AC97 output

ARSTn

AC97

8ma

AC97 reset

SCLK1

SPI1

I/O, 8ma

SPI bit clock

SFRM1

SPI1

I/O, 8ma

SPI Frame Clock

SSPRX1

SPI1

SPI input

SSPTX1

SPI1

8ma

SPI output

INT[3], INT[1:0]

INT

External interrupts

PRSTn

Syscon

Power on reset

RSTOn

Syscon

4ma

User Reset in out - open drain

EGPIO[15:0]

GPIO

I/O, 4ma

Enhanced GPIO

FGPIO[3:1]

GPIO

I/O, 8ma

GPIO on Port F

HGPIO[5:2]

GPIO

I/O, 8ma

GPIO on Port H

CGPIO[0]

GPIO

I/O, 8ma

GPIO on Port C

CVDD

Power

Digital power, 1.8V

RVDD

Power

Digital power, 3.3V

CGND

Ground

Digital ground

RGND

Ground

Digital ground

Table Q. Pin Description (Continued)

Pin Name

Block

Pad

Type

Pull

Type

Description

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

Table R

illustrates the pin signal multiplexing and configuration options.

Table R. Pin Multiplex Usage Information

Physical Pin Name

Description

Multiplex signal name

EGPIO[0]

Ring Indicator Input

EGPIO[1]

1Hz clock monitor

CLK1HZ

EGPIO[3]

HDLC Clock

HDLCCLK1

EGPIO[4]

I2S Transmit Data 1

SDO1

EGPIO[5]

I2S Receive Data 1

SDI1

EGPIO[6]

I2S Transmit Data 2

SDO2

EGPIO[7]

DMA Request 0

DREQ0

EGPIO[8]

DMA Acknowledge 0

DACK0

EGPIO[9]

DMA EOT 0

DEOT0

EGPIO[10]

DMA Request 1

DREQ1

EGPIO[11]

DMA Acknowledge 1

DACK1

EGPIO[12]

DMA EOT 1

DEOT1

EGPIO[13]

I2S Receive Data 2

SDI2

EGPIO[14]

PWM1 Output

PWMOUT1

EGPIO[15]

Device active / present

DASP

ABITCLK

I2S Serial clock

SCLK

ASYNC

I2S Frame Clock

LRCK

ASDO

I2S Transmit Data 0

SDO0

ASDI

I2S Receive Data 0

SDI0

ARSTn

I2S Master clock

MCLK

SCLK1

I2S Serial clock

SCLK

SFRM1

I2S Frame Clock

LRCK

SSPTX1

I2S Transmit Data 0

SDO0

SSPRX1

I2S Receive Data 0

SDI0

DS636PP5

EP9301
Entry Level ARM9 System-on-Chip Processor

Acronyms and Abbreviations

The following tables list abbreviations and acronyms
used in this data sheet.

Units of Measurement

Term

Definition

ADC

Analog-to-Digital Converter

ALT

Alternative

AMBA

Advanced Micro-controller Bus Architecture

ATAPI

ATA Packet Interface

CODEC

COder / DECoder

CRC

Cyclic Redundancy Check

DAC

Digital-to-Analog Converter

DMA

Direct-Memory Access

EEPROM Electronically Erasable Programmable Read Only Memory

EMAC

Ethernet Media Access Controller

EBUS

External Memory Bus

FIFO

First In / First Out

FIQ

Fast Interrupt Request

FLASH

Flash memory

GPIO

General Purpose I/O

HDLC

High-level Data Link Control

I/F

Interface

Inter-IC Sound

Integrated Circuit

ICE

In-Circuit Emulator

IDE

Integrated Drive Electronics

IEEE

Institute of Electronics and Electrical Engineers

IrDA

Infrared Data Association

IRQ

Standard Interrupt Request

ISO

International Standards Organization

JTAG

Joint Test Action Group

LFSR

Linear Feedback Shift Register

MII

Media Independent Interface

MMU

Memory Management Unit

OHCI

Open Host Controller Interface

PHY

Ethernet PHYsical layer interface

PIO

Programmed I/O

RISC

Reduced Instruction Set Computer

SDMI

Secure Digital Music Initiative

SDRAM

Synchronous Dynamic RAM

SPI

Serial Peripheral Interface

SRAM

Static Random Access Memory

STA

Station - Any device that contains an IEEE

802.11

conforming Medium Access Control (MAC) and physical
layer (PHY) interface to the wireless medium

TFT

Thin Film Transistor

TLB

Translation Lookaside Buffer

USB

Universal Serial Bus

Symbol

Unit of Measure

degree Celsius

Hertz = cycle per second

kbps

Kilobits per second

kbyte

Kilobyte

KHz

KiloHertz = 1000 Hz

Mbps

Megabits per second

MHz

MegaHertz = 1,000 KiloHertz

microAmpere = 10

-6

Ampere

microsecond = 1,000 nanoseconds = 10

-6

seconds

milliAmpere = 10

-3

Ampere

millisecond = 1,000 microseconds = 10

-3

seconds

milliWatt = 10

-3

Watts

nanosecond = 10

-9

seconds

picoFarad = 10

-12

Farads

Volt

Watt

Term

Definition

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

ORDERING INFORMATION

The order numbers for the device are:

EP9301-CQ

C to +70

208-pin LQFP

EP9301-CQZ

C to +70

208-pin LQFP

Lead Free

EP9301-IQ

-40

C to +85

208-pin LQFP

EP9301-IQZ

-40

C to +85

208-pin LQFP

Lead Free

EP9301 -- CQZ

Product Line:
Embedded Processor

Part Number

Temperature Range:
C = Commercial

Package Type:
Q = 208 pin, Low Profile Quad Flat Pack (28 mm x 28 mm)

Note:

Go to the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative.

Z = Lead Free

Lead Material:

E = Extended Operating Version

I = Industrial Operating Version

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find one nearest you go to

www.cirrus.com

IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries

("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS

IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that infor-

mation being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including

those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information

as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing

this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights.

Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization

with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or

promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY

OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIR-

CRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE

SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY

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THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY

SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY,

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Cirrus Logic, Cirrus, MaverickCrunch, MaverickKey, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this doc-

ument may be trademarks or service marks of their respective owners.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
Microwire is a trademark of National Semiconductor Corp. National Semiconductor is a registered trademark of National Semiconductor Corp.
Texas Instruments is a registered trademark of Texas Instruments, Inc.
Motorola and SPI are registered trademarks of Motorola, Inc.
LINUX is a registered trademark of Linus Torvalds.

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: EP9301-CQZ