MAR `05

DS515PP7

http://www.cirrus.com

Universal Platform

System-on-chip Processor

EP9312 Data Sheet

FEATURES

· 200-MHz ARM920T Processor

· 16-kbyte Instruction Cache
· 16-kbyte Data Cache
· Linux

, Microsoft

Windows

CE-enabled MMU

· 100-MHz System Bus

· MaverickCrunch

Math Engine

· Floating Point, Integer, and Signal Processing

Instructions

· Optimized for digital music compression and

decompression algorithms.

· Hardware interlocks allow in-line coding.

· MaverickKey

IDs

· 32-bit unique ID can be used for DRM-compliant,

128-bit random ID.

· Integrated Peripheral Interfaces

· 32-bit SDRAM Interface (up to 4 banks)
· 32/16-bit SRAM / FLASH / ROM
· Serial EEPROM Interface
· EIDE (up to 2 devices)
· 1/10/100 Mbps Ethernet MAC
· Three UARTs
· Three-port USB 2.0 Full-speed Host (OHCI)

(12 Mbits per second)

· LCD and Raster Interface
· Touchscreen Interface with ADC

· IrDA Interface
· 8 x 8 Keypad Scanner
· One Serial Peripheral Interface (SPI) Port

· 6-channel or 2-channel Serial Audio Interface (I

· 2-channel, Low-cost Serial Audio Interface (AC'97)
· 2 High-resolution PWMs (16 bits each)

· Internal Peripherals

· 12 Direct Memory Access (DMA) Channels
· Real-time Clock with Software Trim
· Dual PLL controls all clock domains.
· Watchdog Timer
· Two General-purpose 16-bit Timers
· One General-purpose 32-bit Timer
· One 40-bit Debug Timer
· Interrupt Controller
· Boot ROM

· Package

· 352 pin PBGA

MMUNICATIONS P

RTS

US
ER INTERFACE

MEMORY AND STORAGE

Unified

SDRAM I/F

Video/LCD

Controller

(3) USB

Hosts

EIDE

I/F

Ethernet

MAC

Bus

Bridge

Boot

ROM

MaverickLock

DMA w/

CRC

SRAM &

Flash I/F

MaverickCrunch

ARM920T

MMU

D-Cache

16KB

I-Cache

16KB

Processor Bus

Peripheral Bus

Serial
Audio

Interface

Interrupts

& GPIO

Clocks &

Timers

Keypad &

Touch

Screen I/F

(3) UARTs

IrDA

12 CHANNEL

DMA

MaverickKey

DS515PP7

EP9312
Universal Platform SOC Processor

The EP9312 is an ARM920T-based system-on-a-chip
design with a large peripheral set targeted to a variety of
applications:

· Thin client computers for business and home
· Internet radio
· Internet access devices
· Industrial computers
· Specialized terminals
· Point of sale terminals
· Test and measurement equipment
The ARM920T microprocessor core with separate 16-
kbyte, 64-way set-associative instruction and data
caches is augmented by the MaverickCrunchTM co-
processor enabling high-speed floating point
calculations.

MaverickKey

unique hardware programmed IDs are a

solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly

becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.
A high-performance 1/10/100 Mbps Ethernet media
access Controller (EMAC) is included along with external
interfaces to SPI, I

S audio, Raster/LCD, IDE storage

peripherals, keypad, and touchscreen. A three-port USB
2.0 Full-speed Host (OHCI) (12 Mbits per second) and
three UARTs are included as well.
The EP9312 is a high-performance, low-power, RISC-
based, single-chip computer built around an ARM920T
microprocessor core with a maximum operating clock
rate of 200 MHz (184 MHz for industrial conditions). The
ARM core operates from a 1.8 V supply, while the I/O
operates at 3.3 V with power usage between 100 mW
and 750 mW (dependent on speed).

OVERVIEW

Table A. Change History

Revision

Date

Changes

March 2001

Initial Release.

June 2001

Upgrade to revision B silicon.

August 2001

Upgrade to revision C silicon.

May 2003

Upgrade to revision D silicon.

December 2003

Update timing data.

July 2004

Update AC data.
Add ADC data.

Febuary 2005

Update with most-current characterization data.

DS515PP7

EP9312

Universal Platform SOC Processor

Table of Contents

FEATURES .........................................................................................................1
Overview .............................................................................................................2

Processor Core - ARM920T ......................................................................................... 6
MaverickCrunchTM Math Engine .................................................................................. 6
MaverickKeyTM Unique ID ............................................................................................ 6
General Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH) ........................ 6
IDE Interface ................................................................................................................ 7
Ethernet Media Access Controller (MAC) .................................................................... 7
Serial Interfaces (SPI, I2S, and AC '97) ....................................................................... 7
Raster/LCD Interface ................................................................................................... 7
Touch Screen Interface with 12-bit Analog-to-digital Converter (ADC) ........................ 8
64-Key Keypad Interface ............................................................................................. 8
Universal Asynchronous Receiver/Transmitters (UARTs) ............................................ 8
Triple-port USB Host .................................................................................................... 9
Two-Wire Interface ....................................................................................................... 9
Real-time Clock with Software Trim ............................................................................. 9
PLL and Clocking ......................................................................................................... 9
Timers ........................................................................................................................ 10
Interrupt Controller ..................................................................................................... 10
Dual LED Drivers ....................................................................................................... 10
General Purpose Input/Output (GPIO) ....................................................................... 10
Reset and Power Management ................................................................................. 10
Hardware Debug Interface ..........................................................................................11
12-Channel DMA Controller ........................................................................................11
Internal Boot ROM ......................................................................................................11

Electrical Specifications .................................................................................12

Absolute Maximum Ratings ....................................................................................... 12
Recommended Operating Conditions ........................................................................ 12
DC Characteristics ..................................................................................................... 13

Timings .............................................................................................................14

Memory Interface ....................................................................................................... 15
IDE Interface .............................................................................................................. 30
Ethernet MAC Interface ............................................................................................ 43
Audio Interface ........................................................................................................... 45
AC'97 ........................................................................................................................ 49
LCD Interface ............................................................................................................ 50
ADC ........................................................................................................................... 51
JTAG .......................................................................................................................... 52

352 Pin BGA Package Outline .......................................................................53

352-Ball PBGA Diagram .................................................................................. 53
352 Pin BGA Pinout (Bottom View) ........................................................................... 54

Acronyms and Abbreviations ........................................................................61
Units of Measurement .....................................................................................61
Ordering Information ......................................................................................62

DS515PP7

EP9312
Universal Platform SOC Processor

List of Figures

Figure 1. Timing Diagram Drawing Key .................................................................................14
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement ..................................... 15
Figure 3. SDRAM Burst Read Cycle Timing Measurement ................................................... 16
Figure 4. SDRAM Burst Write Cycle Timing Measurement ................................................... 17
Figure 5. SDRAM Auto Refresh Cycle Timing Measurement ................................................ 18
Figure 6. Static Memory Single Word Read Cycle Timing Measurement .............................. 19
Figure 7. Static Memory Single Word Write Cycle Timing Measurement .............................. 20
Figure 8. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement .................... 21
Figure 9. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement .................... 22
Figure 10. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement ................ 23
Figure 11. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement ................ 24
Figure 12. Static Memory Burst Read Cycle Timing Measurement .......................................25
Figure 13. Static Memory Burst Write Cycle Timing Measurement .......................................26
Figure 14. Static Memory Single Read Wait Cycle Timing Measurement ............................. 27
Figure 15. Static Memory Single Write Wait Cycle Timing Measurement .............................. 28
Figure 16. Static Memory Turnaround Cycle Timing Measurement .......................................29
Figure 17. Register Transfer to/from Device .......................................................................... 31
Figure 18. PIO Data Transfer to/from Device ......................................................................... 33
Figure 19. Initiating an Ultra DMA data-in Burst ..................................................................... 35
Figure 20. Sustained Ultra DMA data-in Burst ....................................................................... 36
Figure 21. Host Pausing an Ultra DMA data-in Burst ............................................................. 36
Figure 22. Device Terminating an Ultra DMA data-in Burst ................................................... 37
Figure 23. Host Terminating an Ultra DMA data-in Burst ....................................................... 38
Figure 24. Initiating an Ultra DMA data-out Burst .................................................................. 39
Figure 25. Sustained Ultra DMA data-out Burst ..................................................................... 40
Figure 26. Device Pausing an Ultra DMA data-out Burst ....................................................... 40
Figure 27. Host Terminating an Ultra DMA data-out Burst ....................................................41
Figure 28. Device Terminating an Ultra DMA data-out Burst ................................................. 42
Figure 29. Ethernet MAC Timing Measurement ..................................................................... 44
Figure 30. TI Single Transfer Timing Measurement ............................................................... 46
Figure 31. Microwire Frame Format, Single Transfer ............................................................ 46
Figure 32. SPI Format with SPH=1 Timing Measurement ..................................................... 47
Figure 33. Inter-IC Sound (I2S) Timing Measurement ........................................................... 48
Figure 34. AC `97 Configuration Timing Measurement .......................................................... 49
Figure 35. LCD Timing Measurement .................................................................................... 50
Figure 36. ADC Transfer Function ......................................................................................... 51
Figure 37. JTAG Timing Measurement .................................................................................. 52
Figure 38. 352 Pin PBGA Pin Diagram .................................................................................. 53
Figure 40. 352 PIN BGA PINOUT ................................................................................... 55

DS515PP7

EP9312

Universal Platform SOC Processor

List of Tables

Table A. Change History .......................................................................................................... 2
Table B. General Purpose Memory Interface Pin Assignments .............................................. 6
Table C. IDE Interface Pin Assignments .................................................................................. 7
Table D. Ethernet Media Access Controller Pin Assignments ................................................. 7
Table E. Audio Interfaces Pin Assignment .............................................................................. 7
Table F. LCD Interface Pin Assignments ................................................................................ 8
Table G. Touch Screen Interface with 12-bit Analog-to-Digital Converter Pin Assignments ... 8
Table H. 64-Key Keypad Interface Pin Assignments ............................................................... 8
Table I. Universal Asynchronous Receiver/Transmitters Pin Assignments ............................ 9
Table J. Triple Port USB Host Pin Assignments ..................................................................... 9
Table K. Two-Wire Port with EEPROM Support Pin Assignments .......................................... 9
Table L. Real-Time Clock with Pin Assignments ..................................................................... 9
Table M.PLL and Clocking Pin Assignments ........................................................................ 10
Table N. Interrupt Controller Pin Assignment ........................................................................ 10
Table O. Dual LED Pin Assignments ..................................................................................... 10
Table P. General Purpose Input/Output Pin Assignment ...................................................... 10
Table Q. Reset and Power Management Pin Assignments ................................................... 10
Table R. Hardware Debug Interface ...................................................................................... 11
Table R. 352 Pin Diagram Dimensions .................................................................................. 54
Table S. Pin Descriptions ..................................................................................................... 59
Table T. Pin Multiplex Usage Information ............................................................................. 60

DS515PP7

EP9312
Universal Platform SOC Processor

Processor Core - ARM920T

The ARM920T is a Harvard architecture processor with
separate 16-kbyte instruction and data caches with an 8-
word line length but a unified memory. The processor
utilizes a five-stage pipeline consisting of fetch, decode,
execute, memory, and write stages. Key features include:

· ARM (32-bit) and Thumb (16-bit compressed)

Instruction Sets

· 32-bit Advanced Microcontroller Bus Architecture

(AMBA)

· 16-kbyte Instruction Cache with lockdown
· 16-kbyte Data Cache (programmable write-through or

write-back) with Lockdown

· MMU for Linux

, Microsoft

Windows

CE, and other

operating systems

· Translation Look Aside Buffers with 64 Data and 64

Instruction Entries

· Programmable Page Sizes of 1 Mbyte, 64 kbyte,

4 kbyte, and 1 kbyte

· Independent lockdown of TLB Entries

MaverickCrunch

Math Engine

The MaverickCrunch Engine is a mixed-mode
coprocessor designed primarily to accelerate the math
processing required to rapidly encode digital audio
formats. It accelerates single- and double-precision
integer and floating point operations plus an integer
multiply-accumulate (MAC) instruction that is
considerably faster than the ARM920T's native MAC
instruction. The ARM920T coprocessor interface is
utilized thereby sharing its memory interface and
instruction stream. Hardware forwarding and interlock
allows the ARM to handle looping and addressing while
MaverickCrunch handles computation. Features include:

· IEEE-754 single and double-precision floating point
· 32 / 64-bit integer
· Add / multiply / compare
· Integer MAC 32-bit input with 72-bit accumulate
· Integer Shifts
· Floating point to/from integer conversion
· Sixteen 64-bit register files
· Four 72-bit accumulators

MaverickKey

Unique ID

MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs

provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.

Both a specific 32-bit ID as well as a 128-bit random ID
are programmed into the EP9312 through the use of
laser probing technology. These IDs can then be used to
match secure copyrighted content with the ID of the
target device the EP9312 is powering, and then deliver
the copyrighted information over a secure connection. In
addition, secure transactions can benefit by also
matching device IDs to server IDs. MaverickKey IDs
provide a level of hardware security required for today's
Internet appliances.

General Purpose Memory Interface (SDRAM,
SRAM, ROM, FLASH)

The EP9312 features a unified memory address model
where all memory devices are accessed over a common
address/data bus. A separate internal port is dedicated to
the read-only Raster/LCD refresh engine, while the rest
of the memory accesses are performed via the Processor
bus. The SRAM memory controller supports 8, 16 and
32-bit devices and accommodates an internal boot ROM
concurrently with 32-bit SDRAM memory.

· 1 to 4 banks of 32-bit, 66- or 100-MHz SDRAM
· One internal port dedicated to the Raster/LCD

Refresh Engine (Read Only)

· Address and data bus shared between SDRAM,

SRAM, ROM, and FLASH memory

· NOR FLASH memory supported

Table B. General Purpose Memory Interface Pin Assignments

Pin Mnemonic

Pin Description

SDCLK

SDRAM Clock

SDCLKEN

SDRAM Clock Enable

SDCSn[3:0]

SDRAM Chip Selects 3-0

RASn

SDRAM RAS

CASn

SDRAM CAS

SDWEn

SDRAM Write Enable

CSn[7:6] and CSn[3:0]

Chip Selects 7, 6, 3, 2, 1, 0

AD[25:0]

Address Bus 25-0

DA[31:0]

Data Bus 31-0

DQMn[3:0]

SDRAM Output Enables / Data Masks

WRn

SRAM Write Strobe

RDn

SRAM Read / OE Strobe

WAITn

SRAM Wait Input

DS515PP7

EP9312

Universal Platform SOC Processor

IDE Interface

The IDE Interface provides an industry-standard
connection to two AT Advanced Packet Interface (ATAPI)
compliant devices. The IDE port will attach to a master
and a slave device. The internal DMA controller performs
all data transfers using the Multiword DMA and Ultra
DMA modes. The interface supports the following
operating modes:

· PIO Modes 0 thru 4
· Ultra DMA Modes 0 thru 3

Ethernet Media Access Controller (MAC)

The MAC subsystem is compliant with the ISO/TEC
802.3 topology for a single shared medium with several
stations. Multiple MII-compliant PHYs are supported.
Features include:

· Supports 1/10/100 Mbps transfer rates for home /

small-business / large-business applications

· Interfaces to an off-chip PHY through industry

standard Media Independent Interface (MII)

Serial Interfaces (SPI, I

S, and AC '97)

The SPI port can be configured as a master or a slave,
supporting the National Semiconductor

, Motorola

, and

Texas Instruments

signaling protocols.

The AC'97 port supports multiple codecs for multichannel
audio output with a single stereo input. Three I

S ports

can be configured to support six-channel, 24-bit audio.

These ports are multiplexed so that I

S port 0 will take

over either the AC'97 pins or the SPI pins. The second
and third I2S ports' serial input and serial output pins are
multiplexed with EGPIO[4,5,6,13]. The clocks supplied in
the first I2S port are also used for the second and third
I2S ports.

· Normal Mode: One SPI Port and one AC'97 Port

· I

S on SSP Mode: One AC'97 Port and up to three I

Ports

· I

S on AC'97 Mode: One SPI Port and up to three I

Ports

Raster/LCD Interface

The Raster/LCD interface provides data and interface
signals for a variety of display types. It features fully
programmable video interface timing for non-interlaced
flat panel or dual scan displays. Resolutions up to
1024 x 768 are supported from a unified SDRAM based
frame buffer. A 16-bit PWM provides control for LCD
panel contrast.

Table C. IDE Interface Pin Assignments

Pin Mnemonic

Pin Description

DD[15-0]

IDE Data bus

IDEDA[2-0]

IDE Device address

IDECSn[0,1]

IDE Chip Select 0 and 1

DIORn

IDE Read Strobe

DIOWn

IDE Write Strobe

DMACKn

IDE DMA acknowledge

Table D. Ethernet Media Access Controller Pin Assignments

Pin Mnemonic

Pin Description

MDC

Management Data Clock

MDIO

Management Data I/O

RXCLK

Receive Clock

MIIRXD[3:0]

Receive Data

RXDVAL

Receive Data Valid

RXERR

Receive Data Error

TXCLK

Transmit Clock

MIITXD[3:0]

Transmit Data

TXEN

Transmit Enable

TXERR

Transmit Error

CRS

Carrier Sense

CLD

Collision Detect

Table E. Audio Interfaces Pin Assignment

Pin

Name

Normal Mode

I2S on SSP

Mode

I2S on AC'97

Mode

Pin

Description

Pin Description Pin Description

SCLK1

SPI Bit Clock

I2S Serial Clock

SPI Bit Clock

SFRM1

SPI Frame Clock I2S Frame Clock

SPI Frame Clock

SSPRX1 SPI Serial Input

I2S Serial Input

SPI Serial Input

SSPTX1

SPI Serial
Output

I2S Serial Output

SPI Serial Output

(No I2S Master
Clock)

ARSTn

AC'97 Reset

I2S Master Clock

ABITCLK AC'97 Bit Clock

AC'97 Bit Clock

I2S Serial Clock

ASYNC

AC'97 Frame
Clock

I2S Frame Clock

ASDI

AC'97 Serial
Input

AC'97 Serial Input I2S Serial Input

ASDO

AC'97 Serial
Output

I2S Serial Output

DS515PP7

EP9312
Universal Platform SOC Processor

LCD-specific features include:

· Timing and interface signals for digital LCD and TFT

displays

· Full programmability for either non-interlaced or dual-

scan color and grayscale flat panel displays

· Dedicated data path to SDRAM controller for

improved system performance

· Pixel depths of 4, 8, 16, or 24 bits per pixel or 256

levels of grayscale

· Hardware Cursor up to 64 x 64 pixels
· 256 x 18 Color Lookup Table
· Hardware Blinking
· 8-bit interface to low-end panel

Touch Screen Interface with 12-bit Analog-
to-digital Converter (ADC)

The touch screen interface performs all sampling,
averaging, ADC range checking, and control for a wide
variety of analog resistive touch screens. This controller
only interrupts the processor when a meaningful change
occurs. The touch screen hardware may be disabled and
the switch matrix and ADC controlled directly if desired.
Features include:

· Support for 4-, 5-, 7-, or 8-wire analog resistive touch

screens.

· Flexibility - unused lines may be used for temperature

sensing or other functions.

· Touch screen interrupt function.

64-Key Keypad Interface

The keypad circuitry scans an 8 x 8 array of 64 normally
open, single-pole switches. Any one or two keys
depressed will be de-bounced and decoded. An interrupt
is generated whenever a stable set of depressed keys is
detected. If the keypad is not utilized, the 16 column/row
pins may be used as general purpose I/O. The Keypad
interface:

· Provides scanning, debounce, and decoding for a 64-

key switch array.

· Scans an 8-row by 8-column matrix.
· May decode 2 keys at once.
· Generates an interrupt when a new stable key is

determined.

· Also generates a 3-key reset interrupt.

Universal Asynchronous
Receiver/Transmitters (UARTs)

Three 16550-compatible UARTs are supplied. Two
provide asynchronous HDLC (High-level Data Link
Control) protocol support for full duplex transmit and
receive. The HDLC receiver handles framing, address
matching, CRC checking, control-octet transparency, and
optionally passes the CRC to the host at the end of the
packet. The HDLC transmitter handles framing, CRC
generation, and control-octet transparency. The host
must assemble the frame in memory before
transmission. The HDLC receiver and transmitter use the
UART FIFOs to buffer the data streams. A third IrDA

compatible UART is also supplied.

· UART1 supports modem bit rates up to 115.2 Kbps,

supports HDLC and includes a 16 byte FIFO for

Table F. LCD Interface Pin Assignments

Pin Mnemonic

Pin Description

SPCLK

Pixel Clock

P[17:0]

Pixel Data Bus [17:0]

HSYNC / LP

Horizontal
Synchronization / Line Pulse

VCSYNC / FP

Vertical or Composite
Synchronization / Frame Pulse

BLANK

Composite Blank

BRIGHT

Pulse Width Modulated Brightness

Table G. Touch Screen Interface with 12-bit Analog-to-Digital

Converter Pin Assignments

Pin Mnemonic

Pin Description

Xp, Xm

Touch screen ADC X Axis

Yp, Ym

Touch screen ADC Y Axis

SXp, SXm

Touch screen ADC X Axis
Voltage Feedback

SYp, SYm

Touch screen ADC Y Axis
Voltage Feedback

Table H. 64-Key Keypad Interface Pin Assignments

Pin Mnemonic

Pin

Description

Alternative Usage

COL[7:0]

Key Matrix Column
Inputs

General Purpose I/O

ROW[7:0]

Key Matrix Row
Inputs

General Purpose I/O

Table G. Touch Screen Interface with 12-bit Analog-to-Digital

Converter Pin Assignments

Pin Mnemonic

Pin Description

DS515PP7

EP9312

Universal Platform SOC Processor

receive and a 16 byte FIFO for transmit. Interrupts are
generated on Rx, Tx and modem status change.

· UART2 contains an IrDA encoder operating at either

the slow (up to 115 Kbps), medium (0.576 or 1.152
Mbps), or fast (4 Mbps) IR data rates. It also has a 16
byte FIFO for receive and a 16 byte FIFO for transmit.

· UART3 supports HDLC and includes a 16 byte FIFO

for receive and a 16 byte FIFO for transmit. Interrupts
are generated on Rx and Tx.

Triple-port USB Host

The USB Open Host Controller Interface (Open HCI)
provides full-speed serial communications ports at a
baud rate of 12 Mbits/sec. Up to 127 USB devices
(printer, mouse, camera, keyboard, etc.) and USB hubs
can be connected to the USB host in the USB "tiered
star" topology.

This includes the following features:

· Compliance with the USB 2.0 specification
· Compliance with the Open HCI Rev 1.0 specification
· Supports both low speed (1.5 Mbps) and full speed

(12 Mbps) USB device connections

· Root HUB integrated with 3 downstream USB ports
· Transceiver buffers integrated, over-current protection

on ports

· Supports power management
· Operates as a master on the bus
The Open HCI host controller initializes the master DMA
transfer with the AHB bus:

· Fetches endpoint descriptors and transfer descriptors
· Accesses endpoint data from system memory
· Accesses the HC communication area
· Writes status and retire transfer descriptor

Two-wire Interface

The two-wire interface provides communication and
control for synchronous-serial-driven devices.

Real-time Clock with Software Trim

The software trim feature on the real time clock (RTC)
provides software controlled digital compensation of the
32.768 KHz input clock. This compensation is accurate to

1.24 sec/month.

Note:

A real time clock must be connected to RTCXTALI or
the EP9312 device will not boot.

PLL and Clocking

The Processor and the Peripheral Clocks operate from a
single 14.7456 MHz crystal.

The Real Time Clock operates from a 32.768 KHz
external oscillator.

Table I. Universal Asynchronous Receiver/Transmitters Pin

Assignments

Pin Mnemonic

Pin Name - Description

TXD0

UART1 Transmit

RXD0

UART1 Receive

CTSn

UART1 Clear To Send /
Transmit Enable

DSRn / DCDn

UART1 Data Set Ready /
Data Carrier Detect

DTRn

UART1 Data Terminal Ready

RTSn

UART1 Ready To Send

EGPIO[0] / RI

UART1 Ring Indicator

TXD1 / SIROUT

UART2 Transmit /
IrDA Output

RXD1 / SIRIN

UART2 Receive / IrDA Input

TXD2

UART3 Transmit

RXD2

UART3 Receive

EGPIO[3] / TENn

HDLC3 Transmit Enable

Table J. Triple Port USB Host Pin Assignments

Pin Mnemonic

Pin Name - Description

USBp[2:0]

USB Positive signals

USBm[2:0]

USB Negative Signals

Table K. Two-Wire Port with EEPROM Support Pin Assignments

Pin Mnemonic

Pin Name - Description

Alternative

Usage

EECLK

Two-wire Interface Clock

General
Purpose I/O

EEDATA

Two-wire Interface Data

General
Purpose I/O

Table L. Real-Time Clock with Pin Assignments

Pin Mnemonic

Pin Name - Description

RTCXTALI

Real-Time Clock Oscillator Input

RTCXTALO

Real-Time Clock Oscillator Output

DS515PP7

EP9312
Universal Platform SOC Processor

Timers

The Watchdog Timer ensures proper operation by
requiring periodic attention to prevent a reset-on-time-
out.

Two 16-bit timers operate as free-running down counters
or as periodic timers for fixed-interval interrupts and have
a range of 0.03 ms to 4.27 seconds.

One 32-bit timer, plus a 6-bit prescale counter, has a
range of 0.03

s to 73.3 hours.

One 40-bit debug timer, plus a 6-bit prescale counter, has
a range of 1.0

s to 12.7 days.

Interrupt Controller

The interrupt controller allows up to 64 interrupts to
generate an Interrupt Request (IRQ) or Fast Interrupt
Request (FIQ) signal to the processor core. Thirty-two
hardware priority assignments are provided for assisting
IRQ vectoring, and two levels are provided for FIQ
vectoring. This allows time-critical interrupts to be
processed in the shortest time possible. Internal
interrupts may be programmed as active high or active
low level sensitive inputs. External interrupts may be
programmed as active-high level-sensitive, active-low
level-sensitive, rising-edge-triggered, falling-edge-
triggered, or combined rising/falling-edge-triggered.

· Supports 64 interrupts from a variety of sources (such

as UARTs, GPIO, and key matrix)

· Routes interrupt sources to either the ARM920T's

IRQ or FIQ (Fast IRQ) inputs

· Four dedicated off-chip interrupt lines INT[3:0]

operate as level-sensitive interrupts

· Any of the 16 GPIO lines maybe configured to

generate interrupts

· Software-supported priority mask for all FIQs and

IRQs

Dual LED Drivers

Two pins are assigned specifically to drive external
LEDs.

General Purpose Input/Output (GPIO)

The 16 EGPIO pins may each be configured individually
as an output, an input, or an interrupt input.

There are 23 pins that may alternatively be used as input,
output, but do not support interrupts. These pins are:

· Key Matrix ROW[7:0], COL[7:0]

· Ethernet MDIO

· Both LED Outputs

· Two-wire Clock and Data

· SLA [1:0]

6 pins may alternatively be used as inputs only:

· CTSn, DSRn / DCDn

· 4 Interrupt Lines

2 pins may alternatively be used as outputs only:

· RTSn

· ARSTn

Reset and Power Management

The chip may be reset through the PRSTn pin or through
the open drain common reset pin, RSTOn.

Clocks are managed on a peripheral-by-peripheral basis
and may be turned off to conserve power.

The processor clock is dynamically adjustable from 0 to
200 MHz (184 MHz for industrial conditions).

Table M. PLL and Clocking Pin Assignments

Pin Mnemonic

Pin Name - Description

XTALI

Main Oscillator Input

XTALO

Main Oscillator Output

VDD_PLL

Main Oscillator Power

GND_PLL

Main Oscillator Ground

Table N. External Interrupt Controller Pin Assignment

Pin Mnemonic

Pin Name - Description

INT[3:0]

External Interrupt 3-0

Table O. Dual LED Pin Assignments

Pin Mnemonic

Pin Name -

Description

Alternative Usage

GRLED

Green LED

General Purpose I/O

REDLED

Red LED

General Purpose I/O

Table P. General Purpose Input/Output Pin Assignment

Pin Mnemonic

Pin Name - Description

EGPIO[15:0]

Expanded General Purpose Input / Output
Pins with Interrupts

Table Q. Reset and Power Management Pin Assignments

Pin Mnemonic

Pin Name - Description

PRSTn

Power On Reset

RSTOn

User Reset In/Out Open Drain
Preserves Real Time Clock value

DS515PP7

EP9312

Universal Platform SOC Processor

Hardware Debug Interface

The JTAG interface allows use of ARM's Multi-ICE or
other in-circuit emulators.

12-channel DMA Controller

The DMA module contains 12 separate DMA channels.
Ten of these may be used for peripheral-to-memory or
memory-to-peripheral access. Two of these are
dedicated to memory-to-memory transfers. Each DMA
channel is connected to the 16-bit DMA request bus.

The request bus is a collection of requests, Serial Audio
and UARTs. Each DMA channel can be used
independently or dedicated to any request signal. For
each DMA channel, source and destination addressing
can be independently programmed to increment,
decrement, or stay at the same value. All DMA
addresses are physical, not virtual addresses.

Internal Boot ROM

The Internal 16 Kbyte ROM allows booting from FLASH
memory, SPI or UART. Consult the EP93xx User's Guide
for operational details.

Table R. Hardware Debug Interface

Pin Mnemonic

Pin Name - Description

TCK

JTAG Clock

TDI

JTAG Data In

TDO

JTAG Data Out

TMS

JTAG Test Mode Select

TRSTn

JTAG Port Reset

DS515PP7

EP9312
Universal Platform SOC Processor

Electrical Specifications

Absolute Maximum Ratings

Note:

1. Includes all power generated by AC and/or DC output loading.
2. The power supply pins are at recommended maximum values.
3. At ambient temperatures above 70° C, total power dissipation must be limited to less than 2.5 Watts.

WARNING: Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Recommended Operating Conditions

(All grounds = 0 V, all voltages with respect to 0 V)

Parameter

Symbol

Min

Max

Unit

Power Supplies

RVDD
CVDD

VDD_PLL

VDD_ADC

-
-
-
-

3.96
2.16
2.16
3.96

V
V
V
V

Total Power Dissipation

(Note 1)

Input Current per Pin, DC (Except supply pins)

±10

Output current per pin, DC

±50

Digital Input voltage

(Note 2)

-0.3

RVDD+0.3

Storage temperature

-40

+125

°C

(All grounds = 0 V, all voltages with respect to 0 V)

Parameter

Symbol

Min

Typ

Max

Unit

Power Supplies

RVDD
CVDD

VDD_PLL

VDD_ADC

3.0

1.65
1.65

3.0

3.3

1.80
1.80

3.3

3.6

1.94
1.94

3.6

V
V
V
V

Operating Ambient Temperature - Commercial

+25

+70

°C

Operating Ambient Temperature - Industrial

-40

+25

+85

°C

Processor Clock Speed - Commercial

FCLK

200

MHz

Processor Clock Speed - Industrial

FCLK

184

MHz

System Clock Speed - Commercial

HCLK

100

MHz

System Clock Speed - Industrial

HCLK

MHz

DS515PP7

EP9312

Universal Platform SOC Processor

DC Characteristics

Note:

4. For open drain pins, high level output voltage is dependent on the external load.
5. All inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper operation (See

Table S on

page 59

). If an input is not driven, it should be tied to power or ground, depending on the particular function. If an I/O pin is not

driven and programmed as an input, it should be tied to power or ground through its own resistor.

= 0 to 70° C; CVDD = VDD_PLL = 1.8; RVDD = 3.3 V;

All grounds = 0 V; all voltages with respect to 0 V unless otherwise noted)

Parameter

Symbol

Min

Max

Unit

High level output voltage

Iout = -4 mA

(Note 4)

0.85

RVDD

Low level output voltage

Iout = 4 mA

0.15

RVDD

High level input voltage

(Note 5)

0.65

RVDD

VDD + 0.3

Low level input voltage

(Note 5)

-0.3

0.35

RVDD

High level leakage current

Vin = 3.3 V

(Note 5)

µA

Low level leakage current

Vin = 0

(Note 5)

-10

µA

Parameter

Min

Typ

Max

Unit

Power Supply Pins (Outputs Unloaded)

Power Supply Current:

CVDD / VDD_PLL Total
RVDD

-
-

190

240

mA
mA

Low-Power Mode Supply Current

CVDD / VDD_PLL Total
RVDD

-
-

1.0

3.5

mA
mA

DS515PP7

EP9312

Universal Platform SOC Processor

Memory Interface

SDRAM Load Mode Register Cycle

Figure 2

through

Figure 5

define the timings associated with all phases of the SDRAM. The following table contains the

values for the timings of each of the SDRAM modes.

Parameter

Symbol

Min

Typ

Max

Unit

SDCLK high time

clk_high

HCLK

) / 2

SDCLK low time

clk_low

HCLK

) / 2

SDCLK rise/fall time

clkrf

Signal delay from SDCLK rising edge time

Signal hold from SDCLK rising edge time

DQMn delay from SDCLK rising edge time

DQd

DQMn hold from SDCLK rising edge time

DQh

DA valid setup to SDCLK rising edge time

DAs

DA valid hold from SDCLK rising edge time

DAh

Figure 2. SDRAM Load Mode Register Cycle Timing Measurement

SDCLK

SDCSn

RASn

CASn

SDWEn

DQMn

OP-Code

clk_high

clk_low

clkrf

DS515PP7

EP9312

Universal Platform SOC Processor

Static Memory 32-bit Read on 8-bit External Bus

Parameter

Symbol

Min

Typ

Max

Unit

AD setup to CSn assert time

ADs

HCLK

CSn assert to Address transition time

AD1

HCLK

(WST1 + 1)

Address assert time

AD2

HCLK

(WST1 + 1)

AD transition to CSn deassert time

AD3

HCLK

(WST1 + 2)

AD hold from CSn deassert time

ADh

HCLK

RDn assert time

RDpwL

HCLK

WST1 + 5)

CSn to RDn delay time

RDd

CSn assert to DQMn assert delay time

DQMd

DA setup to AD transition time

DAs1

DA setup to RDn deassert time

DAs2

HCLK

DA hold from AD transition time

DAh1

DA hold from RDn deassert time

DAh2

Figure 8. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement

CSn

WRn

RDn

DQMn

ADs

AD1

AD2

DAs1

RDd

DAh1

DAs1

DAs2

DAh2

ADh

WAIT

RDd

DQMd

AD3

DS515PP7

EP9312
Universal Platform SOC Processor

Static Memory 32-bit Write on 8-bit External Bus

Parameter

Symbol

Min

Typ

Max

Unit

AD setup to WRn assert time

ADs

HCLK

WRn/DQMn deassert to AD transition time

ADd

HCLK

AD hold from WRn deassert time

ADh

HCLK

CSn hold from WRn deassert time

CSh

CSn to WRn assert delay time

WRd

WRn assert time

WRpwL

HCLK

(WST1 + 1)

WRn deassert time

WRpwH

HCLK

2) + 14

CSn to DQMn assert delay time

DQMd

DQMn assert time

DQMpwL

HCLK

(WST1 + 1)

DQMn deassert time

DQMpwH

HCLK

2) + 7

WRn / DQMn deassert to DA transition time

DAh

HCLK

WRn / DQMn assert to DA valid time

DAV

Figure 9. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement

CSn

WRn

RDn

DQMn

ADs

WRd

DQMd

WRpwL

DAh

WRpwH

ADd

CSh

ADh

DQMpwL

DQMpwH

WRpwL

WRpwH

WRpwL

WRpwH

DQMpwL

DQMpwH

DQMpwL

DQMpwH

DAh

ADd

WAIT

DAV

DS515PP7

EP9312

Universal Platform SOC Processor

Static Memory 32-bit Read on 16-bit External Bus

Parameter

Symbol

Min

Typ

Max

Unit

AD setup to CSn assert time

ADs

HCLK

CSn assert to AD transition time

ADd1

HCLK

(WST1 + 1)

AD transition to CSn deassert time

ADd2

HCLK

(WST1 + 2)

AD hold from CSn deassert time

ADh

HCLK

RDn assert time

RDpwL

HCLK

((2

WST1) + 3)

CSn to RDn delay time

RDd

CSn assert to DQMn assert delay time

DQMd

DA setup to AD transition time

DAs1

DA to RDn deassert time

DAs2

HCLK

+ 12

DA hold from AD transition time

DAh1

DA hold from RDn deassert time

DAh2

Figure 10. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement

CSn

WRn

RDn

DQMn

RDpwl

ADd1

RDh

DQMh

DAh2

DAs1

DAh1

DAs2

WAIT

ADs

RDd

DQMd

ADh

ADd2

DS515PP7

EP9312
Universal Platform SOC Processor

Static Memory 32-bit Write on 16-bit External Bus

Parameter

Symbol

Min

Typ

Max

Unit

AD setup to WRn assert time

ADs

HCLK

WRn/DQMn deassert to AD transition time

ADd

HCLK

+ 6

AD hold from WRn deassert time

ADh

HCLK

× 2

CSn hold from WRn deassert time

CSh

CSn to WRn assert delay time

WRd

WRn assert time

WRpwL

HCLK

× (WST1 + 1)

WRn deassert time

WRpwH

HCLK

× 2) + 14

CSn to DQMn assert delay time

DQMd

DQMn assert time

DQMpwL

HCLK

× (WST1 + 1)

DQMn deassert time

DQMpwH

HCLK

× 2) + 7

WRn / DQMn deassert to DA transition time

DAh1

HCLK

WRn / DQMn assert to DA valid time

DAV

Figure 11. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement

CSn

WRn

RDn

DQMn

ADs

WRd

WRpwL

DAh

ADd

WRpwH

DQMd

ADh

DAh

WRpwL

DQpwL

DQpwH

DQpwL

WAIT

CSh

DAV

DS515PP7

EP9312

Universal Platform SOC Processor

Static Memory Burst Read Cycle

Note:

These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.

Parameter

Symbol

Min

Typ

Max

Unit

CSn assert to Address 1 transition time

ADd1

HCLK

(WST1 + 1)

Address assert time

ADd2

HCLK

(WST2 + 1)

AD transition to CSn deassert time

ADd3

HCLK

(WST1 + 2)

AD hold from CSn deassert time

ADh

HCLK

CSn to RDn delay time

RDd

CSn to DQMn assert delay time

DQMd

DA setup to AD transition time

DAs1

DA setup to CSn deassert time

DAs2

HCLK

+ 12

DA hold from AD transition time

DAh1

DA hold from RDn deassert time

DAh2

Figure 12. Static Memory Burst Read Cycle Timing Measurement

CSn

WRn

RDn

DQMn

ADd1

ADd2

RDd

DQMd

DAs1

DAh1

DAs1

DAh1

DAs1

DAh1

DAs2

DAh2

ADh

WAIT

ADd3

ADs

DS515PP7

EP9312
Universal Platform SOC Processor

Static Memory Burst Write Cycle

Note:

These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.

Parameter

Symbol

Min

Typ

Max

Unit

AD setup to WRn assert time

ADs

HCLK

AD hold from WRn deassert time

ADh

HCLK

WRN/DQMn deassert to AD transition time

ADd

HCLK

+ 6

CSn hold from WRn deassert time

CSh

CSn to WRn assert delay time

WRd

CSn to DQMn assert delay time

DQMd

DQMn assert time

DQpwL

HCLK

(WST1 + 1)

DQMn deassert time

DQpwH

HCLK

2) + 14

WRn assert time

WRpwL

HCLK

(WST1 + 11)

WRn deassert time

WRpwH

HCLK

2) + 7

WRn/DQMn deassert to DA transition time

DAh

HCLK

WRn/DQMn assert to DA valid time

DAv

Figure 13. Static Memory Burst Write Cycle Timing Measurement

CSn

WRn

DQMn

WAIT

ADs

ADd

WRpwL

DQpwL

DQpwH

WRpwH

DAv

DAh

WRd

DQMd

CSh

ADh

DS515PP7

EP9312
Universal Platform SOC Processor

IDE Interface

Register Transfers

Note:

1. t

is the minimum total cycle time, t

is the minimum DIORn / DIOWn assertion time, and t

is the minimum DIORn / DIOWn

negation time. A host implementation shall lengthen t

and/or t

to ensure that t

is equal to or greater than the value

reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.

2. This parameter specifies the time from the negation edge of DIORn to the time that the data bus is released by the device.

3. The delay from the activation of DIORn or DIOWn until the state of IORDY is first sampled. If IORDY is inactive then the host

shall wait until IORDY is active before the register transfer cycle is completed. If the device is not driving IORDY negated at
the t

after the activation of DIORn or DIOWn, then t

shall be met and t

is not applicable. If the device is driving IORDY

negated at the time t

after the activation of DIORn or DIOWn, then t

shall be met and t

is not applicable.

4. Timings based upon software control. See User's Guide.

5. ATA / ATAPI standards prior to ATA / ATAPI-5 inadvertently specified an incorrect value for mode 2 time t

by utilizing the

16-bit PIO value.

6. All IDE timing is based upon HCLK = 100 MHz.

Parameter

Symbol

Mode 0

(in ns)

Mode 1

(in ns)

Mode 2

(in ns)

Mode 3

(in ns)

Mode 4

(in ns)

Cycle time

(min)

(Notes 1, 4, 5)

600

383

330

180

120

Address valid to DIORn / DIOWn setup

(min)

(Note 4)

DIORn / DIOWn pulse width 8-bit

(min)

(Note 1, 4)

290

DIORn / DIOWn recovery time

(min)

(Note 1, 4)

DIOWn data setup

(min)

(Note 4)

DIOWn data hold

(min)

DIORn data setup

(min)

DIORn data hold

(min)

DIORn data high impedance state

(max)

(Note 2, 4)

DIORn / DIOWn to address valid hold

(min)

(Note 4)

Read Data Valid to IORDY

(min)

active (if IORDY initially low after t

)

(Note 4)

IORDY Setup time

(Note 3, 4)

IORDY Pulse Width

(max)

(Note 4)

1250

IORDY assertion to release

(max)

DIOWn assert to data valid

(max)

DDV

DS515PP7

EP9312

Universal Platform SOC Processor

Note:

1. Device address consists of signals IDECS0n, IDECS1n and IDEDA (2:0)
2. Data consists of DD (7:0)
3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is

to be extended is made by the host after t

from the assertion of DIORn or DIOWn. The assertion and negation or IORDY

are described in the following three cases:

3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2 Device negates IORDY before t

, but causes IORDY to be asserted before t

. IORDY is released prior to negation

and may be asserted for no more than t

before release: no wait generated.

3-3 Device negates IORDY before t

. IORDY is released prior to negation and may be asserted for no more than t

before release: wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated
and DIORn is asserted, the device shall place read data on DD (7:0) for t

before asserting IORDY.

Figure 17. Register Transfer to/from Device

ADDR valid

(Note 1)

DIORn/

DIOWn

WRITE

DD (7:0)

(Note 2)

READ

DD (7:0)

(Note 2)

IORDY

(Note 3,3-1)

IORDY

(Note 3,3-2)

IORDY

(Note 3,3-3)

DDV

DS515PP7

EP9312
Universal Platform SOC Processor

PIO Data Transfers

Note:

1. t

is the minimum total cycle time, t

is the minimum DIORn / DIOWn assertion time, and t

is the minimum DIORn / DIOWn

negation time. A host implementation shall lengthen t

and/or t

to ensure that t

is equal to or greater than the value

reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.

2. This parameter specifies the time from the negation edge of DIORn to the time that the data bus is released by the device.
3. The delay from the activation of DIORn or DIOWn until the state of IORDY is first sampled. If IORDY is inactive then the host

shall wait until IORDY is active before the register transfer cycle is completed. If the device is not driving IORDY negated at
the t

after the activation of DIORn or DIOWn, then t

shall be met and t

is not applicable. If the device is driving IORDY

negated at the time t

after the activation of DIORn or DIOWn, then t

shall be met and t

is not applicable.

4. Timings based upon software control. See User's Guide.
5. All IDE timing is based upon HCLK = 100 MHz.

Parameter

Symbol

Mode 0

(in ns)

Mode 1

(in ns)

Mode 2

(in ns)

Mode 3

(in ns)

Mode 4

(in ns)

Cycle time

(min)

(Note 1, 4)

600

383

240

180

120

Address valid to DIORn / DIOWn setup

(min)

(Note 4)

DIORn / DIOWn 16-bit

(min)

(Note 1, 4)

165

125

100

DIORn / DIOWn recovery time

(min)

(Note 1, 4)

DIOWn data setup

(min)

(Note 4)

DIOWn data hold

(min)

DIORn data setup

(min)

DIORn data hold

(min)

DIORn data high impedance state

(max)

(Note 2, 4)

DIORn / DIOWn to address valid hold

(min)

(Note 4)

Read Data Valid to IORDY

(min)

active (if IORDY initially low after t

)

(Note 4)

IORDY Setup time

(Note 3, 4)

IORDY Pulse Width

(max)

(Note 4)

1250

IORDY assertion to release

(max)

DIOWn assert to data valid

(max)

DDV

DS515PP7

EP9312

Universal Platform SOC Processor

Note:

1. Device address consists of signals IDECS0n, IDECS1n and IDEDA (2:0)
2. Data consists of DD (15:0)
3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is

to be extended is made by the host after t

from the assertion of DIORn or DIOWn. The assertion and negation or IORDY

are described in the following three cases:

3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2 Device negates IORDY before t

, but causes IORDY to be asserted before t

. IORDY is released prior to negation

and may be asserted for no more than t

before release: no wait generated.

3-3 Device negates IORDY before t

. IORDY is released prior to negation and may be asserted for no more than t

before release: wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated
and DIORn is asserted, the device shall place read data on DD (15:0) for t

before asserting IORDY.

Figure 18. PIO Data Transfer to/from Device

ADDR valid

(Note 1)

DIORn/

DIOWn

WRITE

DD(15:0)

(Note 2)

READ

DD(15:0)

(Note 2)

IORDY

(Note 3,3-1)

IORDY

(Note 3,3-2)

IORDY

(Note 3,3-3)

DDV

DS515PP7

EP9312
Universal Platform SOC Processor

Ultra DMA Data Transfer

Figure 19

through

Figure 28

define the timings associated with all phases of Ultra DMA bursts. The following table

contains the values for the timings for each of the Ultra DMA modes.

Note:

1. Timing parameters shall be measured at the connector of the sender or receiver to which the parameter applies.
2. The test load for t

DVS

and t

DVH

shall be a lumped capacitor load with no cable or receivers. Timing for t

DVS

and t

DVH

shall be

met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value.

3. t

, t

MLI

and t

indicate sender-to-recipient or recipient-to-sender interlocks, i.e., either sender or recipient is waiting for the

other to respond with a signal before proceeding. t

is an unlimited interlock that has no maximum time value. t

MLI

is a limited

time-out that has a defined minimum. t

is a limited time-out that has a defined maximum.

4. t

ZIORDY

may be greater than t

ENV

since the device has a pull up on IORDYn giving it a known state when released.

5. All IDE timing is based upon HCLK = 100 MHz.

Timing reference levels = 1.5 V

Parameter

Symbol

Mode 0

(in ns)

Mode 1

(in ns)

Mode 2

(in ns)

Mode 3

(in ns)

min max min max min max min max

Cycle time allowing for asymmetry and clock variations
(from DSTROBE edge to DSTROBE edge)

CYCRD

112

Two-cycle time allowing for clock variations (from rising edge to next
rising edge or from falling edge to next falling edge of DSTROBE)

2CYCRD

230

154

115

Cycle time allowing for asymmetry and clock variations
(from HSTROBE edge to HSTROBE edge)

CYCWR

230

170

130

100

Two-cycle time allowing for clock variations (from rising edge to next
rising edge or from falling edge to next falling edge of HSTROBE)

2CYCWR

460

340

260

200

Data setup time at recipient (Read)

Data hold time at recipient (Read)

Data valid setup time at sender (Write)

(Note 2)

(from data valid until STROBE edge)

DVS

Data valid hold time at sender (Write)

(Note 2)

(from STROBE edge until data may become invalid)

DVH

First STROBE time (for device to first negate DSTROBE from STOP
during a data in burst)

230

200

170

130

Limited interlock time

(Note 3)

150

100

Interlock time with minimum

(Note 3)

MLI

Unlimited interlock time

(Note 3)

Maximum time allowed for output drivers to release
(from asserted or negated)

Minimum delay time required for output

ZAH

Drivers to assert or negate (from released)

ZAD

Envelope time (from DMACKn to STOP and HDMARDYn during data in
burst initiation and from DMACKn to STOP during data out burst initiation)

ENV

Ready-to-final-STROBE time (no STROBE edges shall be sent this long
after negation of DMARDYn)

RFS

Ready-to-pause time
(that recipient shall wait to pause after negating DMARDYn)

160

125

100

Maximum time before releasing IORDY

IORDYZ

Minimum time before driving STROBE

(Note 4)

ZIORDY

Setup and hold times for DMACKn (before assertion or negation)

ACK

Time from STROBE edge to negation of DMARQ or assertion of STOP
(when sender terminates a burst)

DS515PP7

EP9312
Universal Platform SOC Processor

Note:

DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as
cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are
driven by the host.

Figure 25. Sustained Ultra DMA data-out Burst

Note:

1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t

after DDMARDYn is

negated.

2. If the t

timing is not satisfied, the device may receive zero, one, or two more data words from the host.

Figure 26. Device Pausing an Ultra DMA data-out Burst

HSTROBE

(host)

DD (15:0)

(host)

HSTROBE

(device)

DD (15:0)

(device)

CYCWR

2CYCWR

CYCWR

DVH

DVS

DVH

DVS

DVH

DD (15:0)

(host)

HSTROBE

(host)

DDMARDYn

(device)

STOP

(host)

DMACKn

(host)

DMARQ

(device)

RFS

DS515PP7

EP9312

Universal Platform SOC Processor

Ethernet MAC Interface

STA - Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer

(PHY) interface to the wireless medium.

PHY - Ethernet physical layer interface.

Parameter

Symbol

Min

Typ

Max

Unit

10 Mbit

mode

100 Mbit

mode

10 Mbit

mode

100 Mbit

mode

10 Mbit

mode

100 Mbit

mode

TXCLK cycle time

TX_per

400

TXCLK high time

TX_high

140

200

260

TXCLK low time

TX_low

140

200

260

TXCLK to signal transition delay time

TXd

TXCLK rise/fall time

TXrf

RXCLK cycle time

RX_per

400

RXCLK high time

RX_high

140

200

260

RXCLK low time

RX_low

140

200

260

RXDVAL / RXERR setup time

RXs

RXDVAL / RXERR hold time

RXh

RXCLK rise/fall time

RXrf

MDC cycle time

MDC_per

400

MDC high time

MDC_high

160

MDC low time

MDC_low

160

MDC rise/fall time

MDCrf

MDIO setup time (STA sourced)

MDIOs

MDIO hold time (STA sourced)

MDIOh

MDC to MDIO signal transition delay time
(PHY sourced)

MDIOd

300

DS515PP7

EP9312

Universal Platform SOC Processor

ADC

Note:

ADIV refers to bit 16 in the KeyTchClkDiv register.
ADIV = 0 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 4.
ADIV = 1 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 16.

Using the ADC:

This ADC has a state-machine based conversion engine that automates the conversion process. The initiator for a
conversion is the read access of the TSXYResult register by the CPU. The data returned from reading this register
contains the result as well as the status bit indicating the state of the ADC. However, this peripheral requires a delay
between each successful conversion and the issue of the next conversion command, or else the returned value of
successive samples may not reflect the analog input. Since the state of the ADC state machine is returned through the
same channel used to initiate the conversion process, there must be a delay inserted after every complete conversion.
Note that reading TSXYResult during a conversion will not affect the result of the ongoing process.

The following is a recommended procedure for safely polling the ADC from software:

1. Read the TSXYResult register into a local variable to initiate a conversion.
2. If the value of bit 31 of the local variable is '0' then repeat step 1.
3. Delay long enough to meet the maximum sample rate as shown above.
4. Mask the local variable with 0xFFFF to remove extraneous data.
5. If signed mode is used, do a sign extend of the lower halfword.
6. Return the sampled value.

Parameter

Comment

Value

Units

Resolution

No missing codes

Range of 0 to 3.3 V

50K counts (approximate)

Integral non-linearity

0.01%

Offset error

±15

Full scale error

0.2%

Maximum sample rate

ADIV = 0
ADIV = 1

3750

925

Samples per second
Samples per second

Channel switch settling time

ADIV = 0
ADIV = 1

500

Noise (RMS) - typical

120

Figure 36. ADC Transfer Function

Vref/2

Vref

0000

FFFF

61A8

9E58

A/D Converter Transfer Function

(approximately ±25,000 counts)

DS515PP7

EP9312
Universal Platform SOC Processor

Note:

1. Controlling Dimension: Millimeter.
2. Primary Datum C and seating plane are defined by the spherical crowns of the solder balls.
3. Dimension b is measured at the maximum solder ball diameter, parallel to Primary Datum C.
4. There shall be a minimum clearance of 0.25 mm between the edge of the solder ball and the body edge.
5. Reference Document: JEDEC MO-151, BAL-2

352 Pin BGA Pinout (Bottom View)

The following table shows the 352 pin BGA pinout. (For better understanding, compare the coordinates on the x and y
axis on

Figure 40, "352 PIN BGA PINOUT", on page 55

with

Figure 38, "352 Pin PBGA Pin Diagram", on page 53

· VDD_core is CVDD.

· VDD_ring is RVDD.

· All core and ring grounds are connected together and are labelled GND.

· Other special power requirements are clearly labelled (i.e. H18=ADC_VDD and H19=ADC_GND).

· NC means that the pin is not connected.

Table R. 352 Pin Diagram Dimensions

Symbol

dimension in mm

dimension in inches

MIN

NOM

MAX

MIN

NOM

MAX

2.20

2.30

2.50

0.087

0.092

0.098

0.60

0.024

1.12

1.17

1.22

0.044

0.046

0.048

0.75

0.030

0.51

0.56

0.61

0.020

0.022

0.024

26.80

27.00

27.20

1.055

1.063

1.071

24.13

0.950

23.80

24.00

24.20

0.937

0.945

0.953

17.95

18.00

18.05

0.707

0.709

0.711

26.80

27.00

27.20

1.055

1.063

1.071

24.13

0.950

23.80

24.00

24.20

0.937

0.945

0.953

17.95

18.00

18.05

0.707

0.709

0.711

1.27

0.050

ddd

0.15

0.006

30° TYP

DS515

PP7

Co
py
rig
h

t 20

0
5

Cirru

s

Lo
gi

c (All Righ

Re
se

ed
)

5
5

EP9312

Un
ivers

a
l Platfor

SOC

Figure 40. 352 PIN BGA PINOUT

Y HSYNC DD[1]

DD[12]

P[2]

AD[15] DA[6] DA[4]

AD[10

]

DA[1]

AD[8]

IDEDA[

DTRN

TDO

BOOT[0] EEDAT ASDO

SFRM1 RDLED USBP[1] ABITCLK Y

W P[12]

P[9]

DD[0]

P[5]

P[3]

DA[7] DA[5]

AD[11

]

AD[9]

IDECS1

IDEDA[

TCK

TMS

EECLK

SCLK1 GRLED

INT[3]

SLA[1]

SLA[0]

RXD[2] W

P[16]

P[11]

P[8]

DD[15]

DD[13] P[1]

AD[1

AD[12

]

DA[2]

IDECS0

IDEDA[

TDI

GND

ASYNC SSPTX1 INT[2]

RTSN

USBP[0] CTSN

TXD[0]

U AD[0]

P[15]

P[10]

P[7]

P[6]

P[4] P[0]

AD[13

]

DA[3]

DA[0]

DSRN BOOT[1]

SSPRX1 INT[1]

PWMO

USBM[0] RXD[1]

TXD[1]

ROW[1] U

T DA[8]

BLANK

P[13]

SPCLK

V_CSY

DD[1

GND

CVD

RVDD

GND

RVDD

CVDD

GND

INT[0]

USBM[1

]

RXD[0]

TXD[2] ROW[2] ROW[4] T

R AD[2]

AD[1]

P[17]

P[14]

RVDD

RVD

GND

CVD

CVDD

GND

RVDD

ROW[0] ROW[3]

PLL_GN

ROW[5] R

P AD[4]

DA[10]

DA[9] BRIGHT RVDD

RVD

RVDD

XTALI

PLL_VD

ROW[6] ROW[7] P

N DA[13] DA[12] DA[11]

AD[3]

CVDD

CVD

GND

XTALO

COL[0]

COL[1]

COL[2]

M AD[7]

DA[14]

AD[6]

AD[5]

CVDD

GND

COL[4]

COL[3]

COL[6]

CSN[0] M

L DA[18] DA[17] DA[16] DA[15]

GND

CVDD

COL[5]

COL[7] RSTON

PRSTN L

K AD[22] DA[20] AD[21] DA[19]

RVDD

GND

CVDD

SYM

SYP

SXM

SXP

J DA[21]

DQMN[

DQMN[2

]

GND

CVDD

RTCXTA

DQMN[

CASN

RASN

SDCSN[

CVDD

GND

RVDD

RTCXTA

ADC_V

ADC_G

SDCSN[

SDWE

SDCLK

RVDD

RVD

RVDD

RVDD EGPIO[7]

EGPIO[

EGPIO[1

EGPIO[11

]

SDCSN[

DA[22] DA[24] AD[25]

RVDD GND

CVD

CVDD

GND

GND EGPIO[2]

EGPIO[

EGPIO[6

]

EGPIO[8] F

E AD[23] DA[23] DA[26] CSN[6]

GND

CVD

RVDD

GND

RVDD

CVDD

GND

ASDI

DIOWN

EGPIO[

EGPIO[3

]

EGPIO[5] E

D AD[24] DA[25] DD[11]

SDCLK

AD[19] DD[9] DD[5]

AD[16

]

MIIRXD[

MIITXD[

TXEN

EGPIO[

14]

USBM[2] ARSTN DIORN EGPIO[1] D

C CSN[1] CSN[3] AD[20] DA[29]

DD[10] DD[6] DD[2] MDC

MIIRXD[

TXCLK

MIITXD[

USBP[2] IORDY DMACKN C

B CSN[2] DA[31] DA[30] DA[27]

DD[7] DD[3] WRN MDIO

MIIRXD[

RXERR

MIITXD[

CRS

EGPIO[1

WAITN

TRSTN B

A CSN[7] DA[28] AD[18]

DD[8]

DD[4]

AD[1

RDN

RXCL

MIIRXD[

RXDVA

MIITXD[

TXERR

CLD

EGPIO[1

EGPIO[

15]

DS515PP7

EP9312
Universal Platform SOC Processor

Pin List

The following Plastic Ball Grid Array (PBGA) ball assignment table is sorted in order of ball.

Ball

Signal

Ball

Signal

Ball

Signal

Ball

Signal

CSN[7]

RVDD

DA[16]

T13

CVDD

DA[28]

E10

GND

DA[15]

T14

GND

AD[18]

E11

GND

T15

INT[0]

DD[8]

E12

RVDD

GND

T16

USBM[1]

DD[4]

E13

CVDD

GND

T17

RXD[0]

AD[17]

E14

CVDD

L10

GND

T18

TXD[2]

RDN

E15

GND

L11

GND

T19

ROW[2]

RXCLK

E16

ASDI

L12

GND

T20

ROW[4]

MIIRXD[0]

E17

DIOWN

L13

GND

AD[0]

A10

RXDVAL

E18

EGPIO[0]

L16

CVDD

P[15]

A11

MIITXD[2]

E19

EGPIO[3]

L17

COL[5]

P[10]

A12

TXERR

E20

EGPIO[5]

L18

COL[7]

P[7]

A13

CLD

SDCSN[3]

L19

RSTON

P[6]

A14

DA[22]

L20

PRSTN

P[4]

A15

DA[24]

AD[7]

P[0]

A16

AD[25]

DA[14]

AD[13]

A17

EGPIO[12]

RVDD

AD[6]

DA[3]

A18

EGPIO[15]

GND

AD[5]

U10

DA[0]

A19

CVDD

U11

DSRN

A20

F14

CVDD

GND

U12

BOOT[1]

CSN[2]

F15

GND

U13

DA[31]

F16

GND

M10

GND

U14

SSPRX1

DA[30]

F17

EGPIO[2]

M11

GND

U15

INT[1]

DA[27]

F18

EGPIO[4]

M12

GND

U16

PWMOUT

DD[7]

F19

EGPIO[6]

M13

GND

U17

USBM[0]

DD[3]

F20

EGPIO[8]

M16

GND

U18

RXD[1]

WRN

SDCSN[0]

M17

COL[4]

U19

TXD[1]

MDIO

SDCSN[1]

M18

COL[3]

U20

ROW[1]

MIIRXD[1]

SDWEN

M19

COL[6]

P[16]

B10

RXERR

SDCLK

M20

CSN[0]

P[11]

B11

MIITXD[1]

RVDD

DA[13]

P[8]

B12

CRS

RVDD

DA[12]

DD[15]

B13

G15

RVDD

DA[11]

DD[13]

B14

G16

RVDD

AD[3]

P[1]

B15

G17

EGPIO[7]

CVDD

AD[14]

B16

G18

EGPIO[9]

CVDD

AD[12]

B17

EGPIO[13]

G19

EGPIO[10]

GND

DA[2]

B18

G20

EGPIO[11]

GND

V10

IDECS0N

B19

WAITN

DQMN[3]

N10

GND

V11

IDEDA[2]

B20

TRSTN

CASN

N11

GND

V12

TDI

CSN[1]

RASN

N12

GND

V13

GND

CSN[3]

SDCSN[2]

N13

GND

V14

ASYNC

DS515PP7

EP9312

Universal Platform SOC Processor

AD[20]

CVDD

N15

GND

V15

SSPTX1

DA[29]

GND

N16

GND

V16

INT[2]

DD[10]

GND

N17

XTALO

V17

RTSN

DD[6]

H10

GND

N18

COL[0]

V18

USBP[0]

DD[2]

H11

GND

N19

COL[1]

V19

CTSN

MDC

H12

GND

N20

COL[2]

V20

TXD[0]

MIIRXD[3]

H13

GND

AD[4]

P[12]

C10

TXCLK

H16

RVDD

DA[10]

P[9]

C11

MIITXD[0]

H17

RTCXTALO

DA[9]

DD[0]

C12

H18

ADC_VDD

BRIGHT

P[5]

C13

H19

ADC_GND

RVDD

P[3]

C14

H20

RVDD

DA[7]

C15

DA[21]

P15

RVDD

DA[5]

C16

DQMN[0]

P16

RVDD

AD[11]

C17

DQMN[1]

P17

XTALI

AD[9]

C18

USBP[2]

DQMN[2]

P18

PLL_VDD

W10

IDECS1N

C19

IORDY

GND

P19

ROW[6]

W11

IDEDA[1]

C20

DMACKN

GND

P20

ROW[7]

W12

TCK

AD[24]

GND

AD[2]

W13

TMS

DA[25]

J10

GND

AD[1]

W14

EECLK

DD[11]

J11

GND

P[17]

W15

SCLK1

SDCLKEN

J12

GND

P[14]

W16

GRLED

AD[19]

J13

GND

RVDD

W17

INT[3]

DD[9]

J16

CVDD

RVDD

W18

SLA[1]

DD[5]

J17

RTCXTALI

GND

W19

SLA[0]

AD[16]

J18

CVDD

W20

RXD[2]

MIIRXD[2]

J19

R13

CVDD

HSYNC

D10

MIITXD[3]

J20

R14

GND

DD[1]

D11

TXEN

AD[22]

R15

RVDD

DD[12]

D12

DA[20]

R16

RVDD

P[2]

D13

AD[21]

R17

ROW[0]

AD[15]

D14

DA[19]

R18

ROW[3]

DA[6]

D15

EGPIO[14]

RVDD

R19

PLL_GND

DA[4]

D16

GND

R20

ROW[5]

AD[10]

D17

USBM[2]

GND

DA[8]

DA[1]

D18

ARSTN

K10

GND

BLANK

Y10

AD[8]

D19

DIORN

K11

GND

P[13]

Y11

IDEDA[0]

D20

EGPIO[1]

K12

GND

SPCLK

Y12

DTRN

AD[23]

K13

GND

V_CSYNC

Y13

TDO

DA[23]

K16

CVDD

DD[14]

Y14

BOOT[0]

DA[26]

K17

SYM

GND

Y15

EEDAT

CSN[6]

K18

SYP

CVDD

Y16

ASDO

GND

K19

SXM

RVDD

Y17

SFRM1

GND

K20

SXP

T10

GND

Y18

RDLED

CVDD

DA[18]

T11

GND

Y19

USBP[1]

CVDD

DA[17]

T12

RVDD

Y20

ABITCLK

Ball

Signal

Ball

Signal

Ball

Signal

Ball

Signal

DS515PP7

EP9312
Universal Platform SOC Processor

The following section focuses on the EP9312 pin signals
from two viewpoints - the pin usage and pad
characteristics, and the pin multiplexing usage. The first
table (

Table S

) is a summary of all the EP9312 pin

signals. The second table (

Table T

) illustrates the pin

signal multiplexing and configuration options.

Table S

is a summary of the EP9312 pin signals, which

illustrates the pad type and pad pull type (if any). The
symbols used in the table are defined as follows. (Note: A
blank box means Not Applicable (NA) or, for Pull Type,
No Pull (NP).)

Under the Pad Type column:

· A - Analog pad
· P - Power pad
· G - Ground pad
· I - Pin is an input only
· I/O - Pin is input/output
· 4mA - Pin is a 4 mA output driver
· 8mA - Pin is an 8 mA output driver
· 12mA - Pin is an 12 mA output driver
See the text description for additional information about
bi-directional pins.

Under the Pull Type Column:

· PU - Resistor is a pull up to the RVDD supply
· PD - Resistor is a pull down to the RGND supply

DS515PP7

EP9312

Universal Platform SOC Processor

Table S. Pin Descriptions

Pin Name

Block

Pad

Type

Pull

Type

Description

TCK

JTAG

JTAG clock in

TDI

JTAG

JTAG data in

TDO

JTAG

4ma

JTAG data out

TMS

JTAG

JTAG test mode select

TRSTn

JTAG

JTAG reset

BOOT[1:0]

System

Boot mode select in

XTALI

PLL

Main oscillator input

XTALO

PLL

Main oscillator output

VDD_PLL

PLL

Main oscillator power, 1.8V

GND_PLL

PLL

Main oscillator ground

RTCXTALI

RTC

RTC oscillator input

RTCXTALO

RTC

RTC oscillator output

WRn

PBUS

4ma

SRAM Write strobe out

RDn

PBUS

4ma

SRAM Read / OE strobe out

WAITn

PBUS

SRAM Wait in

AD[25:0]

PBUS

8ma

Shared Address bus out

DA[31:0]

PBUS

8ma

Shared Data bus in/out

CSn[3:0]

PBUS

4ma

Chip select out

CSn[7:6]

PBUS

4ma

Chip select out

DQMn[3:0]

PBUS

8ma

Shared data mask out

SDCLK

SDRAM

8ma

SDRAM clock out

SDCLKEN

SDRAM

8ma

SDRAM clock enable out

SDCSn[3:0]

SDRAM

4ma

SDRAM chip selects out

RASn

SDRAM

8ma

SDRAM RAS out

CASn

SDRAM

8ma

SDRAM CAS out

SDWEn

SDRAM

8ma

SDRAM write enable out

P[17:0]

Raster

4ma

Pixel data bus out

SPCLK

Raster

12ma

Pixel clock in/out

HSYNC

Raster

8ma

Horizontal synchronization / line pulse out

V_CSYNC

Raster

8ma

Vertical or composite synchronization / frame
pulse out

BLANK

Raster

8ma

Composite blanking signal out

BRIGHT

Raster

4ma

PWM brightness control out

PWMOUT

PWM

8ma

Pulse width modulator output

Xp, Xm

ADC

Touchscreen ADC X axis

Yp, Ym

ADC

Touchscreen ADC Y axis

sXp, sXm

ADC

Touchscreen ADC X axis feedback

sYp, sYm

ADC

Touchscreen ADC Y axis feedback

VDD_ADC

ADC

Touchscreen ADC power, 3.3V

GND_ADC

ADC

Touchscreen ADC ground

COL[7:0]

Key

8ma

Key matrix column inputs

ROW[7:0]

Key

8ma

Key matrix row outputs

USBp[2:0]

USB

USB positive signals

USBm[2:0]

USB

USB negative signals

TXD0

UART1

4ma

Transmit out

RXD0

UART1

Receive in

CTSn

UART1

Clear to send / transmit enable

DSRn

UART1

Data set ready / Data Carrier Detect

DTRn

UART1

4ma

Data Terminal Ready output

RTSn

UART1

4ma

Ready to send

TXD1

UART2

4ma

Transmit / IrDA output

RXD1

UART2

Receive / IrDA input

TXD2

UART3

4ma

Transmit

RXD2

UART3

Receive

MDC

EMAC

4ma

Management data clock

MDIO

EMAC

4ma

Management data input/output

RXCLK

EMAC

Receive clock in

MIIRXD[3:0]

EMAC

Receive data in

RXDVAL

EMAC

Receive data valid

RXERR

EMAC

Receive data error

TXCLK

EMAC

4ma

Transmit clock in

MIITXD[3:0]

EMAC

Transmit data out

TXEN

EMAC

4ma

Transmit enable

TXERR

EMAC

4ma

Transmit error

CRS

EMAC

Carrier sense

CLD

EMAC

Collision detect

GRLED

LED

12ma

Green LED

RDLED

LED

12ma

Red LED

EECLK

EEPROM

4ma

EEPROM / Two-wire Interface clock

EEDAT

EEPROM

4ma

EEPROM / Two-wire Interface data

ABITCLK

AC97

8ma

AC97 bit clock

ASYNC

AC97

8ma

AC97 frame sync

ASDI

AC97

AC97 Primary input

ASDO

AC97

8ma

AC97 output

ARSTn

AC97

8ma

AC97 reset

SCLK1

SPI1

8ma

SPI bit clock

SFRM1

SPI1

8ma

SPI Frame Clock

SSPRX1

SPI1

SPI input

SSPTX1

SPI1

8ma

SPI output

INT[3:0]

INT

External interrupts

PRSTn

Syscon

Power on reset

RSTOn

Syscon

4ma

User Reset in out - open drain

SLA[1:0]

EEPROM

4ma

Flash programming voltage control

EGPIO[15:0]

GPIO

I/O, 4ma

Enhanced GPIO

DD[15:8]

IDE

8ma

IDE data bus

DD7

IDE

8ma

IDE data bus

DD[6:0]

IDE

8ma

IDE data bus

IDEDA[2:0]

IDE

8ma

IDE Device address output

IDECS0n

IDE

8ma

IDE Chip Select 0 output

IDECS1n

IDE

8ma

IDE Chip Select 1 output

DIORn

IDE

8ma

IDE Read strobe output

DIOWn

IDE

8ma

IDE Write strobe output

DMACKn

IDE

8ma

IDE DMA acknowledge output

IORDY

IDE

IDE ready input

CVDD

Power

Digital power, 1.8V

RVDD

Power

Digital power, 3.3V

CGND

Ground

Digital ground

RGND

Ground

Digital ground

Table S. Pin Descriptions (Continued)

Pin Name

Block

Pad

Type

Pull

Type

Description

DS515PP7

EP9312
Universal Platform SOC Processor

Table T

illustrates the pin signal multiplexing and configuration options.

Table T. Pin Multiplex Usage Information

Physical

Pin Name

Description

Multiplex signal name

COL[7:0]

GPIO

GPIO Port D[7:0]

ROW[7:0]

GPIO

GPIO Port C[7:0]

EGPIO[0]

Ring Indicator Input

EGPIO[1]

1Hz clock monitor

CLK1HZ

EGPIO[2]

IDE DMA request

DMARQ

EGPIO[3]

Transmit Enable output / HDLC clocks

TENn / HDLCCLK1 / HDLCCLK3

EGPIO[4]

I2S Transmit Data 1

SDO1

EGPIO[5]

I2S Receive Data 1

SDI1

EGPIO[6]

I2S Transmit Data 2

SDO2

EGPIO[7]

DMA Request 0

DREQ0

EGPIO[8]

DMA Acknowledge 0

DACK0

EGPIO[9]

DMA EOT 0

DEOT0

EGPIO[10]

DMA Request 1

DREQ1

EGPIO[11]

DMA Acknowledge 1

DACK1

EGPIO[12]

DMA EOT 1

DEOT1

EGPIO[13]

I2S Receive Data 2

SDI2

EGPIO[14]

PWM 1 output

PWMOUT1

EGPIO[15]

IDE Device active / present

DASP

ABITCLK

I2S Serial clock

SCLK

ASYNC

I2S Frame Clock

LRCK

ASDO

I2S Transmit Data 0

SDO0

ASDI

I2S Receive Data 0

SDI0

ARSTn

I2S Master clock

MCLK

SCLK1

I2S Serial clock

SCLK

SFRM1

I2S Frame Clock

LRCK

SSPTX1

I2S Transmit Data 0

SDO0

SSPRX1

I2S Receive Data 0

SDI0

IDEDA[2:0]

GPIO

GPIO Port E[7:5]

IDECS0n

GPIO

GPIO Port E[4]

IDECS1n

GPIO

GPIO Port E[3]

DIORn

GPIO

GPIO Port E[2]

DD[7:0]

GPIO

GPIO Port H[7:0]

DD[15:12]

GPIO

GPIO Port G[7:4]

SLA[1:0]

GPIO

GPIO Port G[3:2]

EEDAT

GPIO

GPIO Port G[1]

EECLK

GPIO

GPIO Port G[0]

DS515PP7

EP9312

Universal Platform SOC Processor

Acronyms and Abbreviations

The following tables list abbreviations and acronyms
used in this data sheet.

Units of Measurement

Term

Definition

ADC

Analog-to-Digital Converter

ALT

Alternative

AMBA

Advanced Micro-controller Bus Architecture

ATAPI

ATA Packet Interface

CODEC

COder / DECoder

CRC

Cyclic Redundancy Check

DAC

Digital-to-Analog Converter

DMA

Direct-Memory Access

EBUS

External Memory Bus

EEPROM Electronically Erasable Programmable Read Only Memory

EMAC

Ethernet Media Access Controller

FIFO

First In / First Out

FIQ

Fast Interrupt Request

FLASH

Flash memory

GPIO

General Purpose I/O

HDLC

High-level Data Link Control

I/F

Interface

Inter-IC Sound

Integrated Circuit

ICE

In-Circuit Emulator

IDE

Integrated Drive Electronics

IEEE

Institute of Electronics and Electrical Engineers

IrDA

Infrared Data Association

IRQ

Standard Interrupt Request

ISO

International Standards Organization

JTAG

Joint Test Action Group

LFSR

Linear Feedback Shift Register

MII

Media Independent Interface

MMU

Memory Management Unit

OHCI

Open Host Controller Interface

PHY

Ethernet PHYsical layer interface

PIO

Programmed I/O

RISC

Reduced Instruction Set Computer

SDMI

Secure Digital Music Initiative

SDRAM

Synchronous Dynamic RAM

SPI

Serial Peripheral Interface

SRAM

Static Random Access Memory

STA

Station - Any device that contains an IEEE

802.11

conforming Medium Access Control (MAC) and physical
layer (PHY) interface to the wireless medium

TFT

Thin Film Transistor

TLB

Translation Lookaside Buffer

USB

Universal Serial Bus

Symbol

Unit of Measure

degree Celsius

Hertz = cycle per second

Kbps

Kilobits per second

kbyte

Kilobyte

kHz

KiloHertz = 1000 Hz

Mbps

Megabits per second

MHz

MegaHertz = 1,000 kHz

microAmpere = 10

-6

Ampere

microsecond = 1,000 nanoseconds = 10

-6

seconds

milliAmpere = 10

-3

Ampere

millisecond = 1,000 microseconds = 10

-3

seconds

milliWatt = 10

-3

Watts

nanosecond = 10

-9

seconds

picoFarad = 10

-12

Farads

Volt

Watt

Term

Definition

DS515PP7

EP9312
Universal Platform SOC Processor

Ordering Information

The order numbers for the device are:

EP9312-CB

C to +70

352-pin PBGA

EP9312-CBZ

C to +70

352-pin PBGA

Lead Free

EP9312-IB

-40

C to +85

352-pin PBGA

EP9312-IBZ

-40

C to +85

352-pin PBGA

Lead Free

EP9312 -- CBZ

Product Line:
Embedded Processor

Part Number

Temperature Range:
C = Commercial Version

Package Type:
B = 352-Ball, Plastic Ball Grid Array (27 mm x 27 mm)

Note:

Go to the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative.

I = Industrial Operating Version

Z = Lead Free

Lead Material:

E = Extended Operating Version

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find one nearest you go to

www.cirrus.com

IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries

("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS

IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that infor-

mation being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including

those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information

as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing

this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights.

Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization

with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or

promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY

OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIR-

CRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE

SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY

AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRAN-

TIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF

THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY

SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY,

INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, MaverickCrunch, MaverickKey, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this doc-

ument may be trademarks or service marks of their respective owners.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
Microwire is a trademark of National Semiconductor Corp. National Semiconductor is a registered trademark of National Semiconductor Corp.
Texas Instruments is a registered trademark of Texas Instruments, Inc.
Motorola and SPI are registered trademarks of Motorola, Inc.
LINUX is a registered trademark of Linus Torvalds.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: EP9312-EBZ

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: EP9312-EBZ